SPI SLAVE PRIMITIVE MODEL

Introduction

The SPI slave primitive model implements the popular synchronous serial communication interface named SPI (Motorola). It provides a simple interface between a serial communication SPI and two parallel buses, one for input and one for output. The width of the bus is definable (via the naming of the part) and a number of additional lines are supplied for flexibility and to simplify the interaction and synchronisation between the SPI primitive and the other model primitives.

Overview

In order to be selected the primitive must be exercised with a CS (Chip select) digital signal which is active low by default. The serial data (SI) is then sampled on the positive edge of serial clock (SCKL) and pushed off one bit up into the shift register on the negative SCKL edge.

Following the first-in first-out basic scheme the first bit which has been received (generally the MSB) will be available on serial output (SO) n+1 edges later, where ‘n’ is the width of the internal shift register. The SO information can be used for ‘cascading’ several devices which share same CS and SCLK.

In addition to the two serial lines two parallel busses are included to allow for parallel I/O. These are discussed in more detail below.

See also

Schematic Parts and Pin Descriptions

Modes of Operation

Model Properties

Creating Additional Schematic Parts

This help file last modified 16th April 2010.


Creating Additional Schematic Parts

To create a new schematic primitive part

  1. Place an existing primitive part (for example SPI_8) and use the decompose command on the Library menu to break it into it’s constituent pieces.
  2. Edit the DI[0..n-1] bus pin by right clicking and then left clicking on the pin.
  3. Rename the part such that the scope of the bus is as required. For example, DI[0..3] for a 4-bit bus.
  4. Repeat the process with the DO[0..n-1] bus pin.
  5. Invoke the Make Device command from the Library Menu and name the part according to the width of the bus. In our example therefore, we would name the part SPI_4. Note that this naming convention is vital in order for the primitive part to work correctly during simulation.


MODEL PROPERTIES

The model properties for the SPI primitive can all be accessed from the Edit Component dialogue for the schematic part. A short description of each property is given below :

The Edit Component Dialogue for the SPI_8 Schematic Part

Clock Polarity

Clock Phase

Data Order

This setting defines how the data is to be interpreted and therefore latched on the DI bus – either MSB first or LSB first.

DI Bus Output Autoload

When enabled the DI bus is written ‘automatically’ when the internal shift register is empty (provided the CS line is still active). This differs for the normal mode where the DI bus is written when the CS pin becomes inactive.

Advanced Properties

These properties can be used to introduce or specify delay periods for transmission to the serial out (SO) pin.


Modes of Operation

This section details the operation of the SPI primitive and, in particular, the way in which the parallel busses are latched according to which mode the primitive is in.

Normal Mode

In normal mode, the data is latched on DI[0..n-1] bus when CS returns inactive. This feature is widely employed by several devices and therefore is the default mode. Once the data is on DI[0..n-1] the line output DI_RDY (data input ready) is set on the negative SCKL edge and cleared on the next positive SCKL edge. This makes it easier to synchronise the associated circuitry using the data latched on the bus on either the negative or the positive edge of DI_RDY.

The output pin EMPTY is brought high when the internal shift register has been fully shifted of n places, where n is taken from primitive name. EMPTY pin is cleared on next positive SCKL edge. Aside from the EMPTY pin signalling this condition, no other actions are taken in normal mode.

Autoload Mode

Unlike normal mode, when the DI bus is written on positive CS edge, the DI bus is written when the internal shift register has gone fully empty, or when the DI bus has been full shifted n places (where n is the size of the bus). This happens provided that CS is still active.

As with normal mode the output pin EMPTY is brought high on the negative SCLK edge as usual. However, in autoload mode this also serves to indicate that a valid data is written onto the DI output bus and the EMPTY pin is cleared on the next positive SCKL edge.

The EMPTY signal has precedence in the case where the shift register is emptied at the same time as the CS pin is returned inactive.

See the section on model properties for information on selecting auto-load mode

Parallel Input

The SPI primitive provides an input bus, DO[0..n-1], which can be used to read from associated circuitry a valid data word on the assertion of the input pin DO_LE (data output latch enable). This data is then sent to the serial output SO on the negative SCKL edge.

The input pin DO_LE should be asserted high on the negative SCKL edge and the read data word is sent to SO output on the next negative SCKL edge.

In all of the above modes you can specify the data order for the data (MSB first or LSB first. See the section on model properties for more information.


Schematic Parts and Pin Descriptions

Schematic Parts

Two schematic parts are supplied as standard, one with an 8-bit wide bus and the other with a 16-bit bus. These are shown below :

See the section on creating additional parts for details on drawing new schematic primitives for use with the SPI slave primitive model.

Pin Descriptions

The following information details the use of the pins on the SPI slave primitive device :

Chip Select (CS) : Input Pin – Active Low.

Used to enable sampling of input data.

Serial Clock (SCLK) : Input Pin

When chip select is active data is sampled from the serial data input line (SI) on the positive edge on the serial clock (SCKL) and pushed off one bit up into the shift register on the negative SCKL edge.

Serial Data Input (SI) : Input Pin

Receives input data.

Serial Data Output (SO) : Output Pin

Transmits output data. The first input bit received will be available on serial output (SO) n+1 clock active edges later , where ‘n’ is the width of the internal shift register. This information can be used for ‘

cascading’ several devices which share same CS and SCLK. This pin is tristated when the CS pin is inactive.

Data Input Received (DI[0..n-1]) : Output Bus

This is the Data output bus where ‘n’ is taken from the naming of the schematic primitive. The operation of this bus is dependant on the mode of operation

Normal Mode :

The Data Input bus is written with the last n bits received when the CS pin is released and remains active for as long as CS is released. When the CS is re-asserted the DI bus is tristated, the internal state machine is reset and the cycle is restarted.

Autoload Mode :

The Data Input Bus is written as soon as n bits are received (that is, co-incedent with the EMPTY pin being asserted). This is then persistent until the CS pin is toggled off and back on again.

Data output to be sent (DO[0..n-1]) : Input Bus

This bus receives parallel input data.

Shift Register Empty Flag (EMPTY) : Output Pin

This pin is brought high when n bits have been received from the DI pin, where n is taken from primitive name and then cleared on the next positive SCKL edge. In autoload mode this pin is brought high on the negative SCLK edge as usual but is used to indicate that a valid data is written onto the DI output

Data Input Ready (DI_RDY) : Output Pin

This pin is set on the negative SCLK edge following data being latched on DI[0..n-1] and cleared on the subsequent positive edge. This allows you to synchronise any associated circuitry which can use the data latched on the bus on either the negative or the positive edge of DI_RDY.

Data Output Latch Enable (DO_LE) : Input Pin

Used to latch data from the DO[0..n-1] input bus - data is read on the assertion of this line and then sent to SO on the subsequent negative edge of SCLK. The bit order of the data word which were been read from DO bus and sent to SO can be set via the SPI_DORD property.