INTRODUCTION

Introduction & Contents

Introduction

The MSP430 series model models the behaviour of the following microcontrollers from Texas Instruments™:

MSP430C1101, MSP430C1111, MSP430C1121, MSP430F1101, MSP430F1111, MSP430F1121, MSP430F2001, MSP430F2011, MSP430F2101, MSP430F2111, MSP430F2121, MSP430F2131, MSP430F2112, MSP430F2122, MSP430F2132, MSP430F2232, MSP430F2252, MSP430F2272, MSP430F233, MSP430F235, MSP430F247, MSP430F248, MSP430F249, MSP430F2330, MSP430F2350, MSP430F23570, MSP430F2410, MSP430F2416, MSP430F2417, MSP430F2418, MSP430F2419, MSP430F2471, MSP430F2481, MSP430F2491.

MSP430G2444, MSP430G2544, MSP430G2744, MSP430G2001, MSP430G2101, MSP430G2111,MSP430G2153, MSP430G2201, MSP430G2203, MSP430G2210, MSP430G2211, MSP430G2213,

MSP430G2233, MSP430G2253, MSP430G2303, MSP430G2313, MSP430G2333, MSP430G2353, MSP430G2403, MSP430G2413, MSP430G2433, MSP430G2453, MSP430G2513, MSP430G2533,

MSP430G2553, MSP430G2755, MSP430G2855, MSP430G2955

Please check the Texas Instruments website (www.ti.com/msp430) for datasheets, the latest information and errata on particular devices.

See also

Getting Started

Model Properties (Alphabetical Index)

Explanation of Warning Messages

Run Time Disassembler

Model Limitations

Model Properties

This help file last modified 30th January 2015


EXPLANATION OF WARNING MESSAGES

The MSP430 model may issue a warning message when it detects illegal or ambiguous behaviour. The display of these messages is controlled by the Configure Diagnostics command on the Debug Menu in ISIS.

An alphabetical list of all warnings issue by the model are listed below.

Read into address <Address> is rejected: recipient doesn't exist. (PC = 0xFFD0)

Read operation try access to the invalid address of linear address space. Check a datasheet of the device, section “Memory organization” for the range of each memory block.

Write into address <Address> is rejected: recipient doesn't exist. (PC = 0xFFD0)

Write operation try access to the invalid address of linear address space. Check a datasheet of the device, section “Memory organization” for the range of each memory block.


GETTING STARTED

The following is a summary of a typical workflow using an MSP430 compiler and Proteus VSM for MSP430:

  1. Start a new project and select a supported MSP430 variant on the firmware page. This will pick and place the mcu on the schematic where you can place and wire the rest of your design. Remember that external clock circuitry is not required for simulation so you can edit the components in the crystal circuitry and check the ‘exclude from simulation’ option.
  2. Use compiler configuration dialogue in VSM Studio to automatically set up your toolchain and then write the controlling firmware in your tool of choice.
  3. Compile the firmware from the build menu in VSM Studio.
  4. Run the simulation, test, debug and experiment! See the main help documentation for more information.


MODEL LIMITATIONS

The following is a list of the current limitations of the model.

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Comparator A :

Analog pins do not output reference voltage to the outer scheme.

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Comparator A+:

Bit CASHORT is not modeled.

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Bootstrap Loader :

Not present at this time.

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FLASH:

Memory contents are not preserved after simulation.

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Supply Voltage Supervisor:

Not present at this time. POR and PUC are not modeled. Processor just starts with appropriate delay (see datasheet).

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Clock Module:

There is no frequency checking of LFXT1. You can set any value at your own risk. External Rosc influence for DCO is not modeled.

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ADC 10-Bit:

The pin ADC10SR which controls conversion rate and power consumption is not modeled.

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ADC 12-Bit:

The TAG_ADC12_1 Calibration TLV structure is not implemented.

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Universal Serial Communication Interface, UART Mode:

IrDA data exchange is not modeled. The state of the bit UCIREN = 1 is ignored.

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Generic:

- Auxiliary pins for device programming and test (TDI, TDO, TCLK, TMS, TEST, etc.) are not modeled.

- UBROF8 object file format doesn’t allow inspect variables now.


MODEL PROPERTIES

The following is a complete list of all properties supported by the MSP430 model:

Program File

Frequency MCLK

Frequency SMCLK

Frequency ACLK

Disassemble Binary Code


Model Properties (Alphabetical Index)

MODEL PROPERTY INDEX

The MSP430 model can be configured via a number of properties, described below.

Not all properties may be applicable for a given device and only those properties that are meaningful for a particular device will be shown on that device’s Edit Component dialogue form.

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Dialogue Form Field : Program File

Default Value : (None)

Units/Type : Filename

Applies To Devices : All

This property specifies the name of the program file that will be loaded into the model. The file can be in Intel Hex (.HEX), IAR UBROF-8 (.D90), GNU ELF (.ELF) or CCE COFF(.COF). The file extension must be specified as this is used to determine the format of the program file. If you are working with VSM Studio, the process will happen automatically when you compile your firmware.

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Dialogue Form Field : Frequency MCLK

Default Value : 0

Units/Type : Hertz

Applies To Devices : All

This property specifies the main clock frequency of the processor. For reasons of efficiency, you can set this parameter to an appropriate value other than 0, but if you do modifying registers of the Clock Module will not affect the frequency.

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Dialogue Form Field : Frequency SMCLK

Default Value : 0

Units/Type : Hertz

Applies To Devices : All

This property specifies the main clock frequency of the processor. For reasons of efficiency, you can set this parameter to an appropriate value other than 0, but if you do modifying registers of the Clock Module will not affect the frequency.

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Dialogue Form Field : Frequency ACLK

Default Value : 0

Units/Type : Hertz

Applies To Devices : All

This property specifies the alternate clock frequency of the processor. For reasons of efficiency, you can set this parameter to appropriate value other than 0, but in this case modifying registers of the Clock Module will not affect this frequency.

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Dialogue Form Field : Disassemble Binary Code

Default Value : No

Units/Type : Boolean

Applies To Devices : All

This property controls the behaviour of the internal disassembler. It can be useful if you want to trace library code or inspect code flow (every instruction) since processor started. If this feature is disabled and the user starts debugging the program will run until the first source line. By contrast, with this feature enabled, the execution will stop at the first instruction following Power-Up-Clear.


RUNTIME DISASSEMBLER

The MSP430 series model includes a run-time disassembler. The model disassembles the current instruction (that is, the instruction at the current value of PC, the next instruction to be executed) and displays the disassembly at the top of its ‘Registers’ pop-up.

The disassembler evaluates addresses using the opcodes under PC and reconstructs assembler mnemonic using human-readable format. For example:

bis.b #40, &BCSCTL1 -- assembler instruction

BCSCTL1 = 0x000057 -- address of the register

It is highly recommended that you supply the CCE COFF (*.COF) file to the schematic part as this enables high/low level debugging and variables display. Source level debugging (although not variables) is also available via the IAR UBROF-8 (.D90) file format. The simulation will run with a HEX file but naturally no debugging is available.+