Introduction

PROSPICE MODEL PARAMETERS

This help file contains context sensitive help for simulator primitives provided by PROSPICE.

Whilst you can browse it using the table of contents on the left, you will also find that the topics are directly linked to the components with the ASIMMDLS and DSIMMDLS libraries.

To access the help for a component already on the schematic, edit it by pointing at it and pressing CTRL-E, and then click the Help button at the bottom left.


Capacitor Model

The Capacitor Model - CAPACITOR

This is a pure device. Lead resistance, inductance and leakage are not modelled.

The capacitor model supports the following properties:

Property Default Description

PRECHARGE - Initial capacitor voltage. This property is a PROSPICE specific extension to standard SPICE. If the property is not specified, the capacitor's initial voltage is taken from the operating point.

IC - Initial capacitor voltage, useable only if initial DC solution is not computed.


Current Source Model

The Current Source Model - CSOURCE

Although it is really a generator, the current source is included here because it is a fundamental primitive in circuit simulation.

The current source has no properties save for its value.

See Also:

  • Arbitary Controlled Current Source
  • Current Controlled Current Source Model
  • Non-Linear Current Controlled Source
  • Non-Linear Voltage Controlled Current Source
  • Voltage Controlled Current Source Model


The Lossless Delay Line Model

The Lossless Delay Line Model - TRANLINE

This delay line models the action of a loss-less transmission line. Only one propagating mode is modelled. If all four nodes are distinct in the actual circuit, then two delay lines may be used to model two propagating modes. Either a frequency and normalized length or a time delay can be specified.

The lossless delay line model has the following properties and defaults:

Property | Default | Description
Z0 | - | Characteristic impedance
F | 1GHz | Frequency
TD | - | Transmission delay
NL | 0.25 | Normalized length at frequency given
V1 | 0 | Initial voltage at end 1
V2 | 0 | Initial voltage at end 2
I1 | 0 | Initial voltage at end 1
I2 | 0 | Initial current at end 2

See Also:

  • Lossy Delay Line Model
  • Uniform RC Transmission Line Model


The Lossy Delay Line Model

The Lossy Delay Line Model - LOSSYLINE

The uniform RLC/RC/LC/RG transmission line model (referred to as the LOSSYLINE model henceforth) models a uniform constant-parameter distributed transmission line. The RC and LC cases may also be modelled using the TRANLINE and URCLINE models; however, the newer LOSSYLINE model is usually faster and more accurate than the others. The operation of this mode model is based on the convolution of the transmission line’s impulse responses with its inputs.

The lossy delay line model has the following properties and defaults:

Property | Default | Description
V1 | - | Initial voltage at end 1
V2 | - | Initial voltage at end 2
I1 | - | Initial voltage at end 1
I2 | - | Initial voltage at end 2
R | - | Resistance per metre
L | - | Inductance per metre
G | - | Conductance per metre
C | - | Capacitance per metre
LEN | - | length of line
REL | 1.0 | Relative rate of change of derivative for breakpoint.
ABS | 1.0 | Absolute rate of change of derivative for breakpoint.
NOCONTROL | TRUE | No timestep control
STEPLIMIT | TRUE | Always limit timestep to 0.8*(delay of line)
NOSTEPLIMIT | TRUE | Don't always limit timestep to 0.8*(delay of line)
LININTERP | TRUE | Use linear interpolation
QUADINTERP | TRUE | Use quadratic interpolation
MIXEDINTERP | TRUE | Use linear interpolation if quadratic results look unacceptable
TRUNCNR | FALSE | Use N-R iterations for step calculation
TRUNCDONTCUT | FALSE | don't limit timestep to keep impulse response errors low
COMPACTREL | RELTOL | special reltol for straight line checking
COMPACTABS | ABSTOL | special abstol for straight line checking

The following types of lines have been implemented so far: RLC (uniform transmission line with series loss only), RC (uniform RC line), LC (lossless transmission line), and RG (distributed series resistance and parallel conductance only). Any other combination will yield erroneous results and should not be tried. The length LEN of the line must be specified.

NOSTEPLIMIT is a flag that will remove the default restriction of limiting time-steps to less than the line delay in the RLC case. NOCONTROL is a flag that prevents the default limiting of the time-step based on convolution error criteria in the RLC and RC cases. This speeds up simulation but may in some cases reduce the accuracy of results. LININTERP is a flag that, when specified, will use linear interpolation instead of the default quadratic interpolation for calculating delayed signals. MIXEDINTERP is a flag that, when specified, uses a metric for judging whether quadratic interpolation is not applicable and if so uses linear interpolation; otherwise it uses the default quadratic interpolation. TRUNCDONTCUT is a flag that removes the default cutting of the time-step to limit errors in the actual calculation of impulse-response related quantities. COMPACTREL and COMPACTABS are quantities that control the compaction of the past history of values stored for convolution. Larger values of these lower accuracy but usually increase simulation speed. These are to be used with the TRYTOCOMPACT simulator option. TRUNCNR is a flag that turns on the use of Newton-Raphson iterations to determine an appropriate timestep in the timestep control routines. The default is a trial and error procedure by cutting the previous timestep in half. REL and ABS are quantities that control the setting of breakpoints.

The option most worth experimenting with for increasing the speed of simulation is REL. The default value of 1 is usually safe from the point of view of accuracy but occasionally increases computation time. A value greater than 2 eliminates all breakpoints and may be worth trying depending on the nature of the rest of the circuit, keeping in mind that it might not be safe from the viewpoint of accuracy. Break-points may usually be entirely eliminated if it is expected the circuit will not display sharp discontinuities. Values between 0 and 1 are usually not required but may be used for setting many breakpoints.

COMPACTREL may also be experimented with when the option TRYTOCOMPACT is specified as a simulator control option. The legal range is between 0 and 1. Larger values usually decrease the accuracy of the simulation but in some cases improve speed. If TRYTOCOMPACT is not specified, history compaction is not attempted and accuracy is high. NOCONTROL, TRUNCDONTCUT and NOSTEPLIMIT also tend to increase speed at the expense of accuracy.

See Also:

  • Lossyless Delay Line Model
  • Uniform RC Transmition Line Model


Uniform RC Transmission Line Model

Uniform RC Transmission Line Model - URCLINE

The URC model is derived from a model proposed by L. Gertzberrg in 1974. The model is accomplished by a subcircuit type expansion of the URC line into a network of lumped RC segments with internally generated nodes. The RC segments are in a geometric progression, increasing toward the middle of the URC line, with K as a proportionality constant. The number of lumped segments used, if not specified for the URC line device, is determined by the following formula:

The URC line is made up strictly of resistor and capacitor segments unless the ISPERL parameter is given a non-zero value, in which case the capacitors are replaced with reverse biased diodes with a zero-bias junction capacitance equivalent to the capacitance replaced, and with a saturation current of ISPERL amps per meter of transmission line and an optional series resistance equivalent to RSPERL ohms per meter.

The URCLINE model has the following properties and defaults:

Property | Default | Description
L | - | Length of transmission line
N | See Above | Number of lumps
K | 1.5 | Propagation constant
FMAX | 1e+009 | Maximum frequency of interest
RPERL | 1000 | Resistance per unit length
CPERL | 1e-012 | Capacitance per unit length
ISPERL | 0 | Saturation current per length
RSPERL | 0 | Diode resistance per length

See Also:

  • Lossyless Delay Line Model
  • Lossy Delay Line Model


The Inductor Model

The Inductor Model - INDUCTOR

This is a pure device. Lead resistance, non-linearity and saturation are not modelled. Mutual inductance is handled by property assignment and naming. A set of mutual inductors is treated in the same way as a multi-part device in ISIS. The set is all given the same name, with a colon and letter following the name (like L1:A and L1:B for example). To specify the value of the mutual inductance, the property MUTUAL_elem is added to one of the pair. Elem should be the element designation letter from the other inductor, and the value specifies the coupling coefficient between them. For example:

L1:A, MUTUAL_B=0.5

L1:B

specifies two inductors with a coupling coefficient of 0.5. The coupling coefficient must be between 0 and 1.

The samples files MUTUAL1.DSN and MUTUAL2.DSN demonstrate this further.

You cannot connect two inductors in parallel, or an ideal voltage source directly across an inductor - the inductor has zero resistance so infinite current would flow, or in practice the simulator will report a singular matrix.

The inductor model has the following properties:

IC - Initial current through the inductor. This property only has effect when the initial DC solution is not computed.

MUTUAL_elem - The coupling coefficient between this and the referenced inductor


The Analogue Resistor Model

The Analogue Resistor Model - RESISTOR

The resistor, like the current source, is a fundamental primitive. Temperature dependence is modelled by two parameters, used to define the first and second temperature coefficients, as in the following equation:

The resistor model has the following properties:

Property | Default | Description
TC1 | 0.0 | The value A in the above expression.
TC2 | 0.0 | The value B in the above expression.
TEMP | 27 | Actual temperature of resistor.
TNOM | 27 | Temperature at which TC1, TC2 were measured.

See Also:

  • The Digital resistor Model


The Voltage-Controlled Voltage Source Model

The Voltage-Controlled Voltage Source Model - VCVS

The voltage controlled current source is a fundamental primitive used by SPICE. Its output is a voltage that is its value multiplied by the voltage on its input.

The voltage-controlled voltage source has one property:

Property | Default | Description
GAIN | 1.0 | The Voltage Gain of the Device
IC | - | Initial condition of controlling source

The GAIN parameter may also be given in the device value field.

See Also:

  • The Arbitrary Controlled Source Models
  • The Current-Controlled Voltage Source Model


The Voltage-Controlled Current Source Model

The Voltage-Controlled Current Source Model - VCCS

The voltage controlled current source is a fundamental primitive used by SPICE. Its output is a current that is its value multiplied by the voltage on its input.

The voltage-controlled current source has two properties:

Property | Default | Description
GAIN | 1.0 | The transconductance of the device.
IC | - | Initial condition of controlling source

The GAIN parameter may also be given in the device value field.

See Also:

  • The Arbitrary Controlled Source Models
  • The Current-Controlled Current Source Model
  • Current Source Model
  • The Non-Linear Current Controlled Current Source
  • The Non-Linear Voltage Controlled Current Source


The Current-Controlled Voltage Source Model

The Current-Controlled Voltage Source Model - CCVS

The current controlled voltage source is a fundamental primitive used by SPICE. Its output is a voltage that is its value multiplied by the current flowing through its input pins, or through the current probe or voltage source specified by the PROBE property.

The current-controlled voltage source has three properties:

Property | Default | Description
GAIN | 1.0 | The transresistance of the device.
PROBE | - | The name of any voltage source or current probe.
IC | - | Initial condition of controlling source.

The GAIN parameter may also be given in the device value field.

See Also:

  • The Arbitrary Controlled Source Models
  • The Voltage-Controlled Voltage Source Model


The Current-Controlled Current Source Model

The Current-Controlled Current Source Model - CCCS

The current controlled voltage source is a fundamental primitive used by SPICE. Its output is a current that is its value multiplied by the current flowing through its input pins, or through the current probe or voltage source specified by the PROBE property.

The current-controlled current source has three properties:

Property | Default | Description
GAIN | 1.0 | The current gain of the device.
PROBE | - | The name of any voltage source or current probe
IC | - | Initial condition of controlling source

The GAIN parameter may also be given in the device value field.

See Also:

  • The Arbitrary Controlled Source Models
  • Current Source Model
  • The Non-Linear Voltage Controlled Current Source
  • The Non-Linear Current Controlled Current Source
  • The Voltage-Controlled Current Source Model


The Arbitrary Controlled Source Models

The Arbitrary Controlled Source Models - AVS, ACS

The arbitrary controlled voltage and current source models provide an extremely powerful modelling facility. The output of these devices is determined by a symbolic expression which can act upon any number of input voltages and currents.

The following devices in ASIMMDLS.LIB are based on these models:

AVCVS, AVCCS, ACCVS, ACCCS, SUMMER, MULTIPLIER.

The expression is entered into the value field of the device, or if more characters are required, you can use an explicit assignment to the VALUE property.

Voltage input values are referred to as V(A), V(B), V(C) etc. within the expression, these values referring to the voltages at pins named A, B, C. The form V(A,B) is also supported, this meaning the differential voltage between pins A and B.

Current input values are referred to as I(A,B) where this value represents the current flowing into pin A and out of pin B. Once a pair of pins are used for current measurement, they will have zero resistance between them.

The expression evaluation supports the following mathematical functions:

abs acos acosh asin asinh atan atanh cos

cosh exp limit ln log pwr pwrs sgn

sin sinh sqrt stp tan u uramp

The limit function takes three arguments and returns y for x<y, z for x>z and x otherwise. The pwr function takes two parameters and evaluates to |x | raised to the power of y whilst pwrs returns |x|^y for x >= 0 and -|x|^y for x < 0. These two functions are extensions to standard SPICE3F5 which we have added for better compatibility with PSPICE™.

The u or stp function is the unit step function, with a value of one for arguments greater than one and a value of zero for arguments less than zero. The function uramp is the integral of the unit step; uramp(x) returns a value of zero for x < 0 and x for x > 0. These functions can be used to synthesize piece-wise non-linear transfer functions, although convergence problems may arise at the switching points.

The following standard operators are supported:

+ - * / ^

The expression x^y raises x to the power of y and is an alternative to the pwr function.

If the argument to log, ln or sqrt becomes negative, the absolute value of the argument is used. If a divisor or argument to ln or log becomes zero, this is an error and the simulation will fail..

A value for time can be created by connecting a current source in parallel with a capacitor, and setting the initial condition to zero.

This ramp voltage can then be used inside sin, cos etc. to create FM generators, VCOs and many other functional models.

Note that the arbitrary controlled source primitives do not, of themselves, implement timestep control. This can lead to the simulator missing rapid ‘transitions’ of the output function. Two work-arounds exist:

  • Set the maximum timestep option TMAX, to a sufficiently small value.
  • Connect two diodes back to back in series across the generator outputs. This (bizarre) approach introduces timestep control via the diodes without changing the circuit behaviour.

We hope to implement proper timestep control for arbitrary sources in a future release, although these models use Berkeley’s code so it will be tricky modification to implement!

See Also

  • The Current-Controlled Current Source Model
  • The Current-Controlled Voltage Source Model
  • Current Source Model
  • Non-Linear Current Controlled Source
  • Non-Linear Voltage Controlled Current Source
  • Voltage Controlled Current Source Model
  • Voltage Controlled Voltage Source Model


The Analogue Diode Model

The Analogue Diode Model - DIODE

The SPICE3F5 diode model is capable of modelling all types of diode including zener and varactor types.

The diode model has the following parameters:

Property | Default | Description
OFF | - | Initially off
IC | - | Initial device voltage
TEMP | 27 | Instance temperature
AREA | 1 | Area factor
IS | 1e-014 | Saturation current
RS | 0 | Ohmic resistance
N | 1 | Emission Coefficient
TT | 0 | Transit Time
CJO | 0 | Junction capacitance
VJ | 1 | Junction potential
M | 0.5 | Grading coefficient
EG | 1.11 | Activation energy
XTI | 3 | Saturation current temperature exp.
KF | 0 | Flicker noise coefficient
AF | 1 | Flicker noise exponent
FC | 0.5 | Forward bias junction fit parameter
BV | ∞ | Reverse breakdown voltage
IBV | 1mA | Current at reverse breakdown voltage
TNOM | 27 | Parameter measurement temperature

The dc characteristics of the diode are determined by the parameters IS and N. An ohmic resistance, RS, is included. Charge storage effects are modelled by a transit time, TT, and a non-linear depletion layer capacitance which is determined by the parameters CJO, VJ, and M. The temperature dependence of the saturation current is defined by the parameters EG, the energy and XTI, the saturation current temperature exponent. The nominal temperature at which these parameters were measured. Reverse breakdown (zener behaviour) is modelled by an exponential increase in the reverse diode current and is determined by the parameters BV and IBV (both of which are positive numbers).

IS, RS and CJO are scaled by the area factor.

See Also:

  • Digital Diode Model


The Bipolar Transistor Models

The Bipolar Transistor Models - NPN, PNP

The NPN and PNP transistors can operate with 3 or 4 pins, depending on whether a substrate connection is used - PROSPICE detects automatically how many pins have been drawn.

The bipolar junction transistor model in SPICE is an adaptation of the integral charge control model of Gummel and Poon. This modified Gummel-Poon model extends the original model to include several effects at high bias levels. The model automatically simplifies to the simpler Ebers-Moll model when certain parameters are not specified. The parameter names used in the modified Gummel-Poon model have been chosen to be more easily understood by the program user, and to reflect better both physical and circuit design thinking.

The bipolar transistor models have the following properties:

Property | Default | Description
OFF | - | Device initially off
ICVBE | - | Initial B-E voltage
ICVCE | - | Initial C-E voltage
AREA | 1 | Area factor
TEMP | 27 | instance temperature
IS | 1e-016 | Saturation Current
BF | 100 | Ideal forward beta
BR | 1 | Ideal reverse beta
IKF | ∞ | Forward beta roll-off corner current
IKR | ∞ | reverse beta roll-off corner current
NF | 1 | Forward emission coefficient
NR | 1 | Reverse emission coefficient
ISE | 0 | B-E leakage saturation current
ISC | 0 | B-C leakage saturation current
NE | 1.5 | B-E leakage emission coefficient
NC | 2 | B-C leakage emission coefficient
RE | 0 | Emitter resistance
RC | 0 | Collector resistance
RB | 0 | Zero bias base resistance
RBM | RB | Minimum base resistance at high currents
IRB | ∞ | Current for base resistance=(rb+rbm)/2
VAF | ∞ | Forward Early voltage
VAR | ∞ | Reverse Early voltage
VJE | 0.75 | B-E built in potential
VJC | 0.75 | B-C built in potential
VJS | 0.33 | Substrate junction built in potential
MJC | 0.33 | B-C junction grading coefficient
MJE | 0.33 | B-E junction grading coefficient
MJS | 0 | Substrate junction grading coefficient
CJC | 0 | Zero bias B-C depletion capacitance
CJE | 0 | Zero bias B-E depletion capacitance
CJS | 0 | Zero bias C-S capacitance
TF | 0 | Ideal forward transit time
TR | 0 | Ideal reverse transit time
XTF | 0 | Coefficient for bias dependence of TF
VTF | ∞ | Voltage giving VBC dependence of TF
ITF | 0 | High current dependence of TF
PTF | 0 | Excess phase
XCJC | 1 | Fraction of B-C cap to internal base
XTB | 0 | Forward and reverse beta temp. exp.
EG | 1.11 | Energy gap for IS temp. dependency
XTI | 3 | Temp. exponent for IS
FC | 0.5 | Forward bias junction fit parameter
KF | 0 | Flicker Noise Coefficient
AF | 0 | Flicker Noise Exponent
TNOM | 27 | Parameter measurement temperature

The dc model is defined by the parameters IS, BF, NF, ISE, IKF, and NE which determine the forward current gain characteristics, IS, BR, NR, ISC, IKR, and NC which determine the reverse current gain characteristics, and VAF and VAR which determine the output conductance for forward and reverse regions. Three ohmic resistances RB, RC, and RE are included, where RB can be high current dependent.

Base charge storage is modelled by forward and reverse transit times, TF and TR, the forward transit time TF being bias dependent if desired, and non-linear depletion layer capacitances which are determined by CJE, VJE, and MJE for the B-E junction, CJC, VJC, and MJC for the B-C junction and CJS, VJS, and MJS for the C-S (Collector-Substrate) junction. The temperature dependence of the saturation current, IS, is determined by the energy-gap, EG, and the saturation current temperature exponent, XTI. Additionally base current temperature dependence is modelled by the beta temperature exponent XTB in the new model.

The values specified are assumed to have been measured at the temperature TNOM.


The JFET Transistor Models

The JFET Transistor Models - NJFET, PJFET

The JFET model is derived from the FET model of Shichman and Hodges.

The JFET models have the following properties:

Property | Default | Description
OFF | - | Device initially off
IC-VDS | - | Initial D-S voltage
IC-VGS | - | Initial G-S voltage
AREA | 1 | Area factor
TEMP | 27 | Instance temperature
VT0 | -2 | Threshold voltage
BETA | 0.0001 | Transconductance parameter
LAMBDA | 0 | Channel length modulation parameter.
IS | 1e-014 | Gate junction saturation current
RD | 0 | Drain ohmic resistance
RS | 0 | Source ohmic resistance
CGS | 0 | Zero bias G-S junction capacitance
CGD | 0 | Zero bias G-D junction capacitance
PB | 1 | Gate junction potential
FC | 0.5 | Forward bias junction fit parameter
B | 1 | Doping tail parameter
KF | 27 | Flicker Noise Coefficient
AF | 27 | Flicker Noise Exponent
TNOM | 27 | Parameter measurement temperature

The dc characteristics are defined by the parameters VTO and BETA, which determine the variation of drain current with gate voltage, LAMBDA, which determines the output conductance, and IS, the saturation current of the two gate junctions. Two ohmic resistances, RD and RS, are included. Charge storage is modelled by non-linear depletion layer capacitances for both gate junctions which vary as the -1/2 power of junction voltage and are defined by the parameters CGS, CGD, and PB.

The parameters BETA, RD, RS CGS, CGD and IS are scaled by the AREA factor.


The MOSFET Transistor Models

The MOSFET Transistor Models - NMOSFET, PMOSFET

SPICE3F5 implements some 7 different MOSFET models

As follows:

Level | Name | Description
1 | MOS1 | Shichman-Hodges
2 | MOS2 | Vladimirescu and Liu (Berkeley MOS2)
3 | MOS3 | Vladimirescu and Liu (Berkeley MOS3)
4 | BSIM1 | Original BSIM model
5 | BSIM2 | New BSIM model
6 | MOS6 | Sakurai and Newton
7 | BSIM3 | Latest BSIM 3.3. model

These models can be called up explicitly using the PRIMITIVE property or using the LEVEL property with a generic model. For example

PRIMITIVE=ANALOG,NMOSFET

LEVEL=5

and

PRIMITIVE=ANALOG,NBSIM2

both call up an N type BSIM2 model. PMOS devices would be selected by referring to PMOSFET or PBSIM2.

Why two schemes? This is essentially to retain backward compatibility with native SPICE input files. Levels 1-3 date back to SPICE2, and all modern variants of SPICE should support them. Levels 4-6 are part of the ‘standard’ SPICE3F5 package from Berkeley, and we and some others have added the latest BSIM3 model as level 7.

Unfortunately, P-SPICE™ allocates different models to the levels above 4, so complete incompatibility will result if you try to use such models with PROSPICE. The only work-around is to manually check the SPICE .MODEL scripts to see if MOSFET levels above 3 are used. In practice, this will be relatively uncommon as the later models are intended exclusively for IC design work.

When entering your own models for PROSPICE, we strongly suggest that you specify the primitive type explicitly.

The MOSFET models are designed to operate with four connections - Drain (D), Gate, (G) Source (S) and Bulk Substrate (B). If the substrate pin is omitted, PROSPICE will automatically connect the source and substrate together.

All SPICE the MOSFET models are focused towards IC design, and for this reason many of the model properties are specified in terms of the physical dimensions of the drain, gate, source etc. The idea is that the same model can be used if the manufacturing geometries are changed globally. In particular, the L, W, AD, and AS properties will follow the simulator control properties DEFL, DEFW, DEFAD and DEFAS if not specified on the device. None of this is terribly helpful if you are just wanting to model discrete MOSFETs, but we have to stick with this scheme in order to retain compatibility with native SPICE models.

The temperature specification is ONLY valid for level 1, 2, 3, and 6 MOSFETs, not for level 4 , 5 or 7 (BSIM) devices.

MOSFET models

The MOSFET models MOS1, MOS2, MOS3 and MOS6 have the following properties:

Property | Default | Description
L | DEFL | Length
W | DEFW | Width
AD | DEFAD | Drain diffusion area
AS | DEFAS | Source diffusion area
PD | 0 | Drain perimeter
PS | 0 | Source perimeter
NRD | 1 | Drain squares
NRS | 1 | Source squares
OFF | - | Device initially off
ICVDS | - | Initial D-S voltage
ICVGS | - | Initial G-S voltage
ICVBS | - | Initial B-S voltage
TEMP | 27 | Instance operating temperature
LEVEL | 1 | Model Index
VTO | 0 | Threshold voltage
KP | 2.00E-05 | Transconductance parameter
GAMMA | 0 | Bulk threshold parameter
PHI | 0.6 | Surface potential
LAMBDA | 0 | Channel-length modulation (MOS1 & MOS2 only)
IS | 1.00E-14 | Bulk junction saturation current
RD | 0 | Drain ohmic resistance
RS | 0 | Source ohmic resistance
CBD | 0 | Zero bias B-D junction capacitance
CBS | 0 | Zero bias B-S junction capacitance
PB | 0.8 | Bulk junction potential
CGSO | 0 | Gate-source overlap capacitance per meter channel width.
CGSO | 0 | Gate-drain overlap capacitance per meter channel width.
CGBO | 0 | Gate-bulk overlap capacitance per meter channel length.
KF | 0 | Flicker noise coefficient
AF | 1 | Flicker noise exponent
RSH | 0 | Sheet resistance
CJ | 0 | Bottom junction cap per sq. meter of junction area
MJ | 0.5 | Bottom grading coefficient
CJSW | 0 | Side junction cap per meter of junction perimeter
MJSW | 0.33 | Side grading coefficient
JS | 0 | Bulk junction. saturation current per sq. meter of junction area
TOX | 0.1um | Oxide thickness
LD | 0 | Lateral diffusion
UO | 600cm2/Vs | Surface mobility
UCRIT | 10000V/cm | Critical field for mobility degradation (MOS2 only)
UEXP | 0 | Critical field exponent in mobility degradation (MOS2 only)
VMAX | 0 | Maximum carrier drift velocity
NEFF | 1 | Total channel charge coefficient.
FC | 0.5 | Coefficient for forward bias depletion capacitance formula
NSUB | 0 | Substrate doping
NSS | 0 | Surface state density
NFS | 0 | Fast surface state density
TPG | 0 | Gate type: 0=Al Gate, +1=opp to substrate; -1=same as substrate
XJ | 0 | Metallurgical Junction depth
XD | 0 | Depletion layer width
ALPHA | 0 | Alpha
ETA | 0 | Vds dependence of threshold voltage (MOS3 only)
DELTA | 0 | Width effect on threshold voltage (MOS2 and MOS3 only)
THETA | 0 | Vgs dependence on mobility
KAPPA | 0.2 | Kappa (MOS3 only)
TNOM | 27 | Parameter measurement temperature

L and W are the channel length and width, in meters. AD and AS are the areas of the drain and source diffusions, in square meters. Note that the suffix U specifies microns (1e-6 m) and P square microns (1e-12m2 ). If any of L, W, AD, or AS are not specified, default values are used, as discussed above. PD and PS are the perimeters of the drain and source junctions, in meters. NRD and NRS designate the equivalent number of squares of the drain and source diffusions; these values multiply the sheet resistance RSH for an accurate representation of the parasitic series drain and source resistance of each transistor. PD and PS default to 0.0 while NRD and NRS to 1.0. OFF indicates an (optional) initial condition on the device for dc analysis.

The dc characteristics of the MOSFETs are defined by the device parameters VTO, KP, LAMBDA, PHI and GAMMA. These parameters are computed by SPICE if process parameters (NSUB, TOX, ...) are given, but user-specified values always override. VTO is positive (negative) for enhancement mode and negative (positive) for depletion mode N-channel (P-channel) devices. Charge storage is modelled by three constant capacitors, CGSO, CGDO, and CGBO which represent overlap capacitances, by the non-linear thin-oxide capacitance which is distributed among the gate, source, drain, and bulk regions, and by the non-linear depletion-layer capacitances for both substrate junctions divided into bottom and periphery, which vary as the MJ and MJSW power of junction voltage respectively, and are determined by the parameters CBD, CBS, CJ, CJSW, MJ, MJSW and PB. Charge storage effects are modelled by the piecewise linear voltages-dependent capacitance model proposed by Meyer. The thin-oxide charge-storage effects are treated slightly different for the LEVEL=1 model. These voltage-dependent capacitances are included only if TOX is specified in the input description and they are represented using Meyer’s formulation.

There is some overlap among the parameters describing the junctions, e.g. the reverse current can be input either as IS (in A) or as JS (in A/m2 ). Whereas the first is an absolute value the second is multiplied by AD and AS to give the reverse current of the drain and source junctions respectively. This methodology has been chosen since there is no sense in relating always junction characteristics with AD and AS entered on the device line; the areas can be defaulted. The same idea applies also to the zero-bias junction capacitances CBD and CBS (in F) on one hand, and CJ (in F/m 2 ) on the other. The parasitic drain and source series resistance can be expressed as either RD and RS (in ohms) or RSH (in ohms/sq.), the latter being multiplied by the number of squares NRD and NRS input on the device line.

A discontinuity in the MOS level 3 model with respect to the KAPPA parameter has been detected and fixed in SPICE versions 3F2 and later. Since this fix may affect parameter fitting, the simulator control option "BADMOS3" may be set to use the old implementation.

BSIM models

The BSIM models stem from separate Berkeley research group from the one that created SPICE, although the two projects are closely related. The idea behind BSIM was to create a MOSFET model that could be generated automatically from information related to the manufacturing processes for a particular IC type. As such the lists of parameters are both long and extremely obscure - even by the standards of the above documentation!. Therefore, we have taken the view that there is no point listing them out here.

More information about the BSIM project including full documentation may be found at

http://www-device.eecs.berkeley.edu/~bsim3

or in the specialist literature related to SPICE3.

BSIM3 is developed by the Device Research Group of the Department of of Electrical Engineering and Computer Science, University of California, Berkeley and copyrighted by the University of California.


The MESFET Transistor Models

The MESFET Transistor Models - NMESFET, PMESFET

These two primitives implement models for N and P type GaAs FETs using the model of Statz et al.

Property | Default | Description
AREA | 1 | Area factor
OFF | - | Device initially off
ICVDS | - | Initial D-S voltage
ICVGS | - | Initial G-S voltage
VT0 | -2 | Pinch-off voltage
VT0 | 2 | Saturation voltage parameter
BETA | 0.0025 | Transconductance parameter
LAMBDA | 0 | Channel length modulation parameter
B | 0.3 | Doping tail extending parameter
RD | 0 | Drain ohmic resistance
RS | 0 | Source ohmic resistance
CGS | 0 | G-S junction capacitance
CGD | 0 | G-D junction capacitance
PB | 1 | Gate junction potential
IS | 1e-014 | Junction saturation current
FC | 0.5 | Forward bias junction fit parameter
KF | 0.5 | Flicker noise coefficient
AF | 0.5 | Flicker noise exponent

The dc characteristics are defined by the parameters VTO, B, and BETA, which determine the variation of drain current with gate voltage, ALPHA, which determines saturation voltage, and LAMBDA, which determines the output conductance. Two ohmic resistances, RD and RS, are included. Charge storage is modelled by total gate charge as a function of gate-drain and gate-source voltages and is defined by the parameters CGS, CGD, and PB.

The parameters BETA, B, ALPHA, RD, RS CGS, and CGD are scaled by the AREA factor.


The Non-Linear Voltage Controlled Current Source

The Non-Linear Voltage Controlled Current Source - NLVCIS

This primitive is similar to the linear primitive already mentioned. The device exists specifically to retain compatibility with the POLY sources of SPICE 2G, which were dropped in SPICE3. The output current is given by:

where f() is an arbitrary polynomial function, VA is the first controlling voltage, VB is the second controlling voltage, and so on. The device needs to have a pair of pins for each of its controlling inputs, and a pair of pins for the output current source. The number of controlling inputs, or the order of the polynomial function, must be specified by the property POLY. The coefficients of the polynomial are given by properties which consist of the appropriate letters prefixed with 'C', for example:

CABB=3.3

means the VAVB2 coefficient equals 3.3.

By connecting a resistor in parallel with the output, a voltage-controlled voltage source may be modelled. This is facilitated by the RPARA property.

The non-linear voltage controlled current source has the following properties:

Property | Default | Description
POLY | - | Polynomial Order (number of controlling inputs)
RPARA | 0 | Parallel output resistor
Cxx | - | Coefficient (as described above)
VALUE | 0 | The D.C. coefficient.

See Also:

  • The Arbitrary Controlled Source Models
  • The Current-Controlled Current Source Model
  • Current Source Model
  • The Non-Linear Voltage Controlled Current Source
  • The Voltage Controlled Current Source Model


The Non-Linear Current Controlled Current Source

The Non-Linear Current Controlled Current Source - ICISOURCE

This is similar to the NLVCIS, but the output is controlled by one or more current probes, or batteries. Each probe must be specified by the property PROBEx, where x is the letter used in the coefficient expressions as above. For example:

POLY=2

PROBEA=IPR1

PROBEB=IPR2

CAB=1

specifies a current source whose output is the product of the currents flowing in current probes IPR1 and IPR2. Note that only BATTERY or IPROBE primitives may be specified in PROBEx properties.

Current controlled current sources have the following properties:

Property | Default | Description
POLY | - | Polynomial Order (number of controlling inputs)
RPARA | 0 | Parallel output resistor
Cxx | - | Coefficient (as described above)
VALUE | 0 | The DC coefficient
PROBEx | - | The required current probe, where x is the appropriate letter
PROBE | - | This is synonymous with PROBEA

See Also:

  • The Arbitrary Controlled Source Models
  • The Current-Controlled Current Source Model
  • Current Source Model
  • The Non-Linear Voltage Controlled Current Source
  • The Voltage Controlled Current Source Model


The Voltage Controlled Switch

The Voltage Controlled Switch Model - VSWITCH

This primitive models a relay with hysteresis. When the input voltage is less than VT-VH/2, the contact resistance is ROFF - when the voltage is greater than VT+VH/2, the contact resistance is RON. Not surprisingly, this primitive may cause convergence problems in some situations.

The voltage controlled switch has the following properties:

Property | Default | Description
ON | FALSE | Switch initially on
OFF | FALSE | Switch initially off
VT | 0 | Threshold Voltage
VH | 0 | Hysteresis Voltage
RON | 1 | Resistance of the switch when on
ROFF | 1M | Resistance of the switch when off


The Voltage Controlled Resistor

The Voltage Controlled Resistor Model - VCR

The primitive is essentially a resistor whose value is controlled by a voltage on the input pins. When the voltage is less than VOFF, the resistor is ROFF - when the voltage is greater than VON, the resistor is RON. Linear interpolation is used for voltages between VOFF and VON. Note that between these values the switch behaves as an amplifier, so beware of making VON-VOFF too small, or ROFF-RON too large. Neither RON nor ROFF may be zero.

Property | Default | Description
VON | 1 | Voltage above which the resistance is RON
RON | 1 | Minimum Resistance
VOFF | 0 | Voltage below which the resistance is ROFF
ROFF | 1M | Maximum Resistance

This primitive is equivalent to the VSWITCH in ASIM - in fact you can use the VON and VOFF properties with a VSWITCH and PROSPICE will use the VCR model instead.


The Current Controlled Switch

The Current Controlled Switch Model - CSWITCH

This primitive behaves just like the voltage controlled switch, except that a current probe is used to control the resistor. The current probe is specified by the PROBE property - the value given should be the name of an IPROBE object or a voltage source.

The current controlled switch has the following properties:

Property | Default | Description
ON | FALSE | Switch initially on
OFF | FALSE | Switch initially off
IT | 0 | Threshold Current
IH | 0 | Hysteresis Current
RON | 1 | Resistance of the switch when on
ROFF | 1M | Resistance of the switch when off
PROBE | - | The required current probe


The Current Controlled Resistor

The Current Controlled Resistor Model - CCR

This primitive behaves just like the voltage controlled resistor, except that a current probe is used to control the resistor. The current probe is specified by the PROBE property - the value given should be the name of an IPROBE object or a voltage source.

Property | Default | Description
ISW | - | Sets ION and IOFF simultaneously
ION | 1M | Current above which the switch is on
RON | 1 | Resistance of the switch when on
IOFF | 0 | Current below which the switch is off
ROFF | 1M | Resistance of the switch when off
PROBE | - | The required current probe


The Current Probe Model

The Current Probe Model - IPROBE

This primitive is normally specified by placing a current probe gadget. However, to use the current controlled primitives (ICISOURCE, CSWITCH and CCR), the name of the probe needs to be specified, and so a probe must be explicitly placed. Current probes placed from the ASIMMDLS library do not contribute to the output files in the same way the current probe gadgets do, but work in the same way.


The Standard Gate Models

The Standard Gate Models-BUFFER, INVERTER, AND, NAND, OR, NOR, XOR, XNOR

The following list gives the names and actions of the standard gate types supported by PROSPICE.

BUFFER | Asserts its Q output whenever its D input is asserted.
INVERTER | Asserts its Q output whenever its D input is not asserted.
AND_#1 | Asserts its Q output only when all its D inputs are asserted.
NAND_#1 | Asserts its Q output when any of its D inputs is not asserted.
OR_#1 | Asserts its Q output when any one of its D inputs is asserted.
NOR_#1 | Asserts its Q output when none of its D inputs are asserted.
XOR_#1 | Asserts its Q output when the number of asserted D inputs is odd. Thus for a two input gate, the model performs a normal XOR operation; for gates with more than two inputs it performs a parity-check operation.
XNOR_#1 | Asserts its Q output when the number of asserted D inputs is even. Thus for a two input gate, the model performs a normal XNOR operation; for gates with more than two inputs it performs a parity-check operation.

All gate models support the NIPS (Number of Inputs) property. This property can be used to specify a different number of input pins that are physically present. For example, a AND_4 primitive device with a NIPS=2 property assignment only ANDs together its first two input pin states - the pins D2 and D3 are ignored.

The main use of the NIPS property is where a gate is in the common output circuits of a Programmable Logic Device (PLD); if each output has a different number of product lines, the NIPS property can be used to specify the number.

Pin | Type | Pin Set | Description
D# | Input | #1 | Data Inputs
Q | Output | - | Output

Time | Type | From/To | Edge | Default
TDLHDQ | Delay | D →Q | L → H | 0
TDHLDQ | Delay | D# → Q | H → L | 0
TGQ | Glitch | Any → Q | Pulse | TDxxDQ

Property | Type | Meaning | Default | Notes
NIPS | Numeric | Number of input pins | See Note | [1]

1. The default for this property is taken from the model name.


The Boolean (Programmable) Gate

The Boolean (Programmable) Gate Model - BOOL_#1

The programmable gate uses a Boolean expression to determine its output. The expression consists of a values combined by Boolean operators. Values are either sub-expressions (enclosed in parentheses) or the letters A through to Z which represent the input pins (A represents D0, B represents D1, and so on).

By default, an input pin value evaluates TRUE if the respective pin is currently active. However input pin values may optionally be followed by a postfix operator, as follows:

+ - The value is TRUE for a positive edge at the respective pin.

- - The value is TRUE for a negative edge at the respective pin.

' - The value is TRUE if the respective pin was previously active.

Note that the terms positive edge, negative edge, active and inactive imply independence from the polarity of the respective pin. If a pin is active low (by virtue of being assigned to the standard DSIM INVERT property) then active implies the input is low whilst negative edge implies a low-to-high transition.

The following operators are supported:

! - The following term is logically-inverted.

& - The left and right terms are ANDed.

| - The left and right terms are ORed.

^ - The left and right terms are Exclusive-ORed (XORed).

Operator precedence is logical-inversion, AND, OR/XOR and evaluation takes placed from left to right. Parentheses may be used to override this as required.

For example, the expression: (A|B)&C- evaluates as TRUE only if either input pin D0 or input D1 is active and there is a negative edge at the D2 input pin.

The expression itself should be put in the gate's VALUE field. If the expression is too long to fit the actual label or you wish to hide it, you can use a property assignment of the form EXPR=expr in the component's property block - this overrides any expression in the VALUE field.

The BOOL model is slower than the standard gate models, so you should use one of those for standard Boolean operations.

Pin | Type | Pin Set | Description
D# | Input | #1 | Data Inputs
Q | Output | - | Output

Time | Type | From/To | Edge | Default
TDLHDQ | Delay | D →Q | L → H | 0
TDHLDQ | Delay | D# → Q | H → L | 0
TGQ | Glitch | Any → Q | Pulse | TDxxDQ

Property | Type | Meaning | Default | Notes
EXPR | Text | The Boolean Expression | See Note | [1]


The Delay/Buffer

The Delay/Buffer Model - DELAY_#1

The DELAY primitive model, when the enable input (EN) is active, produces a delay between events on its input and events on its output. When the enable input is inactive, events are passed without delay.

Note that the DELAY model is different from the BUFFER model in that it has no current amplifying action. In other words, if a Weak input event will result in a Weak output event.

Pin | Type | Pin Set | Description
D# | Input | #1 | Data Inputs
Q | Output | #1 | Output
EN | Input | - | Enable Delay

Time | Type | From/To | Edge | Default | Notes
DELAY | Delay | D# → Q | Any | 0 | [1]
TDLHDQ | Delay | D# → Q | L → H | 0 | [2]
TDHLDQ | Delay | D# → Q | H → L | 0 | [2]
TGQ | Glitch | Any → Q | Pulse | TDxxDQ |

1. If the DELAY property is specified then both TDLHDQ and TDHLDQ are initialised to its value.

2. If the DELAY property is not specified, and one or both of TDLHDQ and TDHLDQ is specified then TDLHDQ and TDHLDQ are initialised to these properties (if only one is specified the other is initialised to its default).

3. If neither of the DELAY, TDLHDQ or TDHLDQ properties are specified then TDLHDQ and TDHLDQ are initialised to the device's VALUE property or VALUE field.


The Tristate Buffer

The Tristate Buffer Model - TRIBUFFER

The TRIBUFFER primitive models a single tristate gate. The model has a single data input D, an output-enable input, OE and a single data output Q. Whilst the OE input is asserted, the Q output follows the D input; when the OE input is not asserted Q output is in the high-impedance state.

Pin | Type | Pin Set | Description
D | Input | - | Data Inputs
QE | Input | - | Output-Enable Input
Q | Output | - | Data Output

Time | Type | From/To | Edge | Default
TDLHDQ | Delay | D → Q | L → H | 0
TDHLDQ | Delay | D → Q | H → L | 0
TDLZOQ | Delay | OE → Q | L → Z | TDLHDQ
TDHZOQ | Delay | OE → Q | H → Z | TDHLDQ
TDZLOQ | Delay | OE → Q | Z → L | TDHLDQ
TDZHOQ | Delay | OE → Q | Z → H | TDLHDQ
TGQ | Glitch | Any → Q | Pulse | TDxxDQ


The Bi-directional Buffer

The Bi-directional Buffer Model - BIBUFFER

The BIBUFFER primitive models the behaviour of a bi-directional tristate buffer. The model has two I/O data words, A and B. When the direction control input ATOB is asserted the A pins are seen as inputs and the B pins as outputs; when the control input is not asserted, the B pins are seen as inputs and the A pins as outputs. A separate output-enable pin (OE) is provided; when asserted, the current output data pins are driven into a

Pin | Type | Pin Set | Description
D | Input | - | Data Inputs
QE | Input | - | Output-Enable Input
Q | Output | - | Data Output

Time | Type | From/To | Edge | Default
TDLHDQ | Delay | A# → B# | L → H | 0
TDHLDQ | Delay | A# → B# | H → L | 0
TDLZOQ | Delay | OE → Q | L → Z | TDLHDQ
TDHZOQ | Delay | OE → Q | H → Z | TDHLDQ
TDZLOQ | Delay | OE → Q | Z → L | TDHLDQ
TDZHOQ | Delay | OE → Q | Z → H | TDLHDQ
TGQ | Glitch | Any → Q | Pulse | TDxxDQ


The J-K Model

The J-K Model - JK

The JK primitive model sets its unlatched Q output according to the current state of its J and K select inputs. The output can be either active, inactive, the current state of its D input, or the inverse of the current state of its D input, as follows:

J K Q

F F D input

F T FALSE

T F TRUE

T T Inverted D input

Note that different behaviour can be achieved by using the INVERT property to invert the activity state of either the J and/or K inputs. A primitive device based on the model can be used when modelling larger devices that have separate J and K data inputs rather than a conventional single data input.

Pin | Type | Pin Set | Description
J | Input | - | J selector
K | Input | - | K selector
D | input | - | Data input
Q | Output | - | Data output

The JK primitive has no propagation delay or other properties.


The Pulse Generator Model

The Pulse Generator Model - PULSE

The PULSE primitive model produces both positive and negative pulses of a definable width on its Q and !Q outputs when triggered with a definable edge transition on its CLK input. A RESET input allows any current output pulse to be reset early.

When a transition occurs on the clock input, a pulse of the defined width is generated on the Q and !Q outputs. If the RETRIGGER property is defined TRUE, then a current output pulse will be extended by a second transition occurring on the CLK input. The end time of the pulse is modified to equal to time of the second transition plus the defined pulse width.

Pin | Type | Pin Set | Description
CLK | Input | - | Clock Input
RESET | Input | - | Pulse reset Input
Q | Output | - | Positive pulse Output
!Q | Output | - | inverted pulse Output

Time | Type | From/To | Edge | Default | Notes
TDCQ | Delay | CLK → Q | L → H | 0 | [1]
TDCQB | Delay | CLK → !Q | H → L | 0 | [1]
TDRQ | Delay | RESET → Q | H → L | TDCQ | [2]
TDRQB | Delay | RESET → !Q | L → H | TDCQB | [2]
TGQ | Glitch | ANY → Q | Pulse | TDCQ |
TGQB | Glitch | ANY → !Q | Pulse | TDCQB |

Property | Type | Meaning | Default | Notes
INIT | Initialisation | Initial state of Q, !Q | 1 | [3]
WIDTH | Delay | Width of Q, !Q output pulses | 1 | [1]
RETRIGGER | Boolean | Are pulses extendible | FALSE |

1. When a transition occurs on the CLK input, TDCQ is used as the delay before the Q output pulse commences and TDCQB is used as the delay before the !Q output pulse commences. The output pulses last WIDTH seconds and then reset without any further delay.

2. When a transition occurs at the RESET input any pulses on the Q or !Q outputs are reset after the respective delays.

3. Bit zero of this property corresponds to the Q output, bit one to the !Q output. A set bit indicates the output is active.


The A or B Selector Model

The A or B Selector Model - AORB_#1

The AORB model is an A-or-B input data selector. The data at the A or B inputs selected by the ASEL input is fed to the Q output.

Pin | Type | Pin Set | Description
A | Input | - | Data word A
B | Input | - | Data Word B
ASEL | Intput | - | A or B data word select
Q | Output | - | Selected Output

Time | Type | From/To | Edge | Default
TDLHDQ | Delay | A#, B# → Q# | L → H | 0
TDHLDQ | Delay | A#, B# → Q# | H → L | 0
TGQ | Glitch | Any → Q# | Pulse | TDxxDQ


The Bistable Model

The Bistable Model - BISTABLE

The BISTABLE primitive model implements a single-bit transparent latch width complementary outputs. Whilst the E (enable) input is active, data on the D is transferred to the Q and !Q outputs. The data is latched when the E input goes inactive.

Pin | Type | Pin Set | Description
D | Input | - | Data Input
E | Input | - | Latch enable Input
Q | Output | - | True Data Output
!Q | Output |  | Inverted Data Output

Time | Type | From/To | Edge | Default
TDLHDQ | Delay | D → Q | L → H | 0
TDHLDQ | Delay | D → Q | H → L | 0
TDLHEQ | Delay | E → Q | H → L | TDLHDQ
TDHLEQ | Delay | E → Q | L → H | TDHLDQ
TDLHDQB | Delay | D → !Q | H → L | TDLHDQ
TDHLDQB | Delay | D → !Q | L → H | TDLHDQ
TDLHEQB | Delay | E → !Q | H → L | TDLHDQB
TDHLEQB | Delay | E → !Q | L → H | TDHLDQB
TGQ | Glitch | Any → Q | Pulse | TDxxCQ
TGQB | Glitch | Any → !Q | Pulse | TDxxCQB

Property | Type | Meaning | Default | Notes
INIT | Initialisation | Initial state of Q, !Q | 1 | [1]

1. Bit zero of this property corresponds to the Q output, bit one to the !Q output. A set bit indicates the output is active.


The D-Type Flip-Flop Model

The D-Type Flip-Flop Model - DTFF

The DTFF primitive models the behaviour of a D-type flip-flop. The level sent on the D input is clocked to the complementary Q and !Q outputs on the positive edge of the CLK input. The model also has asynchronous overriding SET and RESET inputs that force the outputs to their respective states as long as the input is asserted. If both SET and RESET are asserted, the Q and !Q outputs are set according to the bit-encoded value of the QSANDR property.

Pin | Type | Pin Set | Description
D | Input | - | Data Input
CLK | Input | - | Clock Input
SET | Input | - | Asynchronous Preset Input
RESET | Input | - | Asynchronous reset input
Q | Output | - | Normal output
!Q | Output | - | Inverted output

Time | Type | From/To | Edge | Default
TDLHCQ | Delay | CLK → Q | L → H | 0
TDHLCQ | Delay | CLK → Q | H → L | 0
TDSQ | Delay | SET → Q | L → H | TDLHCQ
TDRQ | Delay | RESET → Q | H → L | TDHLCQ
TDLHCQ | Delay | CLK → !Q | L → H | TDLHCQ
TDHLCQ | Delay | CLK → !Q | H → L | TDHLCQ
TDSQB | Delay | SET → !Q | L → H | TDHLCQ
TDRQB | Delay | RESET → !Q | H → L | TDLHCQ
TGQ | Glitch | Any → Q | Pulse | TDxxCQ
TGQB | Glitch | Any → !Q | Pulse | TDxxCQB

Property | Type | Meaning | Default | Notes
INIT | Initialisation | Initial state of Q, !Q | 0 | [1]
QSANDR | Numeric | Q and !Q states for both SET and RESET asserted | 3 | [2]

1. INIT specifies the initial state of the Q and !Q outputs: a zero value sets Q low and !Q high, a non-zero value sets Q high and !Q low.

2. Bit zero of this property corresponds to the Q output, bit one to the !Q output. A set bit indicates the respective output is high and a reset bit indicates the respective output is low.


The Counter Model

The Counter Model - COUNTER_#1

The COUNTER primitive model provides a full-function model of an n-bit up/down counter. The model supports:

  • Up/down counting by either separate up and down clocks or by a single clock and a separate count-direction input.
  • A dual-clock counter can be achieved by connecting the UCLK clock-up input to the up clock, the DCLK clock-down input to the down clock, and setting the USEDIR property FALSE. A single clock counter with direction control can be achieved by connecting both the UCLK clock-up and DCLK clock-down inputs to the clock, connecting the CNTUP count-direction input to the direction control and setting the USEDIR property TRUE.
  • Counter initialisation via the INIT property.
  • Definable count range via the LOWER and UPPER properties - these define the lowest and highest count outputs respectively. The counter counts between the LOWER and UPPER values inclusively. Note that the INIT property is not limited by these values.
  • Definable reset value via the RESET property. When the counter is reset via the RESET input pin, the Q outputs are set to the value of the RESET property.
  • Loading of the counter's Q outputs from the D data inputs via the LOAD input pin. A synchronous or asynchronous load operation is definable via the ALOAD property.
  • Resetting of the counter's Q outputs via the RESET input pin. Synchronous or asynchronous reset is definable via the ARESET property.
  • Count enable/disable control via the CE input pin.
  • Output-enable control via the OE input pin.
  • Minimum count, maximum count, and ripple-carry outputs.
  • The minimum count (MIN) and maximum count (MAX) outputs are asserted when the counter output is at its minimum or maximum values respectively. If the USEDIR property is TRUE then the MIN output is only asserted when counting down (the CNTUP direction-control input is not asserted) and the MAX output is only asserted when counting up (the CNTUP direction-control input is asserted).
  • The ripple-carry output (RCO) is asserted when either of the above MIN or MAX outputs are asserted and the count-enable (CE) input is asserted.

The OE output-enable input only affects the output state of the model. The OE input does not have to be asserted to perform reset, load or count operations.

In the case of more than one function being selected simultaneously, the reset operation has the highest priority, followed by the load operation; given no reset or load operation and the CE input being asserted, a count operation will be performed.

Pin | Type | Pin Set | Description
UCLK | Input | - | Count-up clock input
DCLK | Input | - | Count-down clock input
CNTUP | Input | - | Count up/down direction control
CE | Input | - | Count enable
LOAD | Input | - | Load input
RESET | Input | - | Reset input
D# | Input | #1 | Load data input
Q# | Output | #1 | Count output
MIN | Output | - | Minimum count output
MAX | Output | - | Maximum count output
RCO | Output | - | Ripple-carry output

Time | Type | From/To | Edge | Default | NOTES
TDLHCQ | Delay | CLK → Q# | L → H | 0 |
TDHLCQ | Delay | CLK → Q# | H → L | 0 |
TDLHXR | Delay | ANY → RCO | L → H | TDLHCQ | [1]
TDHLXR | Delay | ANY → RCO | H → L | TDHLCQ | [1]
TDLHER | Delay | CE → RCO | L → H | TDLHXR | [1]
TDHLER | Delay | CE → RCO | H → L | TDHLXR | [1]
TDLHDR | Delay | CNTUP → RCO | L → H | TDLHXR | [1]
TDHLDR | Delay | CNTUP → RCO | H → L | TDHLXR | [1]
TDLHXF | Delay | ANY → FLAGS | L → H | TDLHCQ | [2]
TDHLXF | Delay | ANY → FLAGS | H → L | TDHLCQ | [2]
TDLHDF | Delay | D → FLAGS | L → H | TDLHXF |
TDHLDF | Delay | D → FLAGS | H → L | TDHLXF |
TDLHRQ | Delay | RESET → Q# | L → H | TDLHCQ | [3]
TDHLRQ | Delay | RESET → Q# | H → L | TDHLCQ | [3]
TDLHLQ | Delay | LOAD → Q# | L → H | TDLHCQ | [3]
TDHLLQ | Delay | LOAD → Q# | H → L | TDHLCQ | [3]
TDLHDQ | Delay | D# → Q# | L → H | TDLHLQ |
TDHLDQ | Delay | D# → Q# | H → L | TDHLLQ |
TDLZOQ | Delay | OE → Q# | L → H | TDLHCQ |
TDHZOQ | Delay | OE → Q# | H → L | TDHLCQ |
TDZLOQ | Delay | OE → Q# | Z → L | TDHLCQ |
TDZHOQ | Delay | OE → Q# | Z → H | TDLHCQ |
TGQ | Glitch | ANY→ ANY | PULSE | TDxxCQ |

Property | Type | Meaning | Default | Notes
ARESET | Boolean | Asynchronous RESET? | FALSE |
ARESET | Boolean | Asynchronous LOAD? | FALSE |
USEDIR | Boolean | Use CNTUP input? | FALSE | [4]
INIT | Initialisation | Initial count value | 0 |
LOWER | Numeric | Minimum count value | 0 | [5]
UPPER | Numeric | Maximum count value | 2n-1 | [5]
RESET | Numeric | Reset output value | LOWER | [6]

1. The RCO output has a propagation delay of TDLHDR/TDHLDR when CNTUP count direction is changed and the USEDIR property is set, TDLHER/TDHLER when the CE enable input is changed, and TDLHXR/TDHLXR for all other changes. See also note [4].

2. The MIN/MAX outputs have a propagation delay of TDLHDF/TDHLDF when CNTUP count direction is changed and the USEDIR property is set, and TDLHXF/TDHLXF for all other changes. See also note [4].

3. The LOAD to Q time is used on LOAD going active (with a clock edge for a synchronous load); the D to Q time is used for a change in the input data whilst LOAD is already active.

4. When the USEDIR property is set TRUE the up/down clock edges are gated with the state of the CNTUP pin to determine whether the counter is clocked or not, and the MIN/MAX outputs are also gated such that MIN is active only when counting down, and MAX when counting up.

5. Counter outputs are LOWER to UPPER inclusive. The default value for the UPPER is set at 2n-1, where n is the number of D inputs and Q outputs defined in the device name.

6. When the counter is reset via its RESET pin, the outputs are set to the value of the RESET property. This value defaults to the value of the LOWER property, which itself defaults to zero.


The Divide by N Model

The Divide by N Model - DIVIDER

The DIVIDER primitive models a divide by N frequency divider. The division ratio (N) is defined as a component property and the Q output changes state on every N'th clock edge unless the reset (RST) is active. In this case, Q is force to the inactive state.

Pin | Type | Pin Set | Description
CLK | Input | - | Clock Input
RST | Input | - | Asynchronous reset input
Q | Output | - | Normal output

Time | Type | From/To | Edge | Default
TDCQ | Delay | CLK → Q | Both | 0
TDRQ | Delay | RST → Q# | Both | 0
TGQ | Glitch | ANY → Q | Pulse | 0

Property | Type | Meaning | Default
RATIO | Numeric | Division Ratio | 2


The Latch Model

The Latch Model - LATCH_#1

The LATCH model primitive implements an edge-triggered or transparent data latch with an asynchronous reset input and tristate outputs.

For an edge-triggered latch (the EDGE property is set TRUE) data at the D input is latched to the Q output on the positive edge of the CLK input providing the EN enable input is asserted. The Q outputs do not change whilst the CLK input is steady, on a negative CLK input edge or when the EN input is inactive. Note that, unlike simple external gating, toggling the EN enable input with the clock active produces does not produce spurious clock edges.

For a transparent latch, the Q output follows the D input whilst the CLK input and EN enable input are asserted. The output is latched when on the negative edge of either the CLK or EN input and remains latched whilst the CLK and EN inputs are not asserted.

When asserted, the asynchronous RESET input resets the latch data to zero. The Q output is enabled by the OE input; when asserted the Q output drives the current latch data, when not asserted the Q output is in the high impedance state. The OE output-enable has no affect on the functioning of the CLK/EN/RESET inputs. Similarly, the EN enable input has no affect on the action of the RESET and OE inputs.

Pin | Type | Pin Set | Description
CLK | Input | - | Clock latch enable
EN | Input | - | Enable
RESET | Input | - | Reset
OE | Input | - | Output Enable
D# | Input | #1 | Latch data input
Q# | Output | #1 | Latch data output

Time | Type | From/To | Edge | Default
TDLHCQ | Delay | CLK → Q# | L → H | 0
TDHLCQ | Delay | CLK → Q# | H → L | 0
TDLHDQ | Delay | D# → Q # | L → H | TDLHCQ
TDHLDQ | Delay | D# → Q # | H → L | TDHLCQ
TDLZOQ | Delay | OE → Q# | L → Z | TDLHCQ
TDHZOQ | Delay | OE → Q# | H → Z | TDHLCQ
TDZLOQ | Delay | OE → Q# | Z → L | TDHLCQ
TDZHOQ | Delay | OE → Q# | Z → H | TDLHCQ
TDRQ | Delay | RESET → Q# | H → L | TDHLCQ
TGQ | Glitch | ANY → Q# | Pulse | TDxxCQ

Property | Type | Meaning | Default
INIT | Initialisation | Initial latch value | 0
EDGE | Boolean | Edge triggered latch? | FALSE


The Shift Register Model

The Shift Register Model - SHIFTREG_#1

The SHIFTREG primitive model implements the functionality of a parallel/serial-in parallel/serial-out shift register. The model features:

  • Shift up/down control via a CLK input and the shift direction control UP input.
  • Register initialisation via the INIT property.
  • Loading of the register's Q outputs from the D data inputs via the LOAD input pin. A synchronous or asynchronous load operation is definable via the ALOAD property.
  • Resetting of the register's Q outputs via the RESET input pin. Synchronous or asynchronous reset is definable via the ARESET property.
  • Shift enable/disable control via the HOLD input pin.
  • Output-enable control via the OE input pin.
  • Serial data inputs, DL and DU. When a shift up operation occurs, the less significant bits are moved one place up into the next more significant bit and the least-significant bit is loaded from the DL input. When a shift down operation occurs, the more significant bits are moved one place down into the next less significant bit and the most-significant bit is loaded from the DU input.

Serial data outputs, QL and QU. The QL output is the same as the least significant bit of the parallel output data, the QU output is the same as the most significant bit of the parallel output data. Unlike the parallel data outputs, the QL and QU are not affected by the OE output-enable input and remain active whilst the parallel outputs are tristate.

The OE output-enable input only affects the output state of the model's parallel data output. The OE input does not have to be asserted to perform reset, load or shift operations, and does not affect the output states of the QU and QL outputs.

In the case of more than one function being selected simultaneously, the reset operation has the highest priority, followed by the parallel load operation; given no reset or load operation and the HOLD input not being asserted, a shift operation will be performed in the direction indicated by the UP shift direction input.

Pin | Type | Pin Set | Description
CLK | Input | - | Clock
RESET | Input | - | Data Reset
LOAD | Input | - | Data load
HOLD | Input | - | Shift-hold
UP | Input | - | Direction control
DL | Input | - | New lower data
DU | Input | - | New upper data
D# | Input | #1 | Parallel load data
Q# | Output | #1 | Data output
QL | Output | - | Lower Q output
QU | Output | - | Upper Q output

Time | Type | From/To | Edge | Default | Notes
TDLHCQ | Delay | CLK → Q | L → H | 0 |
TDHLCQ | Delay | CLK → Q | H → L | 0 |
TDLHLQ | Delay | LOAD → Q | L → H | TDLHCQ | [1]
TDHLLQ | Delay | LOAD → Q | H → L | TDHLCQ | [1]
TDHLDQ | Delay | D# → Q | H → L | TDHLCQ | [1]
TDLHDQ | Delay | D# → Q | L → H | TDLHCQ | [1]
TDLZOQ | Delay | OE → Q | L → Z | TDLHCQ |
TDHZOQ | Delay | OE → Q | H → Z | TDHLCQ |
TDZLOQ D | Delay | OE → Q | Z → L | TDHLCQ |
TDZHOQ | Delay | OE → Q | Z → H | TDLHCQ |
TDRQ | Delay | RESET → Q | H → L | TDHLCQ |
TGQ | Glitch | ANY → Q | Pulse | TDxxCQ |

Property | Type | Meaning | Default
INIT | Initialisation | Initial register contents | 0
ARESET | Boolean | Asynchronous RESET? | FALSE
ALOAD | Boolean | Asynchronous LOAD? | FALSE

1. The LOAD to Q time is used on LOAD going active (with a clock edge for a synchronous load); the D to Q time is used for a change in the input data whilst LOAD is already active.


The Decoder Model

The Decoder Model - DECODER_#1_#2

The DECODER primitive models a input-to-output data decoder. The input data is translated in to output data according to the type of decoder specified the TYPE property, as follows:

BINARY | - | A single output corresponding to the binary value at the input is asserted
BCD | - | A single output corresponding to the BCD value at the input is asserted.
7A | - | The first seven output bits are set in order to drive a seven-segment LED with the binary input value, higher value outputs remain inactive. The output is compatible with the TTL 74LS247 seven-segment driver (the numbers 6 and 9 have tails), and is illustrated below. Q0 corresponds to the segment 'a' and Q6 to segment 'g'.
7B | - | The first seven output bits are set in order to drive a seven-segment LED with the binary input value, higher value outputs remain inactive. The output is compatible with the TTL 74LS47 seven-segment driver (the numbers 6 and 9 do not have tails), and is illustrated below.
TABLE | - | The input data is translated via a user-defined table look-up. The LENGTH property indicates the size of the table, whilst table entries are defined by the properties with names TABLE0, TABLE1, TABLE2, etc. A table entry not defined is set to the value specified by the DEFAULT property, which itself defaults to zero. The WARN property, if TRUE, causes a warning to be issued (in the simulation log) for any defaulted table entry.

The EN input has higher priority to the ALL input, and the ALL input has higher priority to the D inputs. Thus:

  • When the EN enable input is inactive, all Q outputs are forced inactive.
  • When the EN and ALL inputs are active then all outputs are forced active.
  • When the EN input is active and the ALL input is inactive, the data value on the D inputs is decoded and the Q outputs driven with the decoded value. Only input values between zero and the value of the LENGTH property inclusive are decoded; values outside this range are ignored and all Q outputs will be set inactive.

Pin | Type | Pin Set | Description
EN | Input | - | Enable input.
ALL | Input | - | All outputs active, input.
D# | Input | #1 | Data input to be decoded.
Q# | Output | #2 | Data input to be decoded.

Time | Type | From/To | Edge | Default | Notes
TDLHDQ | Delay | D#, ALL → Q# | L → H | 0 | [1]
TDHLDQ | Delay | D#, ALL → Q# | H → L | 0 | [1]
TDLHEQ | Delay | EN → Q# | L → H | TDLHDQ | [1]
TDHLEQ | Delay | EN → Q# | H → L | TDHLDQ | [1]
TDLHAQ | Delay | ALL → Q# | L → H | TDLHDQ | [1]
TDHLAQ | Delay | ALL → Q# | H → L | TDHLDQ | [1]
TGQ | Glitch | ANY → Q# | Pulse | TDxxCQ | [1]

Property | Type | Meaning | Default | Notes
TYPE | Text | Type of decoder. | BINARY | [2]
LENGTH | Numeric | Table length. | 16/0 | [3]
DEFAULT | Numeric | Default table entry value. | 0 | [4]
WARN | Boolean | Warn of defaulted entries. | FALSE | [5]
TABLEn | Numeric | Value of table entry nn. | DEFAULT | [6]

1. The Q outputs have a propagation delay (in order of descending priority) of TDLHEQ/TDHLEQ when there is a transition at the EN input, TDLHAQ/TDHLAQ when there is transition at the ALL input, and TDLHDQ/TDHLDQ for all input transitions.

2. The TYPE property should be assigned one of the following keywords:

BINARY | Binary input to single output decoder.
BCD | BCD input to single output decoder.
7A | Binary input to 7-segment LED output decoder, Type A.
7B | Binary input to 7-segment LED output decoder, Type B.
TABLE | Table decoder.

3. Where TYPE is assigned TABLE, 7A or 7B, this specifies the number of entries in the table and the default property value is 0, 16 and 16 respectively. Input values that are greater than the value of the LENGTH property are ignored and all outputs will be set inactive.

4. For a TABLE type decoder, table entries not explicitly specified by a TABLEnn property are initialised to the value of this property. See also notes [5] and [6].

5. For a TABLE type decoder, if set TRUE, a warning is entered in to the simulation log for any table entries defaulted to the DEFAULT property value. See also notes [4] and [6].

6. For a TABLE type decoder, the table entries are specified via properties with the names TABLE0, TABLE1, TABLE2, etc. The highest TABLEn property should be equal to the value of the LENGTH property. Any table entry not specified is set to the value of the DEFAULT property, which itself defaults to zero. See also notes [4] and [5].


The Priority Encoder Model

The Priority Encoder Model - ENCODER_#1_#2

The ENCODER primitive models a n-input priority encoder. When the encoder input enable EI is asserted, the Q output is assigned the binary value of the highest D input asserted; if none of the D inputs are asserted, the Q output is set to zero and the enable output EO is asserted.

Pin | Type | Pin Set | Description
EI | Input | - | Enable input.
D# | Input | #1 | Data input lines
Q# | Input | #2 | Binary output.
EO | Output | - | Enable output

Time | Type | From/To | Edge | Default
TDLHDQ | Delay | D# → Q | L → H | 0
TDHLDQ | Delay | D# → Q | H → L | 0
TDLHEQ | Delay | EI → Q# | L → H | TDLHDQ
TDHLEQ | Delay | EI → Q# | H → L | TDHLDQ
TDLHDE | Delay | D# → EO | L → H | TDLHDQ
TDHLDE | Delay | D# → EO | H → L | TDHLDQ
TGQ | Glitch | ANY → Q | Pulse | TDxxDQ


The One-of-N Selector Model

The One-of-N Selector Model - SELECTOR_#1

The SELECTOR primitive models a one-of-n selector. When the EN enable input and the OE output enable are asserted, data on the D input selected by the binary value on the S input is routed to the complementary Q and !Q outputs. When the output enable input is not asserted the Q and !Q outputs are driven into the high-impedance state; when the enable input is not asserted the Q and !Q are held in their inactive states.

Pin | Type | Pin Set | Description
EN | Input | - | Selector enable
OE | Input | - | Output enable
S# | Input | #1 | Data input select value
D# | Input | - | Data inputs
Q | Input | - | True selected data output
!Q | Input | - | Inverted selected data output

Time | Type | From/To | Edge | Default
TDLHDQ | Delay | D# → Q | L → H | 0
TDHLDQ | Delay | D# → Q | H → L | 0
TDLHEQ | Delay | EN → Q | L → H | TDLHDQ
TDHLEQ | Delay | EN → Q | H → L | TDHLDQ
TDLHSQ | Delay | S# → Q | L → H | TDLHDQ
TDHLSQ | Delay | S# → Q | H → L | TDHLDQ
TDLHDQB | Delay | D# → !Q | L → H | 0
TDHLDQB | Delay | D# → !Q | H → L | 0
TDLHEQB | Delay | EN → !Q | L → H | TDLHDQB
TDHLEQB | Delay | EN → !Q | H → L | TDHLDQB
TDLHSQB | Delay | S# → !Q | L → H | TDLHDQB
TDHLSQB | Delay | S# → !Q | H → L | TDHLDQB
TDLZOQ | Delay | OE → Q | L → Z | TDLHCQ
TDHZOQ | Delay | OE → Q | H → Z | TDHLCQ
TDZLOQ | Delay | OE → Q | Z → L | TDHLCQ
TDZHOQ | Delay | OE → Q | Z → H | TDLHCQ
TDLZOQB | Delay | OE → !Q | L → Z | TDLHOQ
TDHZOQB | Delay | OE → !Q | H → Z | TDHLOQ
TDZLOQB | Delay | OE → !Q | Z → L | TDHLOQ
TDZHOQB | Delay | OE → !Q | Z → H | TDLHOQ
TGQ | Delay | ANY → Q | Pulse | TDxxCQ
TGQB | Delay | ANY → !Q | Pulse | TDxxCQB


The ALU Function Model

The ALU Function Model - FUNCTION_#1_#2

The FUNCTION model carries out a mathematical or Boolean operation on the two the input data words (A and B) and the carry input. The result is presented at the Q and COUT carry outputs.

The model supports three pre-operation functions: the NEGA input when asserted causes the word at the A inputs to be negated and similarly the NEGB input when asserted causes the word at the B inputs to be negated. Following any negation, and prior to the operation, the SWAP input, if asserted causes the A and B words to be swapped.

A particular operation is selected by asserting the relevant function input. The function operations are defined in decreasing priority as follows:

ADD | - | A plus B plus CIN.
SUB | - | A minus B minus CIN.
MUL | - | A multiplied by B.
DIV | - | A divided by B.
AND | - | A bitwise ANDed with B.
OR | - | A bitwise ORed with B.
XOR | - | A bitwise exclusive-ORed with B.
LSH | - | A left-shifted B places.
RSH | - | A right-shifted B places.

Where more than one function is selected, the highest priority function takes place. The result of the operation is incremented and/or decremented if the INC or DEC inputs are asserted.

Note that, because of internal data widths, the two input data words should not be greater than thirty-one bits each (i.e. the #1 field in the name should be less than or equal to thirty).

Pin | Type | Pin Set | Description
A# | Input | #1 | Input data word A
B# | Input | #1 | Input data word B
NEGA | Input | - | Negate data word A
NEGB | Input | - | Negate data word B
SWAP | Input | - | Swap A and B data words
ADD | Input | - | Add data words
SUB | Input | - | Subtract data words
MUL | Input | - | Multiply data words
DIV | Input | - | Divide data words
AND | Input | - | Bitwise AND data words
OR | Input | - | Bitwise OR data words
XOR | Input | - | Bitwise exclusive-OR data words
LSH | Input | - | Left shift data word
RSH | Input | - | Right shift data word
INC | Input | - | Increment operation result
DEC | Input | - | Decrement operation result
CIN | Input | - | Carry in
Q# | Output | #2 | Result output
COUT | Output | - | Carry out

Time | Type | From/To | Edge | Default | Notes
TDLHDQ | Delay | A#,B# → Q# | L → H | 0 | [1]
TDHLDQ | Delay | A#,B# → Q# | H → L | 0 | [1]
TDLHDC | Delay | A#,B#→COUT | L → H | TDLHDQ | [1]
TDHLDC | Delay | A#,B# →COUT | H → L | TDHLDQ | [1]
TDLHCQ | Delay | CIN → Q# | L → H | TDLHDQ | [1]
TDHLCQ | Delay | CIN → Q# | H → L | TDHLDQ | [1]
TDLHCC | Delay | CIN → COUT | L → H | TDLHDQ | [1]
TDHLCC | Delay | CIN → COUT | H → L | TDHLDQ | [1]
TDLHOQ | Delay | Op. → Q# | L → H | TDLHDQ | [1]
TDHLOQ | Delay | Op. → Q# | H → L | TDHLDQ | [1]
TDLHOC | Delay | Op. → COUT | L → H | TDLHDQ | [1]
TDHLOC | Delay | Op. → COUT | H → L | TDHLDQ | [1]
TGQ | Glitch | Any → Any | Pulse | TDxxDQ | [1]

Property | Type | Meaning | Default | Notes
INIT | Initialisation | Initial state of Q | 0 | [2]

1. The A# or B# to whatever times are used where either the A or B input words have changed. If these are unchanged, and the carry has changed, then the CIN to whatever times are used. If the A and B words and the carry input are unchanged, the Operation-to-whatever times are used. Op. indicates any of the operation inputs.

2. This value is only used if no operation is selected.


The Magnitude Comparator Model

The Magnitude Comparator Model - COMPARATOR_#1

The COMPARATOR primitive model sets its output flags in accordance with the magnitudes of its two input data words, A and B.

If the A and B input words are equal, the output flags are set according to which input flags are asserted. If the A=B input flag is asserted the two words are assumed equal, regardless of the other input flags. If the A=B is not asserted and only one of the A<B and A>B is asserted then the A word is assumed less than or greater than the B word respectively. If A<B and A>B inputs are both asserted or neither is asserted the ambiguity is resolved by the FBADT and FBADF properties respectively.

Pin | Type | Pin Set | Description
A<B | Input | - | A less than B input flag.
A=B | Input | - | A equal to B input flag.
A>B | Input | - | A greater than B input flag.
A# | Input | #1 | A input data word.
B# | Input | #1 | B input data word.
QA<B | Output | - | A less than B output flag.
QA<=B | Output | - | A less than or equal to B output flag.
QA=B | Output | - | A equal to B output flag.
QA>=B | Output | - | A greater than or equal to B output flag.
QA>B | Output | - | A greater than B output flag.

Time | Type | From/To | Edge | Default | Notes
TDLHDQ | Delay | A#,B# → Q# | L → H | 0 | [1]
TDHLDQ | Delay | A#,B# → Q# | H → L | 0 | [1]
TDLHDC | Delay | A#,B#→COUT | L → H | TDLHDQ | [1]
TDHLDC | Delay | A#,B# →COUT | H → L | TDHLDQ | [1]
TDLHCQ | Delay | CIN → Q# | L → H | TDLHDQ | [1]
TDHLCQ | Delay | CIN → Q# | H → L | TDHLDQ | [1]
TDLHCC | Delay | CIN → COUT | L → H | TDLHDQ | [1]
TDHLCC | Delay | CIN → COUT | H → L | TDHLDQ | [1]
TDLHOQ | Delay | Op. → Q# | L → H | TDLHDQ | [1]
TDHLOQ | Delay | Op. → Q# | H → L | TDHLDQ | [1]
TDLHOC | Delay | Op. → COUT | L → H | TDLHDQ | [1]
TDHLOC | Delay | Op. → COUT | H → L | TDHLDQ | [1]
TGQ | Glitch | Any → Any | Pulse | TDxxDQ | [1]

Property | Type | Meaning | Default | Notes
FBADF | Numeric | Output flags if A<B and A>B both FALSE | 5 | [2]
FBADT | Numeric | Output flags if A<B and A>B both TRUE | 0 | [2]


The Memory Model

The Memory Model - MEMORY_#1_#2

The MEMORY model provides a means of modelling mass-storage memory devices, such as FIFOs, RAMs, EPROMs, etc.

A write pulse is defined as the period over which both the WR write strobe and CS chip select inputs are active; the state of the RD read strobe input is ignored. The data on the D inputs is then written to the address specified by the A address inputs on at the end of a write pulse whose duration is greater than the minimum write pulse width specified by the TWWR property. Note that no address set-up time is modelled - any transitions of the A address inputs during the write pulse are ignored.

A read pulse is defined as the period over which both the RD read strobe and CS chip select inputs are active and the WR input is inactive. The D inputs are driven with the data at the memory location specified by the A address inputs throughout a valid read pulse. When no read pulse is active, the D data inputs are in a high-impedance state.

You can initialise the memory by assigning the FILE property the path and name of a disk file, followed by a comma and then the file type. For example, the assignment:

FILE=DATA.BIN,PACKED

initialised the memory with the binary data in the file DATA.BIN. If the file contains insufficient data for the memory size, then remaining memory locations will be initialised according to the presence and value of the INIT property. Currently, the file types supported by the model are:

PACKED | The file contains packed (that is, non-aligned) binary data. For example, for a six-bit wide memory, the least significant six bits of the first byte correspond to the first memory location; the remaining two bits and the least significant four bits of the second byte correspond to the least significant two and most significant four bits of the second memory location, and so on.
BINARY | The file contains binary data that is byte, word or long-word aligned. Alignment should be in accordance with the data width of the memory. For a memory with 1 to 8 bits byte alignment is expected; for a memory with 9 to 16 bits, word alignment is expected, and for a memory with 17 to 32 bits long-word alignment is expected. For word and long-word alignment the bytes should be stored little-endian (that is, least-significant byte first). For example, for a 9-bit wide memory, the least significant nine bits of the each successive word in the file corresponds the successive memory locations. The first word consists of the first (least significant) and second (most significant) bytes in the file, the second word consists of the third (least significant) and fourth (most significant) bytes in the file, and so on.
ASCDEC | The file contains ASCII decimal values, separated by one or more space, tab, or newline (carriage return and/or line feed) characters.
ASCHEX | The file contains ASCII hexadecimal values, separated by one or more space, tab, or newline (carriage return and/or line feed) characters. The hexadecimal characters can be upper or lower case.
ASCBIN | The file contains ASCII binary values, separated by one or more space, tab, or newline (carriage return and/or line feed) characters.

If no file type is given, the model will use the file extension to determine the file type:

.BIN | The file is assumed to be pure binary.
.HEX | The file is assumed to be Intel Hex.
.S19 | The file is assumed to be Motorola Hex.

In these cases, the BASE and SHIFT properties may be used to re-map addresses in the incoming file. This can be used to achieve byte splitting when 8 bit ROMs are used with 16 or 32 bit microprocessors, and also where a ROM is not at address 0 in the CPU’s memory map. For example, let us suppose you are using two 2764 (8KB) ROMs with an 8086. The HEX file will contain 16KB of data with addresses running from 0x0000 thru 0x3FFF. The first ROM will hold the even bytes and the second the odd bytes. To achieve this translation, you would assign

BASE=0

SHIFT=1

for the ‘even’ ROM, and

BASE=1

SHIFT=1

for the ‘odd’ ROM. In the case of 32 bit systems, you would use BASE values of 0,1,2,3 and assign SHIFT=2

.

The INIT property is used to initialise memory locations not initialised through any FILE property assignment, or where the data file specified in such an assignment contains insufficient data. If the property is assigned the RANDOM keyword, then uninitialised memory locations will be initialised with random data from the global random initialisation value generator. This generator can be seeded through the INITSEED Simulation Control Property.

Memory locations are always assigned from an initialisation value least-significant bit upwards for as many bits as are required by the data width of the memory.

Pin | Type | Pin Set | Description
CS | Input | - | Chip-select enable
WR | Input | - | Write strobe
RD | Input | - | Read strobe
A# | Input | #1 | Address inputs
D# | I/O | #2 | Data input or output

Time | Type | From/To | Edge | Default | Notes
TDLHAD | Delay | A# → D# | L → H | 0 | [1]
TDHLAD | Delay | A# → D# | H → L | 0 | [1]
TDLZCD | Delay | CS → D# | L → Z | TDLHAD | [1]
TDHZCD | Delay | CS → D# | H → Z | TDHLAD | [1]
TDZLCD | Delay | CS → D# | Z → L | TDHLAD | [1]
TDZHCD | Delay | CS → D# | Z → H | TDLHAD | [1]
TDLZRD | Delay | RD → D# | L → Z | TDLHAD | [1]
TDHZRD | Delay | RD → D# | H → Z | TDHLAD | [1]
TDZLRD | Delay | RD → D# | Z → L | TDHLAD | [1]
TDZHRD | Delay | RD → D# | Z → H | TDLHAD | [1]
TDLZWD | Delay | WR → D# | L → Z | TDLHAD | [1]
TDHZWD | Delay | WR → D# | H → Z | TDHLAD | [1]
TDZLWD | Delay | WR → D# | Z → L | TDHLAD | [1]
TDZHWD | Delay | WR → D# | Z → H | TDLHAD | [1]
TGQ | Glitch | Any → D# | Pulse | TDxxAD |

Property | Type | Meaning | Default | Notes
TWWR | Delay | Minimum write pulse width. | 100n | [2]
FILE | Text | Source filename for init. | See Note | [3]
BASE | Hex Value | Base address in data file | 0 |
SHIFT | Integer | No. of bits to shift file addresses. | 0 |
INIT | Initialisation | Initial value for memory. | 0 | [3]

1. These delays apply for the D# outputs when a read-pulse commences or terminates; a read pulse being defined as RD and CS active with WR inactive. For coincident changes on these or the A# inputs, the priority is (in descending order) TDxxCD, TDxxRD, TDxxAD and TDxxAD. For example: if CS is already active and RD goes active simultaneously with WR going inactive, the D# outputs will be set with a propagation delay of TDxxRD since this has a higher priority to TDxxWD. The delay TDxxAD is used when a read pulse exists and the address bus (A#) inputs change mid-pulse.

2. A memory write only occurs given a write pulse of width greater than TWWR.

3. If assigned, the FILE and INIT properties are used to initialise the MEMORY models memory. There is no default for the FILE property - if it is not assigned then no file-based memory initialisation takes place and the memory is initialised according to the INIT property.


The Digital Resistor Model

The Digital Resistor Model - RESISTOR

The RESISTOR primitive models a resistor as used in digital circuits. It provides a way to model pull-up and pull-down resistors efficiently. Use of the analogue resistor model for this purpose will incur a major performance penalty.

A strong signal of any polarity on one pin is propagated to the other with the same polarity but as a weak signal; all other signals are propagated as a floating signal.

Pin | Type | Pin Set | Description
1 | Passive | - | Resistor Leg
2 | Passive | - | Resistor Leg

See Also:

Analogue Resistor Model


The Digital Diode Model

The Digital Diode Model - DIODE

The DIODE primitive models a diode as used in digital circuits.

A strong or weak high signal on the anode pin is propagated to the cathode pin with the same strength and polarity; all other signals are propagated to the cathode as a floating signal. A strong or weak low signal on the cathode pin is propagated to the anode pin with the same strength and polarity; all other signals are propagated to the anode as a floating signal.

Pin | Type | Pin Set | Description
A | Passive | - | Anode
K | Passive | - | Cathode

See Also:

Analogue Diode Model


The Matrix Model

The Matrix Model - MATRIX_#1_#2

The MATRIX primitive model implements the functional behaviour of the AND fuse matrix found in most PLD devices, as shown below:

The matrix consists of a set of inputs and a set of outputs. Each output is driven by a product line line which, in the default state is connected to all the input lines by fuse links. The JEDEC file specifies which fuses should remain intact (input connected to output product line) or blown (input open-circuit to output product line). A given output is said to be active when all the inputs connected to its product line are also active; if any input is inactive, the output is also inactive. Thus, the output implements the logical-AND (i.e. the product term) of all its inputs.

In the above diagram, there are twelve data inputs (D0 through D11) and eight data outputs (Q0 through Q7). The output Q1 has a product line whose fuse numbers are 12 (input D0) through to 23 (input D11). If the JEDEC file specified the fuses for this line as 010101110111, this would evaluate to Q1=D0 AND D2 AND D4 AND D8.

Most PLD devices have an AND matrix fed by both the true and the complement of the input data, so allowing the output product terms to include the equivalent of a logical-NOT. In general, such devices have a matrix with twice the number of inputs as there are physical pins; the even matrix inputs then consist of the true data and the odd inputs of the inverted data. For such devices, the internal input data word is twice the width of the external data word.

You can model such PLD devices most simply by creating a MATRIX primitive with the number of inputs equal to twice the number of physical pins, and then driving the MATRIX with both true and complementary data. However, as nearly all PLDs require both true and complementary data, and as the inversion of data externally (using separate INVERTOR primitives on each data input) is non-optimum, the MATRIX primitive provides a means of producing internal data words that are twice the width of the number of model inputs and which contain both true and complementary data. This model function is controlled by the INVPINS property, as shown in the following two diagrams which relate typical PLD input stages to the property's usage within the MATRIX primitive model:

Thus, in a PLD where the even product line offsets (0, 2, etc.) are the true data and the odd product line offsets the complementary data (shown above left), you need to create a MATRIX model with the same number of inputs as there are physical pins and to specify the INVPINS=+ property. Similarly, in a PLD where the even product line offsets (0, 2, etc.) are the complementary data and the odd product line offsets the true data (shown above right), you need to create a MATRIX model with the same number of inputs as there are physical pins and to specify the INVPINS=- property. The former is by far the most common. Note that specifying the INVPINS property results in the internal data width of the MATRIX primitive being twice the width of the external (i.e. number of D# inputs) width: this must be accounted for when specifying fuse numbers (see below).

The MATRIX primitive requires fuse numbers to be specified for the first fuse in each matrix outputs product line. You can specify these fuse numbers in one of two ways. If the PLDs AND matrix has irregular fuse numbering you can use the alternative properties FUSE0, FUSE1, FUSE2, etc. to specify the number of the first fuse in the Q0, Q1 and Q2 outputs' respective product lines. For the example above, we would thus need eight property assignments, as follows:

FUSE0=0

FUSE1=12

...

FUSE7=84

Alternatively, if the product line first fuse numbers are all a fixed number apart, you can use the FUSEBASE property to specify the first product line's first fuse number and the FUSEINCR property to specify the increment to the next product line's first fuse number. For the example above, we would thus only need two property assignments, as follows:

FUSEBASE=0

FUSEINCR=12

In general, for most PLDs, the FUSEINCR property would be assigned a value equal to the width of the model's internal input data word - this will be the same as the number of D# model inputs if the INVPINS property is not specified and twice the number of D# model inputs if the INVPINS property is specified.

Note that if you specify the FUSEINCR property, then it (and the FUSEBASE property) will be used in preference to any FUSEn assignments. Further, both methods only allow you to specify the number of the first fuse for each product line: the MATRIX primitive model automatically numbers the remainder of the fuses in the product term from left to right according to the internal data width.

Pin | Type | Pin Set | Description
D# | Input | #1 | Data Inputs
Q# | Output | #2 | Data Outputs

Property | Type | Meaning | Default | Notes
FILE | Text | Name of JEDEC file. | See Note | [1]
INVPINS | Text | Generate Inverted inputs | See Note | [2]
FUSEBASE | Numeric | Fuse Number of 1st P.Line. | 0 | [3]
FUSEINCR | Numeric | Increment For Next P. Line. | See Note | [3]
FUSEn | Numeric | Number for nth P.Line. | 0 | [3]

1. The FILE property specifies the path and filename of the JEDEC file to be used for fuse values. This property must be specified - there is no default.

2. If specified, the INVPINS property causes the model to create an internal data word containing both the input data word at the D# inputs and its complement.

3. If FUSEINCR is assigned, then the FUSEBASE and FUSEINCR properties will be used to specify the first fuse numbers of each outputs product line. If not specified, then FUSEn properties will be expected instead.

See Also:

Fuse Expression Model

Fused 1-of-N Selector Model

Macro Cell Model


The Fuse Expression Model

The Fuse Expression Model - FUSE_#1

The FUSE primitive model has any number of inputs but only a single output which is determined according to the fuse expression assigned to the models EXPR property. The format of fuse expressions are described in full at the start of this chapter.

For example, the following diagram shows part of the output (post AND matrix) stage of a typical PLD. Each product line from the AND matrix can be separately enabled/disabled (via the PTn fuses). Enabled product term lines are then ORed together and the result inverted if the XOR fuse is programmed. The diagram illustrates how the fuse expression is built up for the overall function. This expression could then be assigned to the EXPR property of a FUSE input with the correct number of input pins. Note the polarity of the fuse numbers in the expression - the ones and zeros in the fuse file (which replace the fuse numbers) correspond directly with the Boolean logic required by the inputs, so the fuse numbers used are not inverted.

Pin | Type | Pin Set | Description
D# | Input | #1 | Data Inputs
Q | Output | - | Selected inputs

Property | Type | Meaning | Default | Notes
FILE | JEDEC File | Name of JEDEC file. | See Note | [1]
EXPR | Fuse Expr. | Fuse expression for the output | See Note | [2]

1. The FILE property specifies the path and filename of the JEDEC file to be used for fuse values. There is no default for this property - it must be specified. If your fuse expression doesn't contain any fuse numbers, you can avoid the need to specify a file by assigning a value of [NULL].

2. The fuse expression must be specified - there is no default.

See Also:

Fused 1-of-N Selector Model

Macro Cell Model

Matrix Model


The Fused 1-of-N Selector Model

The Fused 1-of-N Selector Model - FSEL_#1

The FSEL primitive models implements a 1-of-n selector where the selected input is determined according to one or more fuses.

The selector has two or more data inputs (D) and a single output (Q) - data at the selected input is transferred to the Q output without delay.

The number of D inputs in the primitive device must be a power of two (i.e. 2, 4, 8, 16, 32, etc.). The input selected is determined according to the combined binary value of one or more fuse expressions specified by the Sn properties (the S0 property forms the least significant bit and the Sn property the most significant bit); the number of Sn properties is thus log2 the number of inputs. The JEDEC file the fuse values are to be found in is specified by the FILE property.

The following example shows a four input FSEL primitive being used to select between one of four clock signals. The clock signal is selected according to the two-bit value formed by the Boolean values of the fuse expressions specified by the S1 (most significant bit) and S0 (least significant bit) properties. Note in particular that the S0 property is set to be the inverse of fuse 1023.

Pin | Type | Pin Set | Description
D# | Input | #1 | Data Inputs
Q | Output | - | Selected inputs

Property | Type | Meaning | Default | Notes
FILE | Text | Name of JEDEC file. | See Note | [1]
INVQ | Fuse Expr. | Invert Q output? | FALSE | [2]
Sn | Fuse Expr. | Input selected value, Bit n. | See Note | [3]

1. The FILE property specifies the path and filename of the JEDEC file to be used for fuse values. There is no default for this property - it must be specified. If none of your fuse expressions contain a fuse number, you can avoid the need to specify a file by assigning a value of [NULL].

2. The Q output is inverted if the expression assigned to this property evaluates TRUE. The expression cannot include references to input pins.

3. See main description for an explanation of these properties.

See Also:

Fuse Expression Model

Macro Cell Model

Matrix Model


The Macro-Cell Model

The Macro-Cell Model - MCELL

The MCELL primitive models implements most of the functions provided by PLD output cells. These output cells are often referred to as Macro cells due to the wide variety of functions they implement.

The MCELL macro-cell model can be used to model register, transparent latch and combinatorial output stages. The cell type is defined in the following order

1. If the REG property is assigned a fuse expression and the expression evaluates TRUE, then a registered macro-cell type is defined.

2. If the LATCH property is assigned a fuse expression and the expression evaluates TRUE, then a latched macro-cell type is defined.

3. If neither the REG or LATCH properties are assigned, or if they are their expression(s) evaluate FALSE, then a combinatorial macro-cell type is defined.

The following truth tables define, for each macro-cell type, the model behaviour when pre-loaded, clocked, asynchronously preset and/or reset, and finally, when synchronously preset and/or reset. Pin states shown in terms of positive clock edge (↑), negative clock edge (↓), active (A), inactive (I), and don't care (X) states.

Registered Macro-cell

Operation | PL | CLK | RESET | SET | Q | !Q
Preload Start | A | X | X | X | PD | !PD
Preload End | ↓ | X | X | X | PD | !PD
Async. reset | | | X | A | | | | | A
Async. preset | | | X | | | A | A | |
Async. preset and reset | | | X | A | A | QSANDR | QBSANDR
Sync. reset | | | ↑ | A | | | | | A
Sync. preset | | | ↑ | | | A | A | |
Sync. preset and reset | | | ↑ | A | A | QSANDR | QBSANDR
Clock | | | ↑ | | | | | D | !D

Latched Macro-cell

Operation | PL | CLK | RESET | SET | Q | !Q
Preload Start | A | X | X | X | PD | !PD
Preload End | ↓ | X | X | X | PD | !PD
Async. reset | | | X | A | | | | | A
Async. preset | | | X | | | A | A | |
Async. preset and reset | | | X | A | A | QSANDR | QBSANDR
Sync. reset | | | A | A | | | | | A
Sync. preset | | | A | | | A | A | |
Sync. preset and reset | | | A | A | A | QSANDR | QBSANDR
Clock | | | A | | | | | D | !D

Combinatorial Macro-cell

Operation | PL | CLK | RESET | SET | Q | !Q
Preload Start | A | X | X | X | PD | !PD
Preload End | ↓ | X | X | X | D | !D
Sync/Async. reset | | | X | A | | | | | A
Sync/Async. preset | | | X | | | A | A | |
Sync/Async.set and reset | | | X | A | A | QSANDR | QBSANDR
Clock | | | X | | | | | D | !D

For all types, the preload operation has highest precedence. Whilst the preload input is active the macro-cell outputs are forced to and follow the state of the preload data input. When the preload input returns to inactive, for register- and latch-type macro-cells the preload data state is latched at the outputs and for combinatorial-type macro-cells the outputs return to following the data (D) input.

Given no preload operation the macro-cell can be preset or reset via the preset (SET) and reset (RESET) inputs. Both these pins have independent enable (ESET and ERESET) and asynchronous (ASET and ARESET

) properties that control whether or not the input pin is used and whether or not its operation is synchronous or asynchronous with respect to the clock input (CLK). Both pins are enabled by default but can be disabled by assigning the relevant ESET or ERESET property a fuse expression that evaluates to FALSE. Similarly, both pins are synchronous in operation by default but can be made asynchronous by assigning the relevant ASET or ARESET property a fuse expression that evaluates to TRUE. If both a set and a reset operation occur simultaneously (synchronous or asynchronous) then the Q and !Q outputs are set to the Boolean states of the QSANDR and QBSANDR properties respectively.

Finally given no preload, preset or reset operations, the macro-cell can be clocked. For register-type macro-cells, the outputs Q and !Q only latch the data input (D) on a positive transition of the clock input (CLK); this is same behaviour as a D type flip-flop. For latched-type macro-cells, the outputs Q and !Q follow the data input (D) whilst the clock input (CLK) is active and latch it on the active-to-inactive transition; this is the same behaviour as a transparent latch. For combinatorial-type macro-cells, the Q and !Q outputs always follow the data input (D) regardless of the state of the clock input (CLK).

Although input/output pin states can be inverted by the standard DSIM INVERT property, the MCELL primitive model supports inversion of most of its pins via a fuse expression - see the table below for a list.

Pin | Type | Pin Set | Description
CLK | Input | - | Register clock/latch enable input
D | Input | - | Data input
RESET | Input | - | Reset input (synchronous and asynchronous)
SET | Input | - | Preset input (synchronous and asynchronous)
PL | Input | - | Preload enable input
PD | Input | - | Preload data input
Q | Output | - | True latch/register/data output
!Q | Output | - | Inverted latch/register/data output

Property | Type | Meaning | Default | Notes
FILE | Text | Name of JEDEC file. | See Note | [1]
REG | Fuse Expr. | Defines a register-type macro-cell | See Note | [2]
LATCH | Fuse Expr. | Defines a latch-type macro-cell | See Note | [2]
ARESET | Fuse Expr. | Asynchronous reset? | TRUE |
ASET | Fuse Expr. | Asynchronous set? | TRUE |
ERESET | Fuse Expr. | Enable RESET input? | See Note | [3]
ESET | Fuse Expr. | Enable SET input? | See Note | [3]
INITQ | Fuse Expr. | Initial state of Q output | NOT INITQ | [4]
INITQB | Fuse Expr. | Initial state of !Q output | TRUE | [4]
QSANDR | Fuse Expr. | Q state if SET & RESET asserted | TRUE |
QBSANDR | Fuse Expr. | !Q state if SET & RESET asserted | FALSE |
INVCLK | Fuse Expr. | Invert CLK input? | FALSE | [5]
INVPL | Fuse Expr. | Invert PL input? | FALSE | [5]
INVPD | Fuse Expr. | Invert PD input? | FALSE | [5]
INVQ | Fuse Expr. | Invert Q output? | FALSE | [5]
INVQB | Fuse Expr. | Invert !Q output? | FALSE | [5]

1. The FILE property specifies the path and filename of the JEDEC file to be used for fuse values. There is no default for this property - it must be specified. If none of your fuse expressions contain a fuse number, you can avoid the need to specify a file by assigning a value of [NULL].

2. These properties define the model behaviour. If both properties evaluate TRUE, the REG property has the higher precedence. See the main description for more details.

3. The RESET/SET inputs can be enabled/disabled via these properties. For a register-type macro-cell, the default values are TRUE; for other types the default values are FALSE.

4. These properties can be used to initialise the Q and !Q outputs for latch- and register-type macro-cells; they are ignored for the combinatorial-type macro-cell. The default for QBINIT is the logical inverse of the INITQ property, which itself defaults to FALSE.

5. These properties can be used to invert the behaviour of their respective pins. The pin behaviour is inverted if the fuse expression evaluates TRUE.

Fuse Expression Model

Fused 1-of-N Selector Model

Matrix Model


The Analogue to Digital Interface Object

The Analogue to Digital Interface Object - ADC

The ADC primitive has four pins, although in common use, a two pinned variety is often used.

Pin | Type | Description
A | Analogue Input | Input from analogue side of circuit.
D | Digital Output | Output to digital side of circuit.
V+ | Analogue Input | Positive power supply.
V- | Analogue Input S | Negative power supply.

If either the V+ or V- pins are omitted, they will be assumed to connect to VCC/VDD and GND/VSS respectively. If the no VCC/VDD net exists, then the ADC will assume that it is operating on a +5V supply unless the VOLTAGE property is specified.

The ADC primitive supports the following properties:

Property | Default | Description
VOLTAGE | 5V | Determines the voltage for ADC’s that do not have power rails.
VTL | 30% | Logic low Voltage Threshold.
VLH | 10% | Low->high hysteresis value.
VTH | 70% | Logic high Voltage Threshold.
VHH | 10% | High->low hysteresis value off.
TTOL | <TTOL> | Timing tolerance. This defaults to the global mixed mode timing tolerance if not specified.
RPOS | ∞ | Resistance from A to V+ pins
RNEG | ∞ | Resistance to A to V- pins

The VTL and VTH properties can be specified either as percentages of the power supply, or as absolute values. For example:

VTL=40%

VTH=60%

and

VTL=2.0

VTH=3.0

are equivalent for a 5V supply.

The hysteresis properties determine the levels at switch the ADC switches from undefined to low and undefined to high as opposed to low to undefined and high to undefined. If VTL, VTH are specified as percentages then VHL, VHH must be percentages too. Likewise, if VTL,VTH are given as absolute levels then VHL, VHH should also be given as levels.

Setting VHL and VHH to zero tends to cause convergence problems in some circuits.

The TTOL property determines the accuracy with which PROSPICE will determine the time of the switching points. In other words, if TTOL is set to 1us, this means that successive two analogue simulation timepoints must occur no more than 1us either side of any point at which the ADC registers a state change on its output. This property is normally defaulted to the global mixed mode timing tolerance, as set under the DSIM tab of the Simulation Options dialogue form.

An ADC object drives the digital net to which its output connects at Weak strength.

See Also:

DAC Interface Object Model

Dual Mode Switch Model


The Digital to Analogue Interface Object

The Digital to Analogue Interface Object - DAC

The DAC primitive has four pins, although in common use, a two pinned variety is often used.

Pin | Type | Description
D | Digital Input | Input from Digital side of circuit.
A | Analogue Output | Output to Analogue side of circuit.
V+ | Analogue Input | Positive power supply.
V- | Analogue Input S | Negative power supply.

If either the V+ or V- pins are omitted, they will be assumed to connect to VCC/VDD and GND/VSS respectively. If the no VCC/VDD net exists, then the DAC will become self powering - current will flow from the output round to the V- pin, or to GND if no V- pin was drawn.

The DAC primitive supports the following properties:

Property | Default | Description
VOLTAGE | 5V | Determines the operating voltage for DACs that do not have power rails.
VLO | 0% | Voltage level for high logic states - SHI, WHI.
VHI | 100% | Voltage level for low logic states - SLO, WLO.
VUD | 50% | Voltage level for undefined logic states - FLT, WUD, CON.
RLO | 1W | Output resistance for logic low states.
RHI | 1W | Output resistance for logic high states.
RUD | (RLO+RHI)/2 | Output resistance for undefined logic states.
RTS | 100MW | Output resistance for floating logic state.
TRISE | 1ns | Output rise time.
TFALL | TRISE | Output fall time
TFALL | (TRISE+TFALL)/2 | Output time to go tri-state.
RAMP | Linear | Determines the shape of the rise/fall curves.

VLO, VHI, and VUD can all be given as either percentages of the power supply or as absolute voltages, so

VLO=40%

VHI=60%

and

VLO=2.0

VHI=3.0

are equivalent for a 5V supply. The DAC actually represents its output as a current source and a resistor in parallel between the output pin at the V- pin or GND, so it is not necessary for their to be a V+ pin or a VCC net in order for DACs to output a given voltage.

To select exponential (i.e. R/C) output curves, you can specify

RAMP=EXP

on a DAC. The output will then reach approximately 0.63 of its destination value in the specified rise or fall times. This nicely models the effect of capacitor loading of the output.

The output rise and fall waveforms are only guaranteed to be simulated accurately if the global mixed mode timing tolerance (TTOL) is smaller than TRISE and TFALL. TTOL can be set on the DSIM tab of the Simulation Options dialogue form.

ADC Interface Object Model

Dual Mode Switch Model


The Dual Mode Switch Model

The Dual Mode Switch Model - DSWITCH

The DSWITCH primitive has three pins (EN, A and B), comprising a digital control input and the two terminals of the switch itself. The primitive model is dual mode in the sense that if it finds itself in a purely digital circuit it will behave as a purely digital model, but if either of the switch terminals is connected to other analogue components then the device will adopt mixed mode behaviour.

The DSWITCH primitive supports the following properties when operating as a mixed mode device.

Property | Default | Description
RON | 1 | Switch resistance when on.
ROFF | ∞ | Switch resistance when off.
TON | 0 | Time to switch on.
TOFF | 0 | Time to switch off.

When operating as a digital device, the DSWITCH will translate logic strength from strong to weak passing through it. It supports the following advanced properties which take precedence over the timing defined by TON and TOFF.

Property | Default | Description
TDLHQQ | 0 | Time delay low to high through the switch.
TDHLQQ | 0 | Time delay high to low through the switch.
TDZLEQ | 0 | Time for output to go low from hi-z on enable.
TDZHEQ | 0 | Time for output to go high from hi-z on enable.
TDLZEQ | 0 | Time for output to go hi-z from low on disable.
TDHZEQ | 0 | Time for output to go hi-z from high on disable.
TGQ | - | Glitch suppression time.

See Also:

ADC Interface Object Model.

DAC Interface Object Model.


N-Bit ADC Model

N-Bit ADC Model - ADC_#1

Description

The N-Bit ADC is a building block for use in creating schematic models of real world analogue to digital converters. The data width and resolution is determined by the part name, so an ADC_8 represents an 8 bit converter.

Pin | Type | Description
VIN | Analogue Input | Analogue voltage input.
VREF+ | Analogue Input | Positive reference voltage.
VREF- | Analogue Input | Negative reference voltage
HOLD | Analogue Input S | Positive edge transition causes sampling of analogue voltage input.
CLK | Digital Input | Positive edge transition causes update of digital output.
OE | Digital Input | Output enable for D# output pins.
D# | Digital Output | Tri-state output bus

The output value is determined by VIN, VREF+ and VREF- with the reference pins setting a valid range for the input voltage. The input voltage is sampled on a positive edge transition of the HOLD input, and transferred to the digital output register on a positive edge transition of the CLK input. Both edges may occur simultaneously, if required. The output bus is tri-state and drives data whenever the OE pin is active.

You can use the INVERT property to make any of the digital inputs active low.

Properties

The ADC model supports the following properties:

Property | Default | Description
MODE | UNSIGNED | Specifies the numerical format of the digital output. Possible values for MODE are UNSIGNED, SIGNMAGNITUDE or TWOSCOMPLEMENT.
TDLHCD | 0 | Specifies the delay between CLK and D# for a low to high transition on D#.
TDHLCD | 0 | Specifies the delay between CLK and D# for a high to low transition on D#.
TDZLOE | 0 | Specifies the delay between OE and D# for a high-Z to low transition on D#.
TDZHOE | 0 | Specifies the delay between OE and D# for a high-Z to high transition on D#.
TDLZOD | 0 | Specifies the delay between OE and D# for a low to high-Z transition on D#.
TDHZOD | 0 | Specifies the delay between OE and D# for a high to high-Z transition on D#.
TG | TDxxCD | Specifies the minimum pulse width possible on D#.


N-Bit DAC Model

N-Bit DAC Model - DAC_#1

Description

The N-Bit DAC is a building block for use in creating schematic models of real world digital to analogue converters. The data width and resolution is determined by the part name, so a DAC_8 represents an 8 bit converter.

Pin | Type | Description
D# | Digital Inputs | Digital input bus.
LE | Digital Input | A logic high on this pin allows the digital inputs to write the data register. When this pin returns low, the data is latched.
VREF+ | Analogue Input | Positive reference voltage.
VREF- | Analogue Input | Negative reference voltage.
VOUT | Analogue Output | Analogue voltage output.

The output voltage range is determined by VREF-, VREF+, with VOUT taking a value between the two in proportion to the value written to the data register. A level triggered data latch is provided via the LE pin; if LE is held high then transitions on the digital inputs will write straight through to the analogue output.

You can use the INVERT property to make any of the digital inputs active low.

Properties

The DAC model supports the following properties:

Property | Default | Description
MODE | UNSIGNED | Specifies the numerical format of the digital output. Possible values for MODE are UNSIGNED, SIGNMAGNITUDE or TWOSCOMPLEMENT
TDDA | 0 | Specifies the digital->analogue delay time. The analogue output value will start changing after this time and head for its new value at a rate determined by SLEWRATE.
SLEWRATE | 1E6 | Determines the rate in V/s at which the analogue output changes to a new value.


The Real Time Digital Probe

The Real Time Digital Probe - RTDPROBE

The RTDPROBE is used to set the state of an indicator according to the bitwise value on its input pin(s). If any pin is at the undefined or floating logic state, the invalid state (-1) is output. The pins of the ISIS device should be named D0, D1, D2 etc.

The model supports the following properties:

Name | Description | Default | Notes
ELEMENT | Target element within bitwise parent indicator. | - | bitwise parent indicator. - This property is used when the RTDPROBE is part of schematic model controlling a BITWISE indicator.


The Real Time Current Probe

The Real Time Current Probe - RTIPROBE

The RTIPROBE model is used to set the state of an indicator from a circuit current. It outputs a state value determined by the following formula:

where MIN and MAX are properties of the RTIPROBE object, and NUMSTATES is determined by the parent indicator. If the input voltage is less then MIN, then the output state is 0, and if the input voltage is greater than MAX

it is limited to NUMSTATES-1.

Fractional values are rounded to the nearest integer.

The model supports the following properties:

Name | Description | Default | Notes
MIN | Value of input voltage for state 0 | 0 |
MAX | Value of input voltage for FSD | 1 |
ELEMENT | Target element within bitwise parent indicator. | - | bitwise parent indicator. - This property is used when the RTIPROBE is part of schematic model controlling a BITWISE indicator.


The Real Time Voltage Probe

The Real Time Voltage Probe - RTVPROBE

The RTVPROBE model is used to set the state of an indicator from a circuit voltage. It outputs a state value determined by the following formula:

where MIN and MAX are properties of the RTVPROBE object, and NUMSTATES is determined by the parent indicator. If the input voltage is less then MIN, then the output state is 0, and if the input voltage is greater than MAX

it is limited to NUMSTATES-1.

Fractional values are rounded to the nearest integer.

The model supports the following properties:

Name | Description | Default | Notes
MIN | Value of input voltage for state 0 | 0 |
MAX | Value of input voltage for FSD | 1 |
LOAD | Value of optional load resistor | - |
ELEMENT | Target element within bitwise parent indicator. | - | bitwise parent indicator. - This property is used when the RTIPROBE is part of schematic model controlling a BITWISE indicator.


The Real Time Digital State Model

The Real Time Digital State Model - RTDSTATE

This model represents a multi-bit digital state selector in which the bitwise output is determined by the value of the STATE property. The output pins of the ISIS device should be named Q0, Q1, Q2 etc as necessary. Two modes of operation are supported:

Bitwise Mode

In this mode, the bitwise output is determined directly by the binary value of the STATE property. For example, a 4 bit device with STATE=10 will output Q3=1, Q2=0, Q1=1, Q0=0.

Table Mode

In this mode, the value for each state is specified by a property S(<N>). The values of these properties can be either hexadecimal values, or named logic states. If hex values are given, then these are used as bitwise values to set the output pins. If named states are given then all outputs are set to that state. The recognized named values are as follows:

SLO or 0 or F | Strong low
SHI or 1 or T | Strong high
WLO | Weak low
WHI | Weak high
FLT | Floating


The Real Time Switch Model

The Real Time Switch Model - RTSWITCH

This model represents an N-state variable resistor for which a different resistance can be specified for each state using properties R(0), R(1), R(2) etc. A further parameter TSWITCH determines the switching time from one state to another, thus avoiding discontinuities that could otherwise cause convergence problems within the SPICE simulation.

The RTSWITCH is a dual mode primitive, meaning that PROSPICE will use either an analogue model or a digital model depending on analysis of what the switch connects to. If either net the switch connects is deemed to be analogue, then the analogue model is used, otherwise the digital model is used. The digital model is open circuit for any value of R(<N>) greater than 1k and closed circuit otherwise.

The advantage of this dual mode behaviour is that active switches based around the RTSWITCH primitive can be used in either analogue or digital simulations without compromising the performance of the latter by introducing unnecessary mixed mode interfacing primitives. At the same time, the user is saved from the confusing notion of having to use specifically analogue and digital switches in order to gain optimum performance.

The model supports the following properties:

Name | Description | Default | Notes
R(<N>) | Resistance for state <N> | - | The value “OFF” may be used to indicate a true open circuit, but beware than convergence problems may arise.
TSWITCH | Switching Time | 1ms |


The JK Flip-Flop Model

The JK Flip-Flop Model - JKFF

The JKFF primitive models the behaviour of a JK-type flip flop. The complementary data outputs Q and !Q are set on the positive edge of the CLK input according to the current states of the J and K data inputs, as follows:

J K Q

F F No change

F T FALSE

T F TRUE

T T Toggled

The model also has asynchronous overriding SET and RESET inputs that force the outputs to their respective states as long as the input is asserted. If both SET and RESET are asserted, the Q and !Q outputs are set according to the bit-encoded value of the QSANDR property.

Pin | Type | Pin Set | Description
J | Input | - | J Function select input
K | Input | - | K Function Select Input
CLK | Input | - | Clock Input
SET | Input | - | Asynchronous Preset Input
RESET | Input | - | Asynchronous reset input
Q | Output | - | True output
!Q | Output | - | Inverted output

Time | Type | From/To | Edge | Default
TDLHCQ | Delay | CLK → Q | L → H | 0
TDHLCQ | Delay | CLK → Q | H → L | 0
TDSQ | Delay | SET → Q | L → H | TDLHCQ
TDRQ | Delay | RESET → Q | H → L | TDHLCQ
TDLHCQ | Delay | CLK → !Q | L → H | TDLHCQ
TDHLCQ | Delay | CLK → !Q | H → L | TDHLCQ
TDSQB | Delay | SET → !Q | L → H | TDHLCQ
TDRQB | Delay | RESET → !Q | H → L | TDLHCQ
TGQ | Glitch | Any → Q | Pulse | TDxxCQ
TGQB | Glitch | Any → !Q | Pulse | TDxxCQB

Property | Type | Meaning | Default | Notes
INIT | Initialisation | Initial state of Q, !Q | 0 | [1]
QSANDR | Numeric | Q and !Q states for both SET and RESET asserted | 3 | [2]

1. INIT specifies the initial state of the Q and !Q outputs: a zero value sets Q low and !Q high, a non-zero value sets Q high and !Q low.

2. Bit zero of this property corresponds to the Q output, bit one to the !Q output. A set bit indicates the respective output is high and a reset bit indicates the respective output is low.