INTRODUCTION

About Proteus Schematic Capture

Many CAD users dismiss schematic capture as a necessary evil in the process of creating PCB layout but we have always disputed this point of view. With PCB layout now offering automation of both component placement and track routing, getting the design into the computer can often be the most time consuming element of the exercise. And if you use circuit simulation to develop your ideas, you are going to spend even more time working on the schematic.

The ISIS schematic capture module has been created with this in mind. It has evolved over twenty years research and development and has been proven by thousands of users worldwide. The strength of its architecture has allowed us to integrate first conventional graph based simulation and with Proteus VSM - interactive circuit simulation - into the design environment. You can now draw a complete circuit for a micro-controller based system and then test it interactively, all from within the same piece of software. Meanwhile, ISIS retains a host of features aimed at the PCB designer, so that the same design can be exported for production with ARES or other PCB layout software.

For the educational user and engineering author, ISIS also excels at producing attractive schematics like you see in the magazines. It provides total control of drawing appearance in terms of line widths, fill styles, colours and fonts. In addition, a system of templates allows you to define a ‘house style’ and to copy the appearance of one drawing to another.

Other general features include:

  • Runs on Windows XP onwards.
  • Automatic wire routing and dot placement/removal.
  • Powerful tools for selecting objects and assigning their properties.
  • Total support for buses including component pins, inter-sheet terminals, module ports and wires.
  • Fully configurable Bill of Materials reporting.
  • Live netlisting to the ARES Layout module and additional netlist outputs to suit other PCB layout tools.

For the ‘power user’, Proteus capture incorporates a number of features which aid in the management of large designs. Indeed, a number of our customers have used it to produce designs containing many thousands of components.

  • Hierarchical design with support for parameterized component values on sub-circuits.
  • Full support for Assembly Variants.
  • Project clips and sub-circuit binding to enable simple, error free design re-use.
  • Design Global Annotation allowing multiple instances of a sub-circuit to have different component references.
  • Automatic Annotation - the ability to number the components automatically.
  • ASCII Data Import - .this facility provides the means to automatically bring component stock codes and costs into Proteus design or library files where they can then be incorporated or even totaled up in the Bill of Materials report.

System Requirements

Performance in ISIS is scaleable according to your computer specification. The following are the recommended minimums requirements :

  • 3.5GHz or faster Intel Pentium processor (AMD processors fine but less optimised).
  • Graphics card supporting OpenGL Version 2.0 or higher and/or Direct 2D and multi-sampling (MSAA).
  • 16Gb RAM.
  • Windows 10.

In particular, note that if your graphics card does not satisfy the above requirements the software will run in Windows GDI mode. This means that display of the screen is handled by Windows and not your graphics hardware and therefore that some features of the software will not be available.

As a general rule, manufacturer graphics cards such as ATI and NVIDEA will satisfy these requirements whilst chipset graphics such as those supplied by Intel will not.

Schematic and Layout

Users intending to design PCB's using the Proteus Layout module will find some of the following PCB layout specific features of interest:

  • The ability to assign and configure net classes directly from the place wire label command on a schematic connection. This allow you to specify trace width and via styles and feeds into the design rule manager in ARES where you can further configure board constraints.
  • Sheet Global Net Properties which allow you to efficiently define a net class for all the nets on a given sheet (e.g. a power supply needing POWER width tracks).
  • Physical terminals which provide the means to have the pins on a connector scattered all over a design.
  • Support for heterogeneous multi-element devices. For example, a relay device can have three elements called RELAY:A, RELAY:B and RELAY:C. RELAY:A is the coil whilst elements B and C are separate contacts. Each element can be placed individually wherever on the design is most convenient.
  • Live netlisting between schematic and layout modules and automatic forward and back annotation between them.
  • Support for pin-swap and gate-swap. This includes both the ability to specify legal swaps in the ISIS library parts and the ability to back-annotate changes into a schematic.
  • A visual packaging tool which shows the PCB footprint and its pin numbers alongside the list of pin names for the schematic part. This facilitates easy and error free assignment of pin numbers to pin names. In additional, multiple packagings may be created for a single schematic part.
  • A full chapter is provided on how to use ISIS and ARES together.

Schematic & Simulation

ISIS provides the development environment for PROTEUS VSM, our revolutionary interactive system level simulator. This product combines mixed mode circuit simulation, micro-processor models and interactive component models to allow the simulation of complete micro-controller based designs.

ISIS provides the means to enter the design in the first place, the architecture for real time interactive simulation and a system for managing the source and object code associated with each project. In addition, a number of graph objects can be placed on the schematic to enable conventional time, frequency and swept variable simulation to be performed.

Major features of PROTEUS VSM include:

  • True Mixed Mode simulation based on Berkeley SPICE3F5 with extensions for digital simulation and true mixed mode operation.
  • Support for both interactive and graph based simulation.
  • CPU Models available for popular microcontrollers such as the PIC, 8051, AVR and ARM series.
  • Interactive peripheral models include LED and LCD displays, a universal matrix keypad, I2C & SPI peripherals, RS232 terminal and a whole library of switches, pots, lamps, LEDs etc.
  • Virtual Instruments include voltmeters, ammeters, a dual beam oscilloscope and a 24 channel logic analyser.
  • An integrated IDE - VSM Studio - which automatically detects and configures installed compilers and will generate optimal code for debugging in Proteus VSM.
  • Active Popups within VSM Studio allow you to both view and interact with parts of the schematic from within the IDE.
  • On-screen graphing - the graphs are placed directly on the schematic just like any other object. Graphs can be maximised to a full screen mode for cursor based measurement and so forth.
  • Graph Based Analysis types include transient, frequency, noise, distortion, AC and DC sweeps and fourier transform. An Audio graph allows playback of simulated waveforms.
  • Direct support for analogue component models in SPICE format.
  • Open architecture for ‘plug in’ component models coded in C++ or other languages. These can be electrical., graphical or a combination of the two.
  • Digital simulator includes a BASIC-like programming language for modelling and test vector generation.
  • A design created for simulation can also be used to generate a netlist for creating a PCB - there is no need to enter the design a second time.

Full details of all these features and much more are provided in the PROTEUS VSM manual.

Proteus & Networks

Proteus is fully network compatible, and offers the following features to help Network Managers:

  • Library files can be set to Read Only. This prevents users from messing with symbols or devices that may be used by others.
  • ISIS individual user configuration in the windows registry. Since the registry determines the location of library files, it follows that users can have individual USERDVC.LIB files in their personal or group directories.
  • Server based licensing options.

How to Use this Documentation

This manual contains background and reference information, wile the tutorial document provides a practical walkthrough of the application and the context sensitive help provides limited information relating to commands and dialog forms. Help on most objects in the user interface can be obtained by pointing with the mouse and pressing F1.

Proteus capture is a vast and tremendously powerful piece of software and it is unreasonable to expect to master all of it at once. However, the basics of how to enter a straightforward circuit diagram and create your own components are extremely simple and the techniques required for these tasks can be mastered most quickly by following the Tutorial. We strongly recommend that you work through this as it will save you time in the long run.

With some of the more advanced aspects of the package, you are probably going to find some of the concepts are new, let alone the details of how ISIS handles them. Each area of the software has been given a chapter of its own, and we generally start by explaining the background theory before going into the operation and use of the relevant features. You will thus find it well worthwhile reading the introductory sections rather than jumping straight to the how-to bits.


SCREEN LAYOUT

The Menu Bar

Menu bar in ISIS

The Menu Bar runs across the top row of the screen and its main purpose (the selection of commands from the menus) is the same as with any other Windows application. In addition, the title bar area above the menu names is used to display certain prompt messages which indicate when the program has entered a particular editing or processing mode.

The Toolbars

As with other modern Windows applications, ISIS provides access to a number of its commands and modes through the use of toolbars. The toolbars can be dragged to any of the four edges of the ISIS application window. If you have a 4K monitor or Have your machine set to use high DPI settings, the icons will upscale automatically. If the haven't, they can be forced from the Sytem Settings command on the System Menu. You'll then need to close and open Proteus for the changes to take effect:

Command Toolbars

The tools located along the top of the screen (by default) provide alternative access to the menu commands, as follows:

TITLE | TOOLBAR
File / Project Commands |
Application Commands |
Display Commands |
Editing Commands |
Design Tools |
Assembly Variants |

If you are working on a relatively small monitor, you can hide any or all of the command toolbars using the Toolbars command on the View Menu.

Mode Selector Toolbar

The toolbar located down the left hand edge of the screen select the editor mode, i.e. what happens when you click the mouse on the Editing Window.

TITLE | TOOLBAR
Main Modes |
Gadgets |
2D Graphics |

Note that the mode toolbar cannot be hidden, as its functions are not duplicated on the menus.

Orientation Toolbar

The orientation toolbar displays and controls the rotation and reflection for objects placed onto the layout.

TITLE | TOOLBAR
Rotation |
Reflection |

The edit box allows you type a rotation angle in directly; but note that in ISIS, only orthogonal angles may be entered.

When an existing object is tagged, the Rotation and Mirror icons highlight in red to show that they will modify the orientation of an object on the layout. When the icons are not highlighted, they serve to determine the orientation for new objects.

The Editing Window

The Editing Window displays the part of the schematic that you are currently editing. The contents of the Editing Window may be redrawn using the Redraw command on the View menu. This also redraws the Overview Window. You can use this feature after any other command that has left the display somewhat untidy.

Panning

You can reposition the Editing Window over different parts of the design in several ways:

  • By clicking left at a point on the Overview Window - this re-centres the Editing Window about the marked point.
  • By clicking the middle mouse wheel on the editing window to 'pick up' the sheet and then moving the mouse to reposition the sheet. We refer to this feature as Track-Pan.

Note that you can roll the middle mouse wheel while in track-pan mode to zoom in and out of the schematic.

  • By moving the mouse over the Editing Window, holding down the SHIFT key, and 'bumping' the pointer against one of its edges. This pans the display in the appropriate direction. We refer to this feature as Shift-Pan.
  • By pointing in the Editing Window and pressing one of the Zoom keys (see below).This re-centres the display about the cursor position.
  • By using the Pan icon on the toolbar.

Zoom In / Zoom Out

You can magnify or reduce the display of the board using the Zoom In and Zoom Out commands that are also invoked by the F6 and F7 shortcut keys. Alternatively, you can roll the middle mouse wheel to zoom in or out of the area currently pointed to by the mouse. Pressing F8 will display a view of the entire board. You can also use the corresponding icons on the toolbar.

If the keyboard is used to invoke the command, then the Editing Window will be redrawn to display a region centred around where the mouse cursor was pointing before. This also provides a way to effect a pan by pressing the zoom key for the current level and simultaneously pointing with the mouse at where you want centre of the new display to be.

Variable Zoom

An arbitrary degree of magnification can be achieved using the Shift-Zoom feature. A given area of the board can be selected to fill the Editing Window by holding down the SHIFT key, pressing the left mouse button and dragging out a box around the desired area. The area can be marked on either the Editing Window or the Overview Window. You can also zoom to an area by clicking the Zoom Area icon on the toolbar.

The Overview Window

The Overview window in ISIS

This window normally shows a simplified representation of the whole drawing, and has a half-inch grid on it. The cyan box marks the outline of the sheet border, whilst the green box indicates the area of the design currently visible in the Editing Window.

Clicking left at a point on the grid re-centres the Editing Window around this point, and redraws the Editing Window.

You can also use the Shift-Zoom and Track-Pan features detailed above on the Overview Window.

At other times, Overview Window is used to display a preview of an object that is selected for placement. This Place Preview feature is activated in the following circumstances for any object which may be oriented:

  • When an object is selected from the object selector.
  • When the rotate or mirror icons are adjusted.
  • When an object type icon is selected for an object whose orientation can be set (e.g. the Component Icon, Device Pin icon, etc.).

The place preview display is cleared automatically as soon as you proceed the place the object, or when you perform any operation other than those listed above.

The Overview Window pane can be dynamically hidden by right clicking on it and selecting the ‘Auto-Hide’ command from the resulting context menu. This is particularly useful where the parts are on the schematic and you want to maximise the Editing Window space for schematic layout.

The Object Selector / Parts Bin

The Object Selector in ISIS

The Object Selector is used for picking components, terminals, generators, graph types and so on from those that are available. It always carries a label indicating what it is listing and this serves as a prompt additional to the state of the Icon Panel as to which mode is current.

The width and position of the Object Selector can be adjusted in conjunction with the width and height of the Overview Window, as described above. You can also hide this pane to maximise the Editing Window space by right clicking on the Object Selector and selecting the Auto-Hide command from the resulting context menu.

The Context Menu for the Object Selector provides a number of mode specific options, giving you quick and easy access to functionality during schematic design.

Co-ordinate Display

The current co-ordinates of the mouse pointer are displayed down at the bottom right of the screen by default. The read-out can be in imperial or metric units and a false origin may be set. Further details are given under co-ordinate system.

The X-Cursor command will display a small or large cross, in addition to the mouse arrow, at the exact location of the current co-ordinates. This is particularly helpful when used in conjunction with the Real Time Snap feature, since it gives you an immediate indication of what ISIS thinks you are pointing at.


CO-ORDINATE DISPLAY

Overview

All co-ordinates in ISIS are actually held in 10nm units, purely to be consistent with the ARES layout module. However, the coordinate read-out is restricted to 1 thou units. The origin is held to be in the centre of the work area and so both positive and negative values are used. The co-ordinates of the pointer are displayed at the bottom right of the screen.

We refer to a 1 thou increment as a unit.

False Origin

Although the Origin command appears on the View menu, it should only be used via its keyboard short cut (by default this is 'O'). Its function is to zero the co-ordinate display at the current mouse position, a feature that is most useful when laying out a complex pattern of pads given a set of dimensions on a drawing of the component.

When a false origin is set, the co-ordinate display changes colour from black to magenta as a reminder.

Cancelling a false origin is done by invoking the Origin command a second time.

The Grid

A line grid is displayed in the Editing Window - this can be switched between line grid, dot grid and no grid via the 'G' shortcut key or by invoking the Grid command on the View menu (three way toggle). When enabled, the spacing reflects the current snap setting, unless this would result in a ridiculous number of lines/dots, in which the spacing is increased.

Snapping to a Grid

You will notice that when the pointer is over the Editing Window, the increments of the co-ordinate display are in fixed steps - initially 100th. This is called snapping and enables you to position components and other objects on a neat grid. The degree of snap may be selected with the Snap commands on the View menu, or directly via keyboard shortcuts (default assignation F4, F3, F2 and CTRL+F1).

If you wish to see exactly where the snapped position is, you can use the X-Cursor command that will display either a small or large cross at this location

Real Time Snap

Furthermore, when the pointer is positioned near to pin ends or wires, the cursor location will also be snapped onto these objects. This function is called Real Time Snap and allows you to connect to or from pins and wires that are not on the currently selected snap grid.


FILING COMMANDS

Introduction

ISIS makes use of the following file types:

  • Project Files (.PDSPRJ)
  • Workspace Files (.WORKSPACE)
  • Project Clips (.PDSCLP)
  • Module Files (.MOD)
  • Library Files (.LIB)

All data from the schematic is collated and stored as part of the Proteus project file with extension 'PDSPRJ'. This is a compound file containing the schematic data, the layout data, the project database and potentially other simulation related files. Backup copies made when saving over an existing file are prefixed with 'Backup of...'.

Information about which modules are open in Proteus (e.g. Schematic, Bill of Materials and Layout) together with their positions on your monitor(s) and which frames they are in are stored in the project workspace file. This allows you to return to the same project state when you reload a project.

A section of a drawing can be exported to a section file and subsequently read into another drawing. Section files have the extension 'SEC'. and are read and written by the Import and Export commands on the File menu.

Module files have the extension 'MOD' and are used in conjunction with the other features for hierarchical design. See hierarchical designs for further information.

Symbol and device libraries have the extension 'LIB'.

The Proteus VSM simulation system uses other file types as well. See the VSM manual for further details.

Starting a New Project

To start a new design you need to create a new Proteus project. You do this by invoking the New Project Wizard either from the home page or from the file menu. This wizard guides you through the setup of your next Proteus project. There is a start page in which you specify the project name and destination directory and then potentially three main screens for schematic, PCB and firmware.

Schematic

When creating a schematic check the box at the top of the screen and then select the template on which you want to base the schematic. Those provided by Labcenter basically contain different sizes of work area, although you can customize and save your own templates from within the schematic capture module.

PCB Layout

If you are creating a PCB check the box at the top of the screen and select from the available templates. PCB templates contain pre-defined board edges, mounting holes and a full set of technology data (design rules, layers in use, default units, etc.) As with schematic, you can customize and save your own templates from within the PCB layout module.

This screen will only be presented to you if you have a license for one of the Proteus PCB design products.

Firmware

If you are creating an embedded design and want to simulate your firmware, check the create firmware box at the top of the screen and then select your controller and compiler using the combo boxes. If selected, the quick start files checkbox will generate a skeleton firmware project for you and configure project settings for compilation.

Creating a firmware project requires a schematic in order to simulate so you cannot proceed from this screen if you opted not to create a schematic earlier in the wizard.

The combo boxes on this screen are license aware so you cannot create a firmware project for a controller than you cannot simulate in Proteus.

There is also a summary page at the end allowing you to review your setup before the wizard exits and generates the project files.

See Also:

Creating a New Project (Tutorial)

Loading an Existing Project

Loading an existing project can be done in three ways:

  • From the command prompt as in: PDS.EXE <my_project>
  • By using the Open Design command once ISIS is running.
  • By double clicking the file in Windows Explorer.

Importing a Legacy Project

Older versions of Proteus typically contained several files such as a DSN file for schematic and a LYT file for layout. The Import Wizard on the home page and File Menu is used to bring these projects into Proteus 8.

To import a legacy project

Launch the import wizard.

Browse for the old schematic (.dsn file)

If a PCB file (.lyt file) is associated with the schematic it will automatically appear in the Layout field. If there is no layout file associated with the schematic then leave this field blank.

If an old VSMStudio file (.vsmp) with the same name as the schematic exists in the same directory it will automatically appear in the VSM Studio edit box. If the wrong VSMP file appears or there is no corresponding VSMP file then either browse for the file or leave blank.

The project name and path are taken from the filestem and location of the schematic being imported. You can change this if required from the fields at the bottom of the dialogue box.

If you change the path for a VSM project then you will need to manually change the PROGRAM property of the microcontroller, otherwise your simulation will fail.

When you are finished use the import button to create an import a Proteus 8 project.

Saving the Project

You can save your Project when quitting via the Exit command, or at any other time, using the Save Project command. In both cases it is saved to the same file from which it was loaded. The old version will be prefixed with the text ‘Backup of’.

The Save As command allows you to save the Project to a different file.

Import / Export Section

The Export command creates a section file out of all currently tagged objects. This file can then be read into another sheet using the Import command. After you have chosen the section file, operation is identical to the Block Copy function.

These commands have nothing to do with graphics export to DTP packages. The Export Graphics commands handle this functionality

Quitting Proteus

When you wish to end a Proteus session, you should use the Exit command, default key 'Q' or use the cross at the top right of the application. If you have modified the project, you will be prompted as to whether you wish to save it.


GENERAL EDITING FACILITIES

Object Placement

Proteus supports many types of object, and full details of the purpose and behaviour of each type is given in the chapter on Object Specifics. However, the basic steps for placing an object are the same for all types.

To place an object:

  1. Select the appropriate icon from the Mode Selector toolbar for the category of object that you want to place.
  2. If the object type is Component, Terminal, Pin, Graph, Symbol or Marker, select the name of the object that you want from the selector. For Components, Terminals, Pins and Symbols, this may first involve picking it from the libraries.
  3. If the object is orientable, it will have appeared in the Overview Window. You should now adjust its orientation to that which you require by clicking on the Rotation and Mirror icons.
  4. Finally, point on the Editing Window, click left to enter placement mode, move the mouse to the location on the schematic where you want to place the object and left click the mouse to deposit the object and exit placement mode.. The exact procedures vary for each object type but you will find it all fairly intuitive and similar to other graphics software.

See Also:

Selecting Parts from the Library (Tutorial)

Placing Objects on the Schematic (Tutorial)

Tagging an Object

Tagging or highlighting an object can be done in several ways as detailed below :

  • Entering selection mode and left clicking on the object.
  • Right clicking on the object (tags the object and presents you with that objects context menu.
  • Dragging a box around the object (or objects!) using the left mouse button.
  • Modeless selection by clicking the left mouse button on the object. This is extremely fast and works for all objects except for wires and 2D Graphic objects where one of the above methods must be used.

Normal use would be to use either modeless selection or simply to right click on the object, however it is very much an area for personal preference.

Objects may be de-selected either by right clicking in free space and selecting the Clear Selection option from the context menu or simply by left clicking in free space.

See Also:

Timesaving Techniques & Block Editing (Tutorial).

Deleting an Object

You can delete any object by pointing at it, clicking right and selecting Delete from the resulting context menu. All wires connected to the object will also be deleted, except in the case of a dot connected to exactly 2 wires, in which case the wires will be joined.

Note that for 2D Graphics objects you must right click on the border of the graphic to invoke the context menu - it is possible that 2D graphics may be placed around or behind another object and it is therefore necessary to ensure that the 2D graphic (as opposed to the other object) is the one you want to action on.

Dragging an Object

You can drag (i.e. re-position) any tagged object by pointing at it (the cursor will change to indicate that the object can be dragged)and then dragging with the left button depressed. This applies not only to whole objects, such a components, but also individually to their labels.

  • If the Wire Auto Router is enabled and there are wires connected to it, then these will be re-routed or 'fixed up'. This can take some time if the object has a lot of connected wires; the pointer becomes an hour glass while this is happening.
  • If you drag an object by mistake, and all the wiring goes horribly wrong, you can use the Undo command, key CTRL+Z to restore things to their original state.

See Also:

Basic Schematic Entry (Tutorial)

Block Editing (Tutorial)

Dragging an Object Label

Many object types have one or more labels attached to them. For example, each component has a reference label and a value label. It is very easy to move these labels in order to improve the appearance of your schematics.

To move a label:

  1. Tag the object by one of the methods outlined above.
  2. Point at the label and depress the left mouse button.
  3. Drag the label to the required position. If you need to position it very finely, you can change the snap resolution using the shortcut keys (by default these are mapped to F4, F3, F2, CTRL+F1) even whilst dragging.
  4. Release the mouse button to finish.

Resizing an Object

Sub-circuits, graphs, lines, boxes and circles may be resized. When you tag these objects, little white squares called handles will appear and the object can be re-sized by dragging the handles.

To resize an object:

  1. Tag the object by entering selection mode and left clicking on the object (remember to left click on the border if the object is a 2D Graphic).
  2. If the object can be resized, a set of little square handles will appear on it.
  3. Resize the object by pointing at a handle, pressing the left mouse button, and dragging it to a new position. The handles disappear whilst you are dragging so that they do not obscure your view of the object itself.

See the section on Resizing 2D Graphics for information about advanced use of handles when resizing 2D graphics path objects.

Reorienting an Object

Many of the object types may be oriented - that is rotated through 0°, 90°, 270° and 360° and reflected in x and/or y. If such an object is tagged, the Rotation and Mirror icons will change colour from blue to red, and will then affect the tagged object.

To reorient an object:

  1. Tag the object using one of the methods outlined here.
  2. Click left on the rotation icon to rotate it anti-clockwise, right to rotate it clockwise.
  3. Click left on the Mirror icon to toggle its reflection in x, and right to toggle its reflection in y.

It is worth noting that if the Rotation and Mirror icons are red, operating them will affect an object somewhere on the diagram, even if you cannot currently see it. This becomes important if, in fact, you wish to manipulate a new object which you are about to place. If the icons are red, first untag the existing object by pointing at an empty area of the design in the Editing Window and clicking left. The icons will then revert to blue, indicating that it is 'safe' to adjust them.

Rotation Icons

Editing an Object

Many of the objects have graphical and/or textual properties that may be edited through a dialogue form, and because this is a very common operation we have provided a variety of ways to achieve it.

To edit a single object using the mouse:

Either:

Right click on the object and select Edit Properties from the resulting context menu.

Or:

Double click the left mouse button on the object.

To edit a succession of objects using the mouse:

  1. Enter Selection Mode.
  2. Point at each object in succession and click left.

To edit an object and access special edit modes:

  1. Point at the object.
  2. Press the shortcut for ‘Edit Object Under Mouse‘ (default assignation is CTRL+'E').

For text scripts, this will invoke the external text editor. Also, if the mouse is not over any object, this command will edit the current graph, if any.

To edit a component by name:

  1. Key the shortcut for ‘Find and Edit Component’ (default assignation is ‘E’).
  2. Type in the reference name (part ID) of a component.

This will locate and bring up the dialogue form for any component in the design, not just those on the current sheet. After the edit, the screen is re-drawn with the component in the centre. You can thus use this command to locate a component, even if you do not actually want to edit it.

Details pertaining to the operation of the dialogue forms associated with each object type are given in the Object Specifics section of this documentation.

Editing An Object Label

Component, terminal, wire and bus labels can all be edited in much the same way as objects:

To edit a single object label using the mouse:

  1. Tag the object by pointing at it and clicking left.
  2. Click left on the label (not the object itself).

To edit a succession of object labels using the mouse:

  1. Enter Selection Mode.
  2. Point at each label in succession and click left.

Either way, a dialogue form with Label and Style tabs is displayed. The editing of local text styles is fully covered in the tutorial on graphics and text styles- see Editing Local Styles.

Copying all Tagged Objects

To copy a section of circuitry:

  1. Tag the required objects by dragging out a tag-box as described in Tagging an Object.
  2. Right click within the tagbox and select the Block Copy option from the resulting context menu.
  3. Move the mouse to lift the copy outline to the require position and click left to place a copy.
  4. Repeat step [3] as required to place multiple copies.
  5. Click right to finish.

When components are copied, their references are automatically reset to the un-annotated state so as to ready them for automatic annotation, and prevent the occurrence of multiple instances of the same part IDs.

Moving all Tagged Objects

To move a set of objects:

  1. Tag the required objects by dragging out a tag-box as described in Tagging an Object.
  2. Move the mouse inside the tagbox (the cursor will change to indicate that the block can be moved.
  3. Depress the left mouse button, drag the outline to the required position and click left to place it.

Moving a tagged object

The behaviour of wires during block move is somewhat subtle. Essentially, ISIS will move all wires or parts of wires enclosed in the tag-box without re-routing them, and then, where wires cross the boundaries of the tag-box, it will reroute from the last point inside the tag-box to the first point outside it. It follows that you can control whether a section of wiring is preserved or re-routed according to whether you include it in the tag-box or not.

Deleting all Tagged Objects

To delete a group of objects:

  1. Tag the required objects by dragging out a tag-box as described in Tagging an Object.
  2. Right click within the area encompassed by the tagbox and select the Block Delete option from the resulting context menu.

If you delete something by mistake, you can recover it using the Undo command.

Rotating all Tagged Objects

To rotate a group of objects:

  1. Tag the required objects by dragging out a tag-box as described in Tagging an Object.
  2. Right click within the area encompassed by the tagbox and select the Block Rotate option from the resulting context menu.

Note that you cannot Block Rotate a tagged section of circuitry if either a sub-circuit or a graph is highlighted (these objects have a fixed orientation). Also, depending on the complexity of the design and in particular whether tagged components are wired up, this operation may take a few seconds to complete. As always, you can undo the rotation via the Undo command.


WIRING UP

Wire Placement

You may have noticed that there is no Wire icon. This is because ISIS is intelligent enough to detect automatically when you want to place a wire. This avoids the tedium of having to select a wire-placement mode.

To connect a wire between two objects:

  1. Move the mouse over the first object - the mouse cursor will change to be a green pencil to indicate that you start wire placement at this point.

  2. Click left to start placement and then move the mouse towards the second connection point. The mouse cursor will change to an uncoloured pencil during placement.

  3. During more complex routes (which involve directional changes) left click the mouse to place an 'anchor'. This will commit the previously section of track and continue to follow the mouse movement from the anchor point. Successive anchor points can be undone by hitting the BACK button on the keyboard.

  4. When the mouse is over the termination point of the wire the cursor will again change to be green in colour. Left click to commit placement of the wire.

A connection point can connect to precisely one wire. For components and terminals there is a connection point at the end of each pin. A dot has four connection points at its centre so that four wires can be joined at a junction dot.

Since it is common to wish to connect to existing wires, ISIS also treats wires as continuous connection points. Furthermore, as such a junction invariably means that 3 wires are meeting at a point it also places a dot for you. This completely avoids ambiguities that could otherwise arise from missing dots.

See Also

Wiring Up (Tutorial)

Connectivity by Touch

It is often convenient to place a component against a wire or the pin of another component/terminal in order to make a connection. Proteus supports this method of connection as shown in the following examples.

Place component against wire

If you place a component pin end directly against a wire it will be considered connected to the wire and a junction dot will be created. The component can then be moved and a wire will automatically be placed

Place component against terminal or component pin

If you place a component such that a pin end on the component is directly against another component pin end or a terminal end on the schematic it will be connected to that component or terminal.

Place (2-pin passive) component in the middle of a wire

If you place a passive component (e.g. res, cap) in the middle of a wire it will insert into the wire connection and both pins of the component will be connected.

Place component and then drag onto wire

If you place a component on the schematic and then separately drag it onto a wire it will not connect. No junction dot is created. The part must be placed directly on to the wire in order to make a connection.

Dragging a component on to a Junction dot

You can connect a component to a junction dot by placing it or dragging the pin end on to a junction dot.

Place component and then drag onto component / terminal pin

If you place a component onto the schematic and then separately drag the component such that a pin touches the end of a component pin or a terminal pin it will form a connection.

Copy and Paste component pin end onto wire

If you copy and paste a component and position the paste onto a wire, it will not connect It has the same rule as dragging an already placed component on to a wire.

Copy and Paste component onto another component pin end or terminal end

If you paste a component or a terminal on to another pin end or terminal it will create a connection

The following basic rules of thumb may be helpful:

  • If you are placing the component you can attach to another component, wire or terminal directly.
  • If you are dragging the component you can attach to another component pin, junction dot or terminal.
  • If you are copy and pasting you can only attach it to a pin end, a bus pin, a junction dot or a terminal only.

The Wire Auto-Router

The wire autorouter in ISIS provides an intelligent aid to quickly placing wires on the schematic. After starting wire placement the wire router will follow the path of the mouse towards the terminal point, making orthogonal adjustments as required. For longer, more complex routes you should periodically click left to 'anchor' or commit the previously routed segment (this gives you far more control over the routing process by allowing you to interact with the auto-router and direct it as required).

The WAR can be completely disabled by holding down the CTRL key during route entry. This is useful if you want to route a diagonal wire directly between two connection points.

Wire Repeat

Suppose you have to connect the data bus of an 8 bit ROM to the main data bus on the circuit diagram and that you have placed the ROM, bus and bus entries as shown below.

Repeat wiring

You would first click left at A, then B to place a horizontal wire between them. By clicking twice at C, you will invoke the Wire Repeat function which will then place a wire between C and D. Clicking left twice on E will join E and F and so forth.

Wire Repeat copies exactly the way the previous wire was routed. If the previous wire was automatically routed then the repeated wire will also be automatically routed. On the other hand, if the previous wire was manually routed then its exact route will be offset and used for the new wire.

Dragging Wires

Although wires follow the general scheme of tag then drag, there are various special techniques that you can apply to them. In particular:

  • If you point at a corner and drag then the corner simply follows the pointer.
  • If you point in the middle of a horizontal or vertical wire segment, the segment will be dragged vertically or horizontally respectively and the adjacent segments will be stretched to maintain connectivity.
  • If you point in the middle of a diagonal segment, or at either end of the wire, then a corner will be created and then dragged. Note that in order for the latter to work, the object to which the wire connects must not be tagged, as otherwise, ISIS will think you are trying to drag the object.

It is also possible to move a wire segment, or a group of wire segments using block move techniques.

To move a wire segment or group of segments:

  1. Drag out a tag-box around the wire segment(s) you wish to move. It is quite acceptable for this 'box' to be a line, lying along a single segment, if this is convenient.
  2. Move the mouse inside the tagbox (the cursor will change to indicate that objects can be moved).
  3. Depress the mouse and move in the direction orthogonal to the wire segments, as shown below.
  4. Release the mouse to finish

Moving a group of wires

A further technique provides a quick way of altering wiring topology, perhaps eliminating unwanted kinks in wires where they have been routed around an object which has since been moved.

To edit a wires topology after routing :

  1. Tag the wire you wish to manipulate.
  2. Move the mouse over the segment that you want to adjust.
  3. Depress the left mouse button and move the mouse orthogonally as indicated by the mouse cursor.
  4. Release the left mouse button when complete.

Removing kinks in a wire


MISCELLANEOUS

The Sheet Border

When a new sheet is created either as the first sheet of a new design, or by using the New Sheet command, it starts off at the size currently specified via the Set Sheet Sizes command. The extent of the sheet is shown by a dark blue sheet outline but this in itself will not actually appear on hard copy.

If a sheet border is required on the final output, you must place a graphics box (or whatever) over the sheet outline or use one of the pre-supplied templates.

The Set Sheet Sizes command is worthy of further discussion since it serves two distinct purposes:

  • To change the paper size for the current sheet, you simply invoke the command and click on the button for the required sheet size.
  • To re-define the dimensions of a paper size, highlight the appropriate data entry field(s) and key in the new dimension(s). If you change the dimensions of the current sheet size, this will affect the current sheet immediately but not any other sheets in the design. To affect these, you must invoke Set Sheet Sizes and click OK for each sheet in turn.

The Set Sheet Sizes dialogue form allows you to define the sizes of five standard sheet sizes (A4 through to A0) as well as a non-standard size and to select which one is the size if the current sheet.

The Set Sheets Sizes dialogue form

For each sheet size (A4-A0 and user) there are two edit fields. The left field defines the width (x-dimension) and the right side defines the height (y-dimension). Whenever the schematic loads a sheet that does not match any of the standard (A4-A0) sheet sizes it places the dimensions of the sheet into the User field and sets that to be the default sheet size for the loaded sheet.

The default values for the standard sheet sizes should work for most printers but please note that all printers have ‘margins’ in which they cannot print - if you attempt to print something that impinges on the margins it will most likely not be drawn. The size of the margin where a printer cannot print varies between printers and the best way to determine it is to draw a sample design with a box that surrounds your chosen sheet size and then printing it. If one or more edges of the box do not appear on the printed output then your sheet size extends into the printers margins and you should reduce it.

There is one more point to note about sheet sizes: Every sheet in a design carries its actual dimensions with it in the design file. If a design is loaded into a the schematic editor with a different sheet size configuration, this will not have any effect unless and until the Set Sheet Sizes command is used.

It is recommended that you either use an existing template or customise the size of a blank schematic and save it as a template. This is then re-usable for all future designs.

In order to use the component placement report you should either use one of our pre-defined templates or set the smart grid markers on a sheet border of your own making. More information here.

The Header Block

It is common practice to have on each sheet of a drawing a header block which shows details such as the design and sheet titles, the document, revision and page numbers, and the design's author.

In order that you have full control over how this information is presented, the header block is defined as a symbol library entry called HEADER. This was made in the usual way by placing graphics objects, tagging them and invoking the Make Symbol command. The significant thing is where, for example, the current design title is required, a text object with the string @DTITLE was placed and this is automatically replaced with the actual design title at display/print time.

The complete list of such keywords is shown below :

Keyword | Description | SCHEMATIC | PCB
@DTITLE | The design title taken from the Edit Design Properties command on the Design Menu. |  |
@BOARD | The current board name, taken from the name supplied. Relevant only for multi-board projects. |  |
@STITLE | The sheet title taken from the Edit Sheet Properties command on the Design Menu. |  |
@DOCNO | The design document number taken from the Edit Design Properties command on the Design Menu. |  |
@REV | The design revision number taken from the Edit Design Properties command on the Design Menu. |  |
@AUTHOR | The design author taken from the Edit Design Properties command on the Design Menu. |  |
@CDATE | The design creation date - generated automatically in a fixed format. |  |
@MDATE | The design modification date - generated automatically in a fixed format. |  |
@WS_CDATE | The design creation date - generated automatically and formatted according to the Windows short format. |  |
@WL_CDATE | The design creation date - generation automatically and formatted according to the Windows long format. |  |
@WS_MDATE | The design modification date - generated automatically and formatted according to the Windows short format. |  |
@WL_MDATE | The design modification date - generated automatically and formatted according to the Windows long format. |  |
@CTIME | The design creation time - generated automatically and formatted according to the Windows time format. |  |
@MTIME | The design modification time - generated automatically and formatted according to the windows time format. |  |
@PAGENUM | The current sheet page number within the design. |  |
@PAGECOUNT | The total number of sheets in the design. |  |
@PAGE | The sheet number within the design expressed as X/Y where X is the sheet page number and Y is the total number of sheets in the design. |  |
@FILENAME | The current designs filename. |  |
@PATHNAME | The full path and filename of the current design file. |  |
@PAGESIZE | The page / sheet size as set in the System Menu > Set Sheet Size. |  |
@VARIANT | The name of the currently active assembly variant. Can be used both on schematic (e.g. Header block) and on layout (e.g. Silkscreen text). |  |
@Board | The name of the Board that you are currently working on |  |

The Windows long and short date formats and Windows time formats are set using the Regional Settings or International applets in Windows Control Panel.

Note that the above keywords must appear at the start of a 2D text string and that the string should not contain additional text. For example, do not place strings of the form:

AUTHORED BY @AUTHOR ON @WS_MDATE

as these will not work! To achieve the above you need to place four strings along side each other (AUTHORED BY, @AUTHOR, ON and @WS_MDATE).

By use of the import bitmap facility, 2D graphics objects and such special text objects it is possible to define any kind of header block you want. In particular, you can incorporate your company logo into the header. Once defined, the header can be placed onto each sheet of the drawing like any other graphics symbol.

We strongly advise you, having created your header block, to place one on the Master Sheet and save as a design template. Please see the help documentation on templates for more information or run through the Tutorial.

Send to Back/Bring to Front

Sometimes several objects (especially Graphics) overlap and it becomes difficult to point at the one you want. By default, ISIS takes the most recently placed object, but you can re-arrange the order using the Send to Back and Bring to Front commands. Each command operates on the currently tagged objects.

You can also use these commands to order the draw order when creating new devices. For example, if you are creating a new op-amp symbol, you may need to send the op-amp body (the triangle graphic) ‘to the back’ in order to ensure it’s fill pattern doesn’t obscure the ‘+’ and ‘-’ input symbols, which of course, need to be ‘in front’.

Global Annotation

ISIS can automatically chose component references for all or some of the components in a design - this process is called Auto-Annotation.

The process is initiated using the Global Annotator command on the Tools Menu.

The Global Annotator dialogue form

The scope options allow you to annotate either the whole design, the current branch of the design (from the sheet you are on downwards in the hierarchy) or on the current sheet only.

The initial annotation option will define the base annotation for the current sheet and will set this property for the current sheet. If you are operating in branch or design mode then any specified sheet offsets on other sheets will be honoured.

The mode options specify whether all parts should be re-annotated (total mode) or only un-annotated parts (incremental mode).

As with all dialogues in Proteus, comprehensive context sensitive help is provided for all the fields on the form. Use the question mark at the top right of the dialogue form to 'point and shoot' at a field for more information.

Keyboard Configuration

Proteus provides an interface for you to map the keyboard to a command set. This allows you to ‘bring out’ the functionality you commonly use according to personal preference. The configuration dialogue, accessible via the Set Keyboard Mapping command is shown below (context sensitive help is available for all fields within the dialogue itself):

The Keyboard Configuration dialogue form

Notes :

  • Accelerators can use any combination of CTRL, SHIFT and ALT keys. For example, CTRL+X, CTRL+ALT+T, SHIFT+CTRL+1, etc.
  • A Reset option is provided to reload all Proteus standard shortcuts. This will clear any customs configurations.
  • Some European keyboards have an ALT GR key (normally found directly to the right of the space bar). Where present this translates to be CTRL+SHIFT for the purposes of assigning keyboard shortcuts.
  • If you assign an ALT accelerator that is used as a menu accelerator then you will no longer be able to accelerate the menu from the shortcut. For example, ALT+T by default expands the Tools Menu within ISIS. If you assign ALT+T to the Tidy command then you would have to have to access the Tools Menu using the mouse.
  • Some commands have keyboard assignments that cannot be changed (this is particularly true of those on Maximised Graphs). Note that an assignment for these commands cannot be re-assigned to another command.
  • If you assign a keyboard shortcut (e.g.CTRL+K) in the Application and then assign the same shortcut in a simulation popup window then the functionality executed by the shortcut is dependant on the focus at the time you use the accelerator. To avoid confusion we recommend you avoid multiple assignations of the same accelerator combination.
  • When the NUM LOCK is on the keys 0-9 on the numeric keypad are distinct from the 0-9 keys on the main keyboard. For example, you could assign CTRL+0 up to CTRL+9 on the main keyboard as shortcuts to the Most Recently Used file list (MRU list) and on the numeric keypad you can assign CTRL+NUM-0 up to CTRL+NUM-9 to Goto Sheet 0-9.
  • When the NUM LOCK is off keys 0-9 on the numeric keypad action their secondary functions and these functions are considered identical to those on the main keypad. The key for the number 5 on the numeric keypad has no secondary function when NUM LOCK is off.
  • You can save your custom keyboard configuration via the ‘Export Keyboard Map’ command on the Options tab. This allows you, for example, to port your keyboard configuration to another computer. Similarly, the ‘Import Keyboard Map’ command allows you to reload a custom keyboard configuration that has previously been saved.


OVERVIEW

ISIS provides a complete and flexible scheme for customizing the appearance of your schematics. Everything from graphics styles, text styles, design colours, wire junction dot size and shape, etc. to a pre-configured sheet size, sheet border graphics, company logo and header block can be set up in a design template file.

Every design template file has an built in repository of graphics and text styles and also has a master sheet. When you initialize a schematic from a design template the graphics and text styles from the template will be applied in the schematic and the contents of the master sheet in the design template will be visible in every sheet in the schematic.

It follows that there are essentially two steps to creating or modifying a design template file: customizing the graphics and text appearance and customizing the master sheet with an appropriate sheet size, border, header, etc. These are discussed in detail in the topics on Master Sheet and Graphics and Text Styles.


THE MASTER SHEET

Each design in ISIS has a Master Sheet (accessible from the Template Menu). The contents of this sheet are drawn on all sheets on the design thus providing a method for displaying a single sheet style throughout a design.

The following points relating to the master sheet are worthy of note :

  • While objects on the master sheet are visible on every sheet on the design they can only be edited or deleted by returning to the Master sheet.
  • As a result of the above and to avoid confusion only 2D Graphics and scripts can be placed on the master sheet – you cannot place components or other objects, nor can you import or paste other objects onto the master sheet.
  • If you change the sheet size on a given sheet such that it is no longer the same as the sheet size of the master sheet then the master sheet is suppressed across all sheets (it would be pointless at best to have a master sheet of A4 size showing on an A3 sheet for example).
  • If you change the size of the master sheet such that it different from the size of an existing sheet then you will be prompted to change the size of all existing sheets to match that of the master sheet. Note that this may have consequences if, for example, your existing sheet is A3 and you change the master sheet size to be A4.

Note that if you don't see your graphics on the root sheets, but they are on the Master Sheet you will need to go to the Template Menu > Set Design Colours and check the box Render Master Sheet:

The Templates Tutorial provides a walkthrough of creating and modifying design templates including editing the master sheet.


Tutorial

TEMPLATES TUTORIAL

Overview

As a starting point for the Templates tutorial, we'll use a pre-supplied sample project. From the Proteus home page click on the Open Sample button, navigate to the Tutorials category and select Styletut.pdsprj.

When this loads, you will see that the basic colour scheme in this design is blue outlines with yellow fills for components and red for terminals, etc. and if you zoom in (roll the middle mouse button or use the zoom keys) about some text, you will see that it is all in the Labcenter Electronics ‘vector’ font

The Tutorial Circuit

Editing Global Styles

We will begin by looking at how to edit the global graphics styles. These styles are, as their name implies, global to the design and editing these styles allows you to make global changes to the appearance of a schematic. Further, when we then save the schematic as a design template these styles will then propagate to all designs initialized from the template.

Let us start by changing the component colour scheme a little. All the components in the design were picked from the standard libraries and as such, the component graphics are all drawn in the COMPONENT style. We can change this style using the Set Graphics Style command on the Template menu. Select this command and you will see the Edit Global Graphics Styles dialogue form displayed as shown below.

Setting the Component Styles

This form gives access to all the graphics styles defined for the current design - drop the Style selector down to see the full list. As the buttons below the Style list indicate, it is possible to create, edit and delete new styles in addition to the editing the ‘predefined’ styles.

Make sure the COMPONENT style is selected in the Styles list. You will see in the Line Attributes and Fill Attributes sections the attributes for the style. Under Line Attributes select a red colour and then under Fill Attributes select a Fill Style of ‘none’. After both changes you will see that the sample at the right of the dialogue form updates to show a new preview of the style as shown below

Shows the Component Graphic style edited by the user

Now select the TERMINAL style in the Styles list. The changes you made to the COMPONENT style are automatically saved and the dialogue changes to display the settings of the TERMINAL style. This time, under Line Attributes select a blue colour for lines and then under Fill Attributes select a Fill Style of ‘solid’ which enables the Fg. Colour control where you can select a yellow fill colour.

Shows the Terminal Graphic style with user defined coloursj

Close the form using the Close button and the schematic is redrawn to show the changes. The new colour scheme would probably work better on a white background and as you will probably print your designs on white paper, let’s now select white as our ‘paper’ colour. From the Template menu select the Set Design Defaults command. The Edit Design Defaults dialogue form allows you to edit most of the standard colours used by ISIS including the background or ‘paper’ colour. Change this to a light grey or white as shown below and close the form.

Editing Design defaults

So we’ve seen how to change graphics styles. How about text styles? Changing these is pretty much the same as changing text styles except that style attributes you get to change are different.

However, before we start changing the text styles of individual elements, lets change the text font used in the drawing ‘en mass’. As you’ve already noted, the drawing is currently displaying all its text in the Labcenter Electronics ‘vector’ font. To change the default design font, again select the Set Design Defaults command from the Template menu to display the Edit Design Defaults dialogue form. Under Font Face For ‘Default’

Font you will see Vector Font selected - change this to the standard Windows Times New Roman font face and close the form. The design is redrawn and all text can now be seen to be in Times New Roman.

Shows the Edit Design Defaults form with the font changed

Wherever ISIS offers a list of TrueType™ fonts (e.g. as part of editing a text style) there are always two additional font faces listed at the top of the list. These are Default Font and Vector Font. The Default Font option is a place holder for whatever font is selected on the Edit Design Defaults dialogue form whilst the Vector Font option selects the internal Labcenter Electronics Vector Font. In the case of STYLETUT all the text and labels in the design has been placed and/or edited to use the Default Font face which means that it all displays in the font set on the Edit Design Defaults form - select a new font face there and all the text in the design is changed immediately!

The main use of the Vector Font is where you need to both produce hard copy output on a pen plotter. Windows does not properly support the use of TrueType fonts on plotters, and the Labcenter Plotter Driver will output all text in the Vector Font whatever it is defined as on the drawing. The Vector Font has the additional advantage that it is guaranteed to come out exactly the same size on all hard copy devices as it does on the screen. This is not always the case with TrueType fonts.

On the other hand, if you only need to use bitmap devices (i.e. printers) these issues do not arise and you can use all your TrueType™ fonts as you see fit. It has to be said that schematics which use more than two font faces are likely to look very odd!

Having changed our designs ‘default font’ to be Times New Roman lets make some object specific text style changes. From the Template menu, select the Set Text Styles command to display the Edit Global Text Styles dialogue form. Notice how similar this dialogue form is to the Edit Global Graphics Styles dialogue form you saw earlier - as we said, editing text styles is very similar to editing graphics styles.

By default, COMPONENT ID should be the Style selected for editing and you will see that the Font Face is set to Default Font which is, as we explained, the placeholder for the font selected on the Edit Design Defaults dialogue form, currently Times New Roman. Because of this, some fields on the dialogue form that aren’t appropriate to a TrueType™ font, such as character width, are greyed out. Change the Font Face to be Courier New and select Bold? under the Effects options.

Editing the Component ID Global Text styles to the users choice

Now select the PIN NUMBER style in the Style list (the changes to the COMPONENT style are automatically saved) and then uncheck the Visible? checkbox under the Effects options. Use the Close button to close the dialogue form.

Shows the option to hide the text

Editing Local Styles

So far we have only changed ‘global’ styles. Changing these has had an effect right across the schematic. We will now look at making changes to ‘local’ styles by editing the op-amp’s U1 component reference label.

Note that changes to the local style are not propogated into the design template. They are intended for customizing individual schematics only. If you want to a style change to be permanent you should apply it as a global style change as detailed above.

Lets start by taking a look at a local style: click left on the U1 label to tag it (and the op-amp) and then click right and choose the Edit Label from the menu. The Edit Component ID dialogue form to be displayed.

Edit Component Value dialogue

Finally, select the Style tab to see the ‘local’ style settings. You will see the following: a Global Style selector at the top, a set of style attributes (Font face, Width, etc.) to the left and for each attribute a Follow Global? check box to the right. Both text and graphics local styles have this format. Wherever a Follow Global? checkbox is checked, the associated style attribute is initialized from the global style indicated in the Global Style selector. Unchecking the Follow Global? checkbox enables the dialogue control for the associated style attribute allowing you to specify a local (object-specific) value for that attribute. Not all the Follow Global? checkboxes are enabled as, in this case, the Width attribute is meaningless for a TrueType™ font face.

The change we are going to make is to make the U1 label a different colour. Start by unchecking the Follow Global? checkbox to the right of the Colour control and you will see the Colour control is enabled and displaying the current colour set in the whatever global style this local style is following (in this case, the COMPONENT ID style). Change the colour to be dark blue, then close the form and untag the op-amp so that it is redrawn in its normal colours. The U1 label is now dark blue.

Setting Component Value style

To verify that the label’s colour is indeed now independent of the global style but that the remainder of the attributes are still following its global style, select the Set Text Styles command on the Template menu again, change the colour of the COMPONENT ID style (selected by default) to magenta, check (enable) the Italic option and then close the form. The op-amp’s component label remains dark blue as its colour is not longer following the global COMPONENT ID style however its Italic attribute is still following the global style, so it is now italicised. All the other components’ IDs, which have remained following the global COMPONENT ID style, have both changed colour and become italicised.

For completeness, we will now show you how to edit a local graphics style. Select the Box icon. Now make sure the COMPONENT style is selected and then, placing the mouse at the top left of the circuit, click left and drag out a box that surrounds (and covers!) the circuit diagram. We now need to change the local style of the box to be transparent. Choose the Selection Icon and click left on the outline of the box to highlight the box then right click on the outline and select the Edit Properties from the menu - the Edit Box’s Graphic Style dialogue form is displayed. Apart from the different style attributes, notice how this form is similar to that of the Edit Terminal Label dialogue form’s Style tab. The operation of this form is the same as the operation of that form. Uncheck the Follow Global? checkbox for the Fill Style control and then, it now being enabled, change the fill style to ‘none’. Under Line Attributes, uncheck the colour checkbox and choose a colour of your choice (we have chosen blue). Close the form with the This Graphic Only button and untag the box.

Shows the Edit Box Graphic Styles dialogue

This is a simple example of the power of local and global styles though in general use of ISIS you will never need to modify a local style. The main use of local styles is with 2D graphics objects (lines, boxes, etc.) when creating a new library part and even then it is recommended that you avoid setting up local styles unless absolutely necessary. As you have seen, once an object has a local setting its appearance is fixed unless it is re-edited and, when applied to new library parts, this means that some or all of a library part will not blend in to the drawing in which it is used. In proper use, this is usually the intention - for example, that the base of a transistor always have a solid fill regardless of the fill selected in the global COMPONENT graphics style. However, when misused, it can lead to library parts that simply don’t port between different colour schemes or users.

Editing the Master Sheet

Having now covered configuration of graphics styles we need to look at design configuration. The first thing we need to do is navigate to the master sheet from the Template menu as shown below

Template Menu - Goto Master Sheet Command

Think of the master sheet as a way to initialise the contents of all sheets with specific graphics. The contents of the master sheet are drawn on every sheet on the design, but are only editable when the master sheet is selected. Further, only graphics and scripts can be placed on the master sheet. This concept allows us, for example, to set up a header block and configure the sheet outline and size for all the sheets on the design in a single place.

More information on the Master Sheet can be found here.

You should see all the graphical objects on the design without any of the components, wiring etc. as shown below.

View of the Master sheet.

Any changes you make to the graphics on this sheet will appear in all the sheets of the schematic. Further, they will be saved into the design template and will therefore appear in all designs initialized from the template. This means that you can set up your sheet size, header information, company logo etc. on a master sheet, save the schematic as a design template, and then reuse the template in all your future designs.

We will now use the master sheet to change the appearance of the design. Start by selecting the Set Sheet Size command from the System Menu and changing the sheet size to be A3.

Set Sheet Sizes dialogue with A3 selected

You will be prompted at this point to make all of the sheets on the design the same size as the master sheet. Since we are enlarging the sheet size select the OK button to close the dialogue resize the sheet.

If you make the sheet size smaller and you are working on a schematic you could end up with parts on an existing sheet outside of the work area. Caution is therefore required when adjusting the sheet size on the master sheet during design development.

One consequence of enlarging the sheet size is of course that the sheet border is now the wrong size. To enlarge this simply right click on the box graphic and drag the handles until the box is aligned with the edges of the world area.

Now drag a box around the header block and move the block back into position at the bottom of the sheet as shown below.

Moving the tagged header block into position

More information on customising the header block can be found here.

Finally, do the same with the script block moving the text and graphics to an appropriate place on the sheet. You can of course change the text, font and colour of the script as detailed in the styles section above.

A common enhancement to the Master sheet is the inclusion of a company logo. You can import a logo in PNG, GIF, JPG, BMP formats from the Import Image command on the File Menu.

As with the other elements of the Master Sheet you will want to position carefully to avoid clashing with the actual electronic design on normal schematic sheets.

We will now go back to the root sheet of the design proper. To do this, navigate back to the root sheet from the design menu as shown below.

Selecting the Root sheet to return to the main design

Detailed information on using the Design Explorer can be found here.

You can provide names for sheets in ISIS via the Edit Sheet Properties command on the Design menu. Naming a sheet makes it recognizable and easy to navigate to from the Goto sheet command, particularly for hierarchical schematics.

You should now see that all the changes made in the master sheet are visible on the root sheet of the schematic and that the components and wiring form but a small area of the sheet. Obviously this is a little contrived and for a real design of this size you would almost certainly stay with an A4 template but it should give you some appreciation of the customization options available to you.

Saving the Design Template

Having now covered both graphical and design customization all that remains is to make our schematic into a design template. To do this go-to the Save as Design Template on the Template Menu, naming the template file appropriately (for example as tutorial) and make sure you check the box to save only the master sheet.

The Save Design as Template dialogue

Clearly in this case we do not want the components, wiring etc. to be saved in the template. You can save components and circuitry as a template but we do not recommend this because if any of the components change in the libraries they will not be updated when you initialize a schematic from the template.

Design Templates must be saved in your Templates directory as specified by the Set Paths command on the System menu. If you need to have more than one templates path (for example, for user templates and company templates) then you can simply add another path via the same command.

When you start up Proteus or start projects directly via the ISIS icon the default template is loaded. At the time of shipping this is our own ‘house style’ but you can make this own template by saving your template with the name ‘default’.

Using a Design Template in a Project

The final thing we want to do is start a new project based on our template to ensure that all our changes have taken effect.

To use a design template in a project

  1. Select the New Project Wizard from the File Menu or Proteus homepage.

  2. On the schematic tab you will see a list of available templates will be displayed and become enabled when you specify that your project contains a schematic. This list corresponds to all the template files located in the Templates directory as specified from the Set Paths command on the System Menu. Select the template you wish to use for the project; when the project opens you should find that all of your styles are in use in ISIS and that Master Sheet config is as specified in this tutorial.

The New Design dialogue


OBJECT PROPERTIES

Introduction

There are two distinct types of object property - system properties and user properties. The former comprise a set of reserved keywords which have special functions within Proteus itself, whereas the latter relate either to external programs, or may relate to your own particular use of the software (for example, the Bill of Materials report).

System Properties

System properties are properties whose keywords have special meaning within ISIS. For example, the DEVICE property of a component object directly determines the library part assigned to it. Some of these properties are textual - e.g. component REF and VALUE labels are directly accessible from the Edit Component dialogue form, but others such as the aforementioned DEVICE property are manipulated as a result of graphical operations.

In general, you need only concern yourself with system properties if you wish to read their values with the Search and Tag command, or modify them with the Property Assignment Tool. For example, you might wish to tag all the 7400 components in your design. This requires you to know that the system property that will hold the library part name is called DEVICE.

Details of the system properties used by each type of object are given in the Object Specifics section of this documentation.

User Properties

Components, sub-circuits and VSM gadgets can carry an unlimited number of extra properties, in addition to their standard system properties. These user properties are held in a block of text known as a property block and consisting of lines such as:

SUPPLIER=XYZ Electronics

The most convenient and common method for editing user property blocks is via the spreadsheet interface in design explorer although you can also do so directly on the dialogue forms of the various objects themselves. In either case it's important to realise that you are making local changes to the design and not persistent changes to the library parts. A more stringent approach would be to correct/update the library parts via Library Manager so that the master devices were correct and then pick the updated parts back into the current schematic. Either method is fine and the decision may largely be one of company policy with respect local property changes.

One advantage of updating the library parts versus making local changes is that the Manage Changes command on the library menu will do a better job of handling design revisions.

See Also:

Design Explorer

To edit user properties via Design Explorer

1) Add the properties to the component grid

2) Change the values

If you want to operate on only a subset of parts (for example change the package of all 10k resistors) then first use the search tab to filter the list of parts and then follow the procedure above.

See Also:

Design Explorer

To edit an objects user properties individually:

  1. Bring up the object's dialogue form by tagging it and selecting Edit Properties from the resulting context menu.

  2. If the object can hold user properties, the dialogue form will have a text editor box labelled Properties. Point below any existing text in this box and click left.

  3. Edit the text as required. Each property should consists of a single line comprising a keyword and value separated by an equals sign (=).

User property keywords should, as a rule, consist of letters, numbers and underscores only. Under no circumstances should they contain spaces, commas, double quotes or equals signs (,"=).

In accordance with the general behaviour of ISIS text, if a property assignment is enclosed in curly brackets ('{' and '}') then it will not be displayed on the screen. For example, entering:

{PRIMITIVE=DIGITAL}

will define an object as requiring digital simulation, but this text will not actually appear.

Occasionally, one may want just the value to appear, in which case you can do:

{MODFILE=}OPAMP

In theory you can put curly brackets in other places. However, when the Property Assignment Tool modifies property blocks, it works on the assumption that if used at all, curly brackets have been placed as shown in the above examples. If they have been placed elsewhere, then you may get unexpected results.

Property Definitions (PROPDEFS)

It is possible to provide extra details for specific user properties of a device. For example, common user component properties are PACKAGE and MODFILE. Given that appropriate Property Definitions have been created for the component libraries, these properties are displayed in their own fields on the Edit Component dialogue form. The property definitions include a description of the property, a data type (such as integer, floating point or string) and for numeric data types a valid input range. A default value may also be (and often is) specified.

This scheme makes it much easier to see what properties are valid for a particular model, and what those properties mean. It is also then possible to supply alternate package types and simulator models in a way that is obvious to the end user of a particular library part.

Properties which are not known for a particular device (or all properties for a device which does not have property definitions) still appear in the textual properties block as described above, and the scheme is thus backward compatible with old designs and/or library parts which do not have property definitions.

When adding and configuring properties via the Bill of Materials property editor rather than manually, the PROPDEFS are created and written for you at the point you create the BOM field.

You can view, edit and delete the current set of propdefs via the Set Property Definitions dialogue on the System Menu in ISIS.

Local Changes vs Device Changes

When you make a change to a component on the schematic it is a local change. This means that you can have several instances of the part across the schematic and only one or two have this change applied. It doesn't matter if you make the change via design explorer , Bill of Materials or the Property Assignment Tool - you are applying the change to the schematic parts, not to the device.

By contrast, if you make the change in Library Manager then you will apply the changes directly to the library parts themselves. If you then pick the part into a future project these changes will be present.

Updating All Instances after Local Changes

Local changes can be very useful but you need to be aware that instances of a device with different properties presents an unsolvable problem to the software if you then choose to later update the device. For example, let's assume you have changed the package on some, but not all, passives with the same name via design explorer. If you then attempt to remake the part or update it from the library you will see a prompt to 'Update All Devices' with the changes.

Example prompt for updating all instances of a device.

Proteus cannot safely update all of the devices because there is no way to tell if the property changes are intended to be kept or not. If there are local changes to existing properties then the update will not affect those properties and you will be warned that local property changes exist. Added properties to some instances but not the one being updated will not be affected by the replace and will not count as local changes since they are additive.

Manual oversight is then required. You can either

1) Browse the schematic and open and correct the tagged components.

2) Open Design Explorer, go to View Menu -> Property Columns and select the checkbox for adding columns for properties with local changes. This will leave you with a grid of parts and properties that you can change as needed.

Note that you can right click on a part in the parts bin and select 'Tag Local Changes' from the context menu to re-tag all instances that have local changes.

The summary of this is that if you make global changes (library manager) and then filter them downwards (update part or pick into project) all properties will come from the master. However, if you make local changes (Design Explorer, BOM, Edit Component, etc.) and then try to apply a global change you will need to review and sort it out manually afterwards as discussed above.


SHEET PROPERTIES

Introduction

Each sheet of a schematic can hold a set of property assignments. These may be considered as defining constants (either numeric or textual) which may be used within object property assignments on the particular sheet. In themselves they are not terribly useful, but their real power comes to light when they are used in the context of object property expressions.

For example, if a sheet property is defined in a block such as:

*DEFINE PI=3.142

you could then define a resistor as having the value:

VAL=EVAL(500/PI)

At netlist time, this syntax causes the netlist compiler to evaluate the property, and the resistor's value will appear in the netlist or bill of materials appear as 159.134.

For further information about property expressions see Property Expression Evaluation

Defining Sheet Properties

Sheet properties can be defined in the following ways:

  • Directly, using a DEFINE script block. You can use this to define constants for use in expressions, as in the above example.
  • As a result of parameter mapping using a MAP ON script block. In this case, the value of the parent property specified by the MAP ON statement is used to select a set of sheet property definitions from a table. This is most commonly used for creating universal simulation models, in which several similar devices are modelling using the same circuit but with different sets of sheet properties for each device type. Further discussion of this is given in the Proteus VSM manual.
  • By inheriting the properties of a parent object. In other words, if the parent object has the object property assignment:
    R3=10k
    then the child sheet will automatically acquire this as a sheet property. This provides the basis for parameterized circuits in which several instances of a given hierarchy module can be assigned different component values.

If the same property is defined both on a child sheet in a DEFINE or MAP ON block and in the parent object property block, the value from the parent will be used. This provides the means to provide default values for sheet properties which can be overridden as required.

Scope Rules for Sheet Properties

It is important to realise that sheet properties may only be referenced on the sheet for which they are defined. In particular, the sheet properties on a parent sheet are not accessible by any of its children unless they are passed though the parent object property block. If you do need to access a property in this manner, you can add a line such as:

TDHL=<TDHL>

to the appropriate parent object(s). If TDHL is defined as a sheet property on the parent sheet, it will then become an object property of the parent object, and thus be defined as a sheet property for the child sheet, where it can in turn appear in further object property expressions.

This arrangement is analogous to passing parameters in a C computer program.

The parent sheet and child sheet with parameter passing

Design Properties

The design properties for a given schematic are determined by accumulating all the sheet properties that are declared on the root sheets of the design. Since root sheets cannot have parents, it follows that design properties can only be declared using DEFINE script blocks on the root sheets.

For SDF netlist output, the design properties appear in the PROPERTIES block of the netlist, and may be interpreted by whatever application is reading the netlist. In the case of Proteus VSM, design properties are used to define simulator options such as the number of steps, the operating temperature and so forth. The specifics of this are given in the Proteus VSM manual.

To create a list of design properties:

  1. Go to the root sheet of your design by selecting the root sheet from the Design menu.
  2. Selecting the root sheet via the Design Menu.

  3. Select the Script icon from the Mode Selector toolbar.
  4. Point where you want the property definition block to appear and click left.
  5. Type in the first line of the script as *DEFINE and then type in the property assignments as required.


PARAMETERIZED CIRCUITS

Introduction

ISIS has a unique and tremendously powerful feature which combines sheet properties, object properties and hierarchical design to facilitate parameterized circuits. A parameterized circuit is one in which some of the component values (or other properties) are given as formulae rather than as constant values. Naturally, the formulae contain variables or parameters and the values for these are taken from the sheet properties defined for that particular instance of the circuit. It then follows that, in the context of a hierarchical design, different instances of the circuit can have different parameters and therefore different component values.

For more information about hierarchical design see Hierarchical Designs. If you have no idea what a hierarchical design is, we suggest you skip this section entirely for the time being!

Example

Parameterized circuits are best illustrated by an example design which you can load from the samples browser (Open Sample on the Proteus home page) under Graph Based Simulation, Low Pass Filter.

The root sheet of this design is shown below:

It consists of a single sub-circuit which has two user properties defining the desired frequency and impedance for the filter. The module attached to the sub-circuit is the actual parameterized circuit (Use either the design explorer or the Next Sheet command to navigate to this sheet).

More information on the Design Explorer can be found here.

The Sub-circuit sheet of the LPF sample

There are several points to note about it:

  • The DEFINE block defines one sheet property: PI. This serves as a constant in the property expression for the capacitor value.
  • The resistor's value field contains the string <IMP>. This syntax with the chevrons (<>) causes the netlist compiler to substitute the <IMP> with value of the IMP sheet property, that is 33k. In this case, no expression evaluation is performed - the substitution is purely literal.
  • The capacitor has a user property assignment (in its property block) which specifies its value as an expression. The E12 function specifies both that the expression should be evaluated by the netlist compiler, and also that it should be rounded to the nearest E12 value. The other options are EVAL (no rounding) and E24 (round to E24 value).

PI, IMP and FREQ are all sheet properties. PI comes from the DEFINE block whilst IMP and FREQ come from the parent sub-circuit.

If we generate an HTML Bill of Materials, you will see the following :

The HTML Bill of Materials for the LPF Sample Design

ISIS has evaluated 1/(2*3.142*33000*10000)) to get approximately 0.000000000482 and then rounded this to the nearest E12 value - 470p.

There are in fact two distinct processes going on in the above example:- property substitution and property expression evaluation. Both have their advantages and disadvantages and the following sections discuss each in more detail.

Property Substitution

This is the mechanism that is used for the resistor value and will operate whenever the netlist compiler encounters a property value containing a property keyword enclosed in chevrons (<>). If the keyword matches a sheet property, then the expression in chevrons is replaced with the value of the sheet property. If no sheet property exists, then a netlist warning is generated and the property is removed from object.

There are two main cases where property substitution is useful:

  • You can use it in a parameterized circuit in which the parameters are not numeric. Packages for PCB design are perhaps the most common example of this - it is all very well getting ISIS to compute that a 470pF capacitor is to be used, but you may still need to package it for PCB design. If you attach to the capacitor the user property:

    PACKAGE=<C1_PACKAGE>

    then you can add the property:

    C1_PACKAGE=CAP10

    to the sub-circuit. When netlisted, the C1 will appear with the property

    PACKAGE=CAP10

    Property expression evaluation cannot be used for this, because CAP10 will not evaluate as a number.
  • The other major use for property substitution is for setting up sweep analyses with Proteus VSM. In this case, you want the simulator to evaluate the expressions, not ISIS and it may then be appropriate to build up component properties using property substitution rather than property expression evaluation. Further discussion of this is given in the VSM manual.

Property Expression Evaluation

In contrast to property substitution which is a purely textual process, property expression evaluation involves ISIS in numerically evaluating a property value that is in the form of a formula, and replacing it with its value. In addition, ISIS can also round the resulting number to an E12 or E24 series value.

There are three forms of syntax:

EVAL (...)

E12 (...)

E24 (...)

In all cases, the parentheses should contain a mathematical expression which may include the operators plus (+), minus (-), times (*) and divide (/) and values. Values can be constant numbers, or the names of sheet properties. Multiplication and division have higher precedence but further levels of parentheses may be used to override this as required.

Some example expressions are shown below:

Expression | Description
EVAL(1/(A+B)) | A and B are sheet properties.
E12(20k+2*F*PI) | 20k automatically treated as 20000.
E24(3+4*5) | Evaluates to 24.

Although in some ways more powerful than property substitution, there are some limitations:

  • The evaluator can only handle numeric values - expressions involving strings are not allowed.
  • You can only reference sheet properties in the formula - you cannot access other object properties or the values of other components.
  • There is no support for mathematical functions (e.g. sin, cosine, square-root) etc.

The Rounding Functions E12(), E24()

The property expression evaluation mechanism supports the ability to round the resulting value to the nearest E12 or E24 value. This prevents parameterized circuits ending up with non-available or multi-digit floating point values.

You should note:

  • Rounding will be disabled for expressions that yield zero or negative values. This is unlikely to be a problem as negative valued resistors and capacitors are hard to come by anyway.
  • The rounding is done on a geometric rather than an arithmetical basis so the mid-point between 3k3 and 4k7 is taken to be approximately 3.94. This, we feel, is in keeping with the thinking behind the E12 and E24 series themselves.
  • Bear in mind that if a parameterized circuit contains several rounded values, there is no mechanism to round them all in the optimum directions, taking into account the way they may interact. This means that for critical filter designs and such like, you may be better computing the values manually (considering the various possible mixes of values) and using parameter substitution to load your chosen values directly into the circuit.

Of course, if you have Proteus VSM, you can run a simulation and see how the values ISIS has chosen affect the circuit performance.


Property Assignment Tool

PROPERTY ASSIGNMENT TOOL (PAT)

Introduction

The property assignment tool is a very flexible way to change component properties on the schematic. For component properties, this has now been largely superseded by the Design Explorer which allows you to edit the schematic properties in an Excel like view. However, the PAT remains a very useful tool for applying other object properties.

See Also:

Design Explorer

The PAT Dialogue Form

The PAT is operated from a modestly complex dialogue form with the following fields:

The Property Assignment Dialogue Form

Field | Description
String | The property assigment , or property keyword on which the selected action will be performed for each object
Count | the initial value for the counter. The counter is incremented on each application of the PAT. The current value of the counter may be included in the string by using the hash (#) character - see examples.
Action | The action you wish to perfrom - see PAT actions.
Apply | The application mode in which you want the PAT to operate - see PAT application modes

PAT Actions

Field Description

ASSIGN

The string should contain a property definition of the form:

keyword=value

and this property will then be assigned to the selected objects.

If you want to assign values that run in a sequence, such as D0, D1,D2, etc then use the hash('#') character in the value and set the initial count as required.

Both user and system properties may be assigned: assigning system properties may cause graphical changes to your drawing.

REMOVE

The string should contain a property keyword only and this property will be removed from the selected objects.

Only user properties can be removed.

RENAME

The string should contain a property assignment of the form:

current_keyword=new_keyword

The name to the left of the assignment is the existing property name you wish to rename; the name to the right is the new name of the property.

Only user properties can be renamed.

SHOW

The string should contain a property keyword only and this property will be made visible for the selected objects.

All user properties and system properties can be shown.

HIDE

The string should contain a property keyword only and this property will be hidden for the selected objects.

All user properties and system properties can be shown.

RESIZE

The string should contain an assignment such as :

REF=20,16

and the given property will be assigned a new height and width for the selected objects. Only textual system properties may be resized.

Changing a labels text size implicitly sets the height and width attributes of the labels text style to be local and that thereafter, changes to the global text style for the label will not be reflected in these labels.

PAT Application Modes

The selected PAT action can be applied to the design in the following ways:

Field Description

On Click

On selecting the OK button, the selection mode icon is selected. Each object on which you click left has the selected action performed upon it.

When you select a different icon the PAT is cancelled.

This mode is the only way to apply the PAT to wires, in order to assign wire labels, ISIS cannot perform PAT assignments on tagged wires because the would be no way for it to know where to put the wire labels.

Local Tagged

The selected action is performed on all tagged objects on the current sheet only.

You can select the tagged objects either individually or with the search and tag command.

Global Tagged

The selected action is performed on all tagged objects across the entire design.

You can select the tagged objects either individually or with the search and tag command.

All Objects

The selected action is performed on all the objects on the design.

The Search & Tag Command

The Search and Tag dialogue allows you to search within a design for components or other objects matching specified criteria. The criteria are specified by the properties of the object type you are searching for. For example, a search for all components with a value of 10k would look like the following :

A Search for all components with a value of 10k

Search results are displayed in a list box at the bottom of the dialogue. You can zoom and centre the schematic on a particular component by double clicking the entry in the list box for that component.

The Search and Tag dialogue form provides the following additional functionality :

A number of mode match criteria are available allowing you greater flexibility when processing searches.

Having completed your original search you can refine or extend your search by changing the search parameters and selecting either the AND or the OR search as required.

You can search across the entire design or only on the current sheet. By default a search across the entire design is selected.

When you zoom into an object from the list box all the search item results will highlight and the dialogue form will exit to allow you an unrestricted view of the schematic. However, the list box automatically repopulates itself with all currently tagged components when you invoke the Search and Tag command. You can browse the search results therefore by simply re-invoking the dialogue box (default shortcut key is ‘T’) and double clicking on the next item in the list.

Examples

The Property Assignment Tool and Search & Tag command provide great power and flexibility when it comes to manipulating object properties. However, they can seem somewhat daunting to beginners. With this in mind, some step by step examples to get you started are given below.

To label a set of bus taps:

  1. Invoke the PAT.(default keyboard assignation is ‘A’).
  2. Set the string to NET=D# and click OK. The action will have defaulted to Assign and the mode to On Click.
  3. Click left on each wire where you want the wire label to appear. The cursor keys and the enter key can be used as an alternative to the mouse. The wires you click on will be assigned new wire labels in the sequence D0, D1, D2, etc.

Labelling a set of bus taps with the Property Assignment Tool

To assign a package to all the BC108s in a design:

  1. Invoke the Search and Tag command (by default this is mapped to the 'T' key).
  2. Set the property to VALUE and the string to BC108, then click OK. The mode will have defaulted to Equals. Exit the dialogue with the Done button to highlight all the search results. All the components with the value BC108 will now be tagged.
  3. Invoke the PAT (default keyboard shortcut is ‘A’).
  4. Set the string to PACKAGE=TO18 and click OK. The action will have defaulted to Assign and the mode to Global Tagged (assuming there were tagged BC108s). All the tagged BC108s will be given the new user property.

To rename all ITEM properties to CODE properties:

  1. Invoke the PAT.
  2. Set the string to ITEM=CODE, the action to Replace and the mode to All Objects, then click OK. All objects with the property ITEM=value will be replaced with a property CODE=value.

Renaming properties globally with the Property Assignment Tool

To hide all package properties:

  1. Invoke the PAT.
  2. Set the string to PACKAGE, the action to Hide and the mode to All Objects, then click OK. All the PACKAGE properties will be hidden

Hiding package properties globally with the Property Assignment Tool

To resize the component references:

  1. Invoke the PAT.
  2. Set the string to REF=10,8, the action to Resize, and the mode to All Objects, then click OK. All the component references will be shrunk to the new size.

Resizing component references globally with the Property Assignment Tool

To assign larger packages to 1000uF capacitors:

  1. Invoke the Search and Tag command (by default this is mapped to the 'T' key on your keyboard).
  2. Set the property to DEVICE and the string to CAP ELEC, then click the Search button. This will display all the electrolytic capacitors in the list box at the bottom of the dialogue box.
  3. Change the Search mode to AND Search.
  4. Set the property to VALUE, the string to 1000u, and the mode to Begins, then click Search. This will display all capacitors with the values 1000u or 1000uF. Use the OK button to exit the dialogue and tag all the components matching the search results.
  5. Invoke the PAT.
  6. Set the string to PACKAGE=ELEC-RAD30 and click OK. The action will have defaulted to Assign and the mode to Global Tagged (assuming there were tagged capacitors). All the tagged capacitors will be given the new package.


PROPERTY DEFINITIONS

Creating Property Definitions

Property definitions are entered using the Component Properties page in the Make Device dialogue form. For more detailed information use the context sensitive help on the dialogue form and/or refer to the instruction on making a device.

The Component Properties Page of the Make Device Dialogue Form

You can also create property definitions implicitly by adding fields to the Bill of Materials report. For example, if you add a field for Minimum Order Quantity (MoQ) to the BOM, you can then populate it with values per component and apply changes back to the schematic. This will update your property definitions with the specification for the MoQ property. For more information please see the chapter on Bill of Materials.

If you add property definitions through Make Device then that definition and value is stored in the Library for re-use in other projects. If you use the Property Editor in the Bill of Materials the changes are applied only to the current schematic. You can of course then use the global Compile to Library command to store the modified parts for future re-use.

Default Property Definitions

A number of properties are will be applied to most devices that you create. For example, anything that is going onto a PCB will need a PACKAGE property, and anything that has a simulator model will need a MODFILE, MODEL or SPICEMODEL property. You can also define a property definition for the part value. This allows you to change the description of the part value, and to provide range checking for it in the same way as for other properties.

You may also want to apply your own properties such as STOCKCODE, SUPPLIER or COST to most of the devices that you create.

To make this easier, there is a list of default property definitions which can be defined using the Set Property Definitions command. The properties defined with this command are available on the Name field combo on the Properties tab of the Make Device dialog form

Alternatively, for properties you would like to see in the BOM, you can work directly through the Bill of Materials module.

In either case, the information you define is held in the file PROPDEFS.INI located in library directory of your Proteus installation.


COMPONENTS

Introduction

A component is an instance of a device, picked from one of the device libraries. Since some devices are multi-element it follows that in some cases, several components on the schematic may, in fact, all belong to one physical component on the PCB. In such cases, the logical components are annotated with names such as U1:A, U1:B, U1:C, U1:D to indicate that they all belong to the same physical part. This form of annotation also enables ISIS to select the correct set of pin numbers for each element.

Apart from physical terminals, components are the only objects you can place which will generate physical entities in the PCB design. Everything else you place serves either to specify connectivity, or else is present only for the purpose of human readability. This is an important point, since attempts to use other ISIS objects (in particular, graphics symbols) to represent objects on the PCB will fail.

Selecting Components from the Device Libraries

When you start ISIS on an empty drawing, the device selector is empty. Before you can place any components, you must first pick them from the libraries into the selector.

To select components from the device libraries:

  1. Select the component icon from the Mode Selector toolbar.
  2. Click left on the 'P' Button on the Object Selector. This will cause the Device Library Browser to appear as shown below.

  3. Either enter one or more keywords or else navigate through the category and subcategory columns to filter down the indexing system and locate the desired library part.
  4. Double click on a part in the results list in order to select it into the design.
  5. When you have finished picking devices, use the ok button to close the dialogue and return to ISIS.

See Also:

Picking Parts from the Library (Tutorial)

Making New Devices (Tutorial)

Device Libraries

Placing Components

Component placement follows the general scheme outlined in Object Placement.

To place a component:

  1. If the device type you want is not listed in the Object Selector, first select component mode and then pick it from the libraries as described in the previous section.
  2. Highlight the device name in the Object Selector. ISIS will show a preview of the device in the Overview Window.
  3. Use the Rotation and Mirror icons to orient the device according to how you want to place it.
  4. Click left in the Editing Window to enter placement mode. At this point a shadow outline of the component will appear.
  5. Move the mouse to the point and which you want to place the component and left click again to commit and exit placement mode.

Replacing Components

To replace a component:

  1. Proceed up to stage four in the steps for placing a component. You should now have a shadow component following the mouse.
  2. Move the shadow component over the existing component such that at least one of the pins is exactly over a pin on the existing component and the mouse itself is over the existing component.
  3. Click left to replace the component on the schematic with the one you are currently placing.

You can also replace a component by using the Property Assignment Tool with the syntax 'DEVICE=<component_name>' in on-click mode. This may of course result in chaos if the part is wired !

Editing Components

A component may be edited using any of the general editing techniques (see Editing an Object), and also specifically by using the Edit Component command (default keyboard shortcut key 'E'). As with most editing features in PROTEUS a dialogue form will appear with the appropriate editing fields. However, with the Edit Component dialogue form the available fields are dependant on the given properties of the component. You will find, therefore, that this dialogue form can be radically different for different components. Context Sensitive Help is available for the dialogue form but please note that, for the reasons given above, some fields may not have a help topic associated with them.

Having said that, several specific attributes are common to components and can be found at the bottom of the dialogue form. Three in particular are used to exclude the component from various other modules and are discussed below:

Exclude from Simulation

When checked the component will not be included for simulation purposes. This should be used for example with connectors which have no meaning in a simulation but are relevant in PCB layout.

Exclude from PCB Layout

When checked the component will not be included for PCB layout purposes. Obvious examples include virtual instruments (e.g. oscilloscope) which is relevant for simulation but clearly not for layout.

Exclude from Bill of Materials

When checked the component will not be included in the Bill of Materials. This is useful where you want a single board fabricated that might satisfy scalable product. For example, a lower cost product might not include bluetooth connectivity but would still use the same mainboard as the more expensive variant.

Gate-Swapping Components

The Edit Component dialogue form also enables gate-swap and re-annotation of multi-element parts. A multi-element part is a single physical parts with several contributing logical elements. The common database deals primarily with parts and it is therefore not possible for elements to supply conflicting data. This is most obviously seen with properties; unlike earlier versions, changing a property in one element will automatically change that property in all of the other elements of the part.

The annotation and swapping of gates in the Edit Component dialogue now works slightly differently. Take the following as an example:

When placed an element reflects both it's part reference (e.g. U1) and it's element identifier (e.g. A). In the edit component dialogue these are now separated into two fields.

Part Reference

Changing the part reference will re-annotate all of the elements. For example, changing U1 to U4 will change all of the U1 elements to U4 elements. You will get a warning if you change this annotation to one that is already in use (for example U2).

Element

Changing the element will swap the current element with the one selected from the combo box. Pressing the new button will change the annotation to the next available element not currently on the schematic.

Examples

To re-annotate U1 to U4

Edit one of the U1 elements and change the part reference to U4

To gateswap U4:A with U4:C

Edit the U4:A element and change the element to U4:C.

To annotate a heterogeneous part

If you have a multi-element heterogeneous part such as a relay with a coil and contacts the process is similar to that in previous versions. When you place the elements on the schematic they will be un-annotated as manual annotation is required for heterogeneous parts.

The annotation of each element is of the form

<part ref> : <element>

and is entered in the part reference field of the dialogue. For example, the coil might be annotated as RL1:A and the contacts as RL1:B and RL1:C

Assuming the contacts are identical, you can subsequently gateswap them via the element field of the Edit Component dialogue.

The gateswap will only work if the contacts are instances of the same library part. Since they are identical, you need only one library part, regardless of how many contacts are placed on the schematic.

Component Properties

Components have the following system properties:

Property Name | Description
REF | Component Reference designator label.
VAL | Component value label.
VALUE | Component value label or the VALUE user property if the assigned text is too long for the label.
DEVICE | Library part. If assigned, this will invoke the automatic replacement logic which will attempt to maintain connectivity.

If any other property names (e.g. RoHS, TOLERANCE, etc.) are assigned, then these will create user properties in the component's text block.

See Also:

Bill of Materials (Properties)

Property Assignment Tool

Make Device (Properties)

Visual Packaging Tool (Properties)

Hidden Power Pins

If a component has been defined with hidden power pins, then the nets to which these will be connected can be viewed or edited by clicking the Hidden Pins button on the Edit Component dialogue form as shown below.

The Hidden Pins button on the Edit Component Dialogue Form

By default, hidden pins connect to a net of the same name - for example, a hidden VDD pin will connected to VDD, a hidden VSS pin to VSS and so on.

See Also:

Power Rail Configuration

Hidden Pins


Dots

JUNCTION DOTS

Introduction

Junction dots are used to mark interconnection between wires. In general, ISIS will place and remove them automatically but it is sometimes useful to place a dot at a specific position and then route wires to and from it.

Wires which touch or cross are never considered connected unless there is a dot at the point of contact. Conversely, where there is a dot, there will always be a connection unless you have contrived to superimpose wires and dots by dragging or moving them into contact with each other.

You can customize the appearance of junction dots by editing the WIRE DOT graphics style. See Editing Global Styles for more information. You can also set their size and shape using the Set Junction Dots command

Placing Junction Dots

To place a dot:

  1. Select Junction dot icon from the Mode Selector Toolbar.
  2. Point where you want the dot to be placed in the Editing Window.
  3. Click left to place the dot.

Auto Dot Placement

ISIS will automatically place a dot whenever you route a wire off an existing wire such that there are then 3 dots at that point.

Auto Dot Removal

When a wire or wires are deleted, ISIS will detect where this leaves dots with two or no connected wires. Such dots are automatically removed unless this would result in an unbroken wire loop.


WIRE LABELS

Introduction

Wire labels are used to assign particular net names to groups of wires and pins, and also to assign net properties to specific nets. They are not in fact proper objects in the general scheme of the software. Instead, their behaviour is similar to other labels such as the reference and value labels of a component. It follows that the procedures for their placement and removal are somewhat different from those for other objects.

See Also:

Netlist Generation

Placing and Editing Wire Labels

To place or edit a wire label:

  1. Select the Wire Label icon from the Mode Selector toolbar.

  2. If placing a new label, point at the wire at the position where you want the label to be placed or, for an existing label, point anywhere along the wire or at the label itself.

  3. Click left to place the label. The Edit Wire Label dialogue form will be displayed.

  4. Type in the required text for the wire label.
  5. Click OK or press ENTER to close the dialogue form.

See Editing Local Styles for more details of the controls on the Style tab of the dialogue forms.

You cannot place a wire label on anything apart from a wire.

You can also place a wire label from the right click context menu of a wire.

You can place more than one label on a wire. If you wish them all to have the same name, and for all of them to update automatically whenever any of the names are changed, the click the Auto-Sync checkbox.

ISIS will orient the wire label according the orientation of the wire segment on which it is placed. This can be changed on the Edit Wire Label dialogue form.

To change the appearance of a wire:

  1. Ensure that the Wire Label Icon is not selected.
  2. Tag the wire by pointing at it and right clicking.
  3. From the resulting context menu select Edit Wire Style to launch the dialogue form.
  4. Uncheck the Follow Global? checkboxes of those style attributes of the graphics style you want to change. If a style attribute and its Follow Global? checkbox are both disabled it is because the style attribute is not meaningful given other attribute settings, either locally or through following the global style attribute.
  5. Set the style attribute to the required setting.
  6. Press ENTER or click the OK button to close the dialogue form and keep the changes. Press ESC or click the CANCEL button to close the dialogue form and abandon changes.

To change the appearance of all wires on the schematic, use the Set Graphics Style command on the Template menu to edit the WIRE graphics style.

Configuring the style and appearance of wires in ISIS

See Also:

Graphics and Text Styles.

Deleting Wire Labels

To delete a wire label:

  1. Select the Selection icon from the Mode Selector toolbar.

  2. Left click on the label. Both the wire and the label with be selected. Care is required to actually left click on the label and not the wire itself.
  3. Right click and select 'Delete Label' from the resulting context menu. If this option is not available on the context menu then you have clicked on the wire and not on the wire label. Try zooming in around the bus label to ensure accuracy.

Using a Wire Label to Assign a Net Name

The normal use of wire labels is to indicate that a particular wire, and all the pins to which it is graphically connected, belong to a given net. Then, that group of pins are deemed connected to any other groups of pins which have also been assigned the same net name, even where there is no graphical connection. Occasionally, one may also label particular nets purely for human benefit.

Net name AGND

See Also:

Net Names

Using a Wire Label to Assign a Net Property

Wire labels are most often used to specify the net class for PCB Layout. The net class is essentially a grouping of nets which have the same characteristics - for example, POWER, or SIGNAL. Creating your own net classes allows you to set up trace and via styles for routing the board and also to define more granular board constraints (design rules) in the layout module.

To specify a wire as belonging to a net class

1) Right click on the wire and select Place Wire Label from the resulting context menu.

2) Switch to the Net Class tab and click the new button to create a new net class.

3) Enter a name for the net class and then define the routing styles, via type and ratsnest display on the dialogue form.

4) Click the OK button to commit placement.

Having set up net classes in ISIS you can define design rules and clearance with respect of net classes from the Design Rule Manager on the Technology Menu in the ARES Layout module.

See Also:

Routing Classes

Wire Label Properties

A wire or wire label (they are equivalent for this purpose) has the following property:

Property Name | Description
NET | The wire label text

Wire labels can also be assigned via the Property Assignment Tool but only when it is used in On Click mode. This is because there is no way for ISIS to determine where a wire label should be placed on a tagged wire, unless you mark the position with the mouse.


SCRIPTS

Introduction

A major feature of ISIS is its ability to support free format text scripts, and the numerous uses it puts them to. These uses include:

  • Defining variables for use in property expressions and parameter mapping.
  • Defining primitive models and scripts for use with the VSM simulators.
  • Annotating designs with substantial quantities of text.
  • Storing property and packaging information when a component is decomposed.

Placing and Editing Scripts

The procedure for placing and editing scripts are almost identical as both operations involve the edit script block dialogue form.

To place a script:

  1. Select the Script Icon from the Mode Selector toolbar.
  2. In the Editing Window, point to where you want the top-left of the script to be and click left to launch the Edit Script Block dialogue as shown below.

  3. Enter the text for the new script in the Text field. You can also adjust the attributes of a script at this time - see To Edit a Script below for full details of the dialogue form.
  4. Close the dialogue form with the OK button to place the new script or with the CANCEL button to quit the form and cancel the script placement.

To edit a script:

  1. Either :
    (a) Tag the script by pointing at it and clicking right and then select edit from the resulting context menu.
    (b) Point at the script with the mouse and use the assigned keyboard shortcut to edit it (by default this is CTRL+E).
    (c) Entering Selection mode via the selection icon and double clicking on the script block.
  2. Adjust the script attributes as required.
  3. Close the Form. To close the form and save changes either click the OK button or use the CTRL+ENTER keys. To close the form and abandon changes, either click the CANCEL button or use the ESC key.

See the graphics and text style tutorial under Editing Local Styles for more details of editing local text styles.

You can resize the Edit Script Block dialogue form to make the Text field bigger and then save the size using the Save Window Size command on the Window’s ‘system’ menu (click on the button at the far left of the title bar).

Script Block Types

ISIS currently supports the following script block types:

Script Block Type | Block Header
Sheet Global Net Property Assignment | *NETPROP
Sheet Property Definition | *DEFINE
Parameter Mapping Table | *MAP ON varname
Model Definition File | *MODELS
Named Script | *SCRIPT type name
SPICE Model Script | *SPICE type name

Part Property Assignments (*FIELD)

Field Blocks are deprecated for new designs in Proteus 8. Non-physical parts can be packaged directly in ARES and properties added through the Bill of Materials property editor. The text below remains in place temporarily during transition.

See Physical Terminals for more information on physical terminals.

See ISIS and ARES regarding packaging considerations for PCB Design.

Field blocks are primarily intended to facilitate the assignment of properties to connectors made from physical terminals. A special means to do this is required since when physical terminals are used, there is no single entity on the schematic that represents the connector and to which properties could be directly attached.

An example block is shown below:

*FIELD

J1,PACKAGE=CONN-D9

J2,PACKAGE=CONN-D25

This assigns connector J1 the PCB package for a 9 pin D connector, and J2 the package for a 25 way connector.

You can assign properties to ordinary components as well, but there is generally little point since you can add them directly to the components.

Sheet Global Net Property Assignments (*NETPROP)

A net property is normally assigned by the placement of a wire label with the syntax:

<prop>=<value>

However, there are occasions when you wish a large number of nets to carry the same property. Most often, the requirement is for all the circuitry on a particular sheet to be of a particular type (perhaps extra wide tracking for a power supply) and it is for this purpose that a NETPROP block may be used. For example, if the block:

*NETPROP

CLASS=POWER

is included on a sheet, then all nets whose wires do not carry explicitly net properties will be assigned the net property CLASS=POWER.

See Using a Wire Label to Assign a Net Property for more information about net properties.

Sheet Property Definitions (*DEFINE)

A sheet property is essentially a variable which is defined on a given sheet and may be used in property expressions within components' property lists on that sheet. Sheet properties defined on the root sheets of a design, also appear in the netlist and may be used as control parameters by software such as the VSM simulators that reads the netlist.

An example block is shown below:

*DEFINE

TEMP=40

MINSTEPS=100

This defines two properties TEMP and MINSTEPS, and would be placed on the root sheet of a design such that they would be passed to VSM as simulation control parameters.

Parameter Mapping Tables (*MAP ON varname)

This is considered a highly advanced topic, and one which is only of great importance if you are involved in creating universal models for use with VSM. Further information on this is given in the VSM manual, but for completeness, we provide an example parameter mapping table here:

*MAP ON VALUE

7400 : TDLH=12n,TDHL=7n

74LS00 : TDLH=10n,TDHL=6n

74S00 : TDLH=5n,TDHL=3n

This table would be placed on the model schematic for a 2 input NAND gate, and would select different values for TDLH and TDHL according to the value (i.e. type) of the parent object. Also on the child sheet would be a NAND_2 primitive with the properties:

TDLH=<TDLH>

TDHL=<TDHL>

At netlist time, the parameter mapping table would examine the parent object's VALUE property and if, say, it were 74LS00, then the sheet properties TDLH=10n and TDHL=6n would be defined for that instance of the model. Then, on processing the NAND_2 primitive, these values would be substituted for <TDLH> and <TDHL> such that the primitive would acquire the correct timing to model a 74LS00.

A DEFAULT case is also supported.

Model Definition Tables (*MODELS)

These blocks are used only with the VSM simulators (currently, in fact, only with the Analogue simulator) and provide a shorthand method for managing the large numbers of properties that some of the simulator primitives use. For example, the bipolar transistor model has over 30 different properties and it would be fairly hopeless if you had to assign all of these individually for each transistor on the circuit.

Instead, you can use a MODELS block to define the properties for a particular type of transistor, and then refer to that set of properties using a model name.

An example block is shown below:

*MODELS

741_NPN : BETAF=80,ISAT=1E-14,RB=100,VAF=50,\

TAUF=0.3E-9,TAUR=6E-9, CJE=3E-12,CJC=2E-12

741_PNP : BETAF=10,ISAT=1E-14,RB=20, VAF=50,\

TAUF=1E-9, TAUR=20E-9,CJE=6E-12,CJC=4E-12

This defines the two transistor types used in a 741 IC. Individual transistors could then be given the values 741_NPN or 741_PNP and VSM would automatically give them the characteristics defined in the model table.

See the VSM manual for further discussion of primitive models.

Named Scripts (*SCRIPT scripttype scriptname)

In certain circumstances it is useful to be able to export a named block of text to an external application. In particular the SPICE and SPICE-AGE netlist formatters make use of the named scripts PSPICE and SPICE-AGE to supply control information for the simulations.

A typical named script block is shown below. Note that the end of the named script is marked by an ENDSCRIPT keyword, though this is optional if there are no other blocks in the script object.

*SCRIPT PROGRAM 7493

// Declare linkage to pins and local variables:

PIN CKA, CKB, RA, RB

PIN QA,QB,QC,QD

INT counta = 0, countb = 0

// Handle single-bit ‘A’ counter and assign output:

IF RA=H THEN

counta = 0

ELIF CKA=HL THEN

counta = (counta+1) % 2

ENDIF

QA = counta & 1

// Handle three-bit ‘B’ counter and assign output:

IF RB=H THEN

countb = 0

ELIF CKB=HL THEN

countb = (countb+1) % 8

ENDIF

QB = countb & 1

QC = countb & 2

QD = countb & 4

*ENDSCRIPT

SPICE Model Script (*SPICE)

These scripts allow SPICE input cards to be typed on the schematic and loaded directly into PROSPICE at simulate time. This can be handy if you want to develop or test SPICE models in native SPICE format in the native SPICE format.

Further Information on this is provided in the Proteus VSM manual.


BUSES

Introduction

A bus is a kind of shorthand for a large number of wires, and is commonly used on microprocessor schematics. ISIS has an unprecedented degree of support for buses, including not only the ability to run buses between hierarchy modules but also the facility to define library parts with bus pins. Thus it is possible to connect a CPU to an array of memories and peripherals by single bus wires, rather than a complex arrangement of wires, bus entries and buses.

Placing Buses

Buses are placed in very much the same way as ordinary wires except that they must run to and from bus connection points, rather than wire connection points. Also, unlike wires, buses may be placed in isolation from any other objects.

To place a bus:

  1. Select the Bus icon from the Mode Selector toolbar.
  2. Point the mouse where you want the bus to start. This may be a bus pin, an existing bus, or free space on the drawing.
  3. Click left to start the bus, then click again at each corner of the desired bus route.
  4. To finish the bus on a bus connection point (a bus pin or an existing bus) point at it (the cursor will change to indicate that you are over the connection point) and click left. To finish the bus in free space, double left click the mouse.

Bus Labels

A bus may be labelled in exactly the same way as a wire. However, ISIS defines a special syntax for bus labels.

To place a bus label :

  1. Select the Wire label icon from the Mode Selector toolbar.
  2. Point on the bus at the position where you want the label to be placed.
  3. Click left to place the label. The Create Wire Label or Edit Wire Label dialogue form will be displayed.
  4. Type in the required text for the wire label. This should be something like D[0..7] or A[8..15]. If you omit the range specification then the bus will take its base as zero and its width from the width of the widest bus pin connected to it. In general, however, you should always use range specification.
  5. Click OK or Press ENTER.

You cannot place a wire label other than on a wire or a bus.

You cannot place more than one wire label on one section of a bus. Attempting to do so will edit the existing wire label.

ISIS will orient the wire label according the orientation of the wire segment on which it is placed. This can be changed on the Edit Wire Label dialogue form.

To edit a bus label:

  1. Select the Selection icon from the Mode Selector Toolbar.
  2. Left click on the bus label. Both the bus and the bus label with be selected. Care is required to actually left click on the label and not the bus itself.
  3. Right click and select edit label from the resulting context menu. If this option is not available on the context menu then you have clicked on the bus and not on the bus label. Try zooming in around the bus label to ensure accuracy.

To delete a bus label:

  1. Select the Selection icon from the Mode Selector toolbar.
  2. Left click on the label. Both the bus and the bus label with be selected. Care is required to actually left click on the label and not the bus itself.
  3. Right click and select delete label from the resulting context menu. If this option is not available on the context menu then you have clicked on the bus and not on the bus label. Try zooming in around the bus label to ensure accuracy.

To change the appearance of a bus:

  1. Ensure the Wire Label icon is not selected.
  2. Tag the bus by pointing at it and clicking right.
  3. Select the Edit Wire Style dialogue from the resulting context menu.
  4. Uncheck the Follow Global? checkboxes of those style attributes of the graphics style you want to change. If a style attribute and its Follow Global? checkbox are both disabled it is because the style attribute is not meaningful given other attribute settings, either locally or through following the global style attribute.
  5. Set the style attributes to the required settings
  6. Press ENTER or click the OK button to close the dialogue form and keep the changes. Press ESC or click the CANCEL button to close the dialogue form and abandon changes.

To change the appearance of all buses on the schematic, use the Set Graphics Style command on the Template menu to edit the BUS WIRE graphics style.

Wire and Bus Junctions

Sometimes, even with the provision of bus pins, it is necessary to tap off a single signal from a bus, perhaps for decoding purposes. From a purely graphical point of view this is just a matter of placing a wire that ends on the bus:

To place a bus tap:

  1. If you plan to route the wire from the bus to another object, ensure that the Bus icon is not selected.
  2. Place the wire in the usual way. The bus will behave like an ordinary wire in these circumstances.

It may be helpful to you to understand that when you place a wire in this way, automatic dot placement will operate to give the wire and bus something to connect to. However, you will not see the dot as it adopts the same colour and width as the bus.

Having got a wire joined to a bus, you must specify which signal from the bus you are tapping.

Double clicking a component pin to invoke Wire Auto-repeat is particularly useful here if you are tapping several lines from pins to bus.

To annotate a bus tap :

  1. Ensure that the bus carries a bus label such as D[0..7]. This label would define eight nets called D0, D1, ... , D7
  2. Place a wire label on the wire to indicate which signal it is tapping.

An example of this is shown below :

Bus Taps on a schematic

If the bus doesn't connect to any bus pins or bus terminals, you can omit step [1]. In these circumstances, the bus itself plays no part at all in the determining the design connectivity.

You can also place bus taps semi-automatically via the Property Assignment Tool; refer to the PAT examples topic for more information.

Placing a bus tap without annotating it will be reported as a netlist error as it is a wholly ambiguous situation. ISIS cannot know which signal you are trying to tap. Nor can a human reader for that matter!

Bus Properties

A bus or bus label (they are equivalent for this purpose) has the following property:

Property Name | Description
NET | The bus label text


SUB-CIRCUITS

Introduction

Sub-circuits are used to attach lower level sheets to higher level sheets in a hierarchical design. Each sub-circuit has a name that identifies the child sheet, and a circuit name that identifies the child circuit. On any given sheet, all the sub-sheets should have different sheet names, but may - and often will - have the same circuit names.

More information about hierarchical design is given in Hierarchical Designs.

Sub-circuits can also have property lists, and this leads to the possibility of parameterized circuits in which different instances of a given circuit can have different part values (or other properties) as well as independent annotations.

Further information about this powerful feature are given in Parameterized Circuits.

Placing Sub-Circuits

To place a sub-circuit box:

  1. Select the Sub-circuit icon from the Mode Selector Toolbar.

  2. Left click the mouse at the point in the editing window where you want to draw the sub-circuit outline.
  3. Move the mouse to define the size of the sub-circuit and then left click the mouse again to commit the shape and place the sub-circuit.

To place sub-circuit ports:

  1. Select the Sub-circuit icon from the Mode Selector Toolbar.

  2. Choose the port type that you want from the Object Selector. Your choice here is dependant on the function of the port.

  3. Point where you want the port. This must be a point on the left or right edge of the sub-circuit to which you want to attach the port. The mouse cursor will change to the hot placement cursor to indicate legal points where you can place a port.

  4. Left click the mouse to place the port.

Having placed a port or ports, you must annotate them. Hierarchical design works by connecting the ports on the parent object with like named logical terminals on the child sheet. It follows that both the ports and the terminals must be given unique names. This can be achieved in a variety of ways:

  • Edit the terminal label using any of the methods described in Editing an Object.
  • Use the Property Assignment Tool to assign the NET property of one or more ports. This is especially effective if a group of ports have names which run in an alphanumeric sequence.

It is quite legal to connect buses to ports. In this case, the name for the port should generally define the range for the bus, as in D[0..7], although this is not mandatory. If no range is given, ISIS will use the range given for the bus section that connects to the port, or if that has no name or range then the width will be taken from whatever bus pins connect to the bus.

Placing a port without annotating it will be reported as a netlist error since such an object has no meaning and cannot be tied up with anything on the child sheet.

Information on naming sub-circuits and their general usage can be found in Hierarchical Designs.

Editing Sub-Circuits

A sub-circuit may be resized using the general procedure described in Resizing an Object and edited using any of the general editing techniques described in Editing an Object.

See Parameterized Circuits for further information on parameterized circuits.

Sub-Circuit Properties

Sub-circuits have the following system properties:

Property Name | Description
NAME | The sub-circuit instance name. This is also used as the name for the child sheet.
CIRCUIT | The name of the child circuit. If you do not assign this, ISIS will choose an automatic name when you first enter the child sheet.

If any other property names are assigned, then these will create user properties in the sub-circuit's text block. Such properties then become sheet properties for the child sheet and may be used in property expressions.


TERMINALS

Introduction

Terminals are used for specifying the interface to a circuit - ISIS does not allow a wire to 'float' - both ends must connect to something so all the inputs and outputs in your design will be indicated by terminals.

There are two types of terminal - Logical Terminals and Physical Terminals. The two are distinguished purely by the syntax of their labels.

You can customize the appearance of terminals by editing the TERMINAL graphics style as shown below. See Editing Global Styles for more information

The Edit Terminal Style dialogue form

Logical Terminals

A logical terminal serves merely to donate a net name to the wire to which it connects. Groups of wires with one or more net names in common are taken to be connected by the netlist generator. Logical Terminals thus provide a means to connect things together without using wires. In particular they provide the means make connections between the sheets in a multi-sheet design.

As with Wire Labels and Bus Entries, the net name can contain any alphanumeric characters plus the hyphen ('-') and underscore ('_'). Spaces can be used within PROTEUS but may cause problems for other software.

Logical terminals may also connect to buses. This provides an extremely efficient way to run buses up and down a hierarchical design.

See Net Names for discussion of the role of logical terminals in netlisting.

Logical terminals are vital to connectivity in multi-sheet designs. If you are using sub-circuits or working with sizeable schematics please refer to the section on Hierarchical Designs for more information.

See Connecting NC Pins for information on using NC terminals to indicate NC status on component pins.

Physical Terminals

A physical terminal represents a pin on a physical connector. For example, a terminal with the name:

J3:2

is taken to be pin 2 of connector J3. Whilst it is perfectly possible to deal with connectors in exactly the same way as all other components (i.e. define a device to represent them), using Physical Terminals has the advantage that the pins can be placed wherever it is most convenient.

Physical terminals will appear as parts in the ARES parts bin and are then packaged when you place them on the board.

Alternatively, you can specify the package type for the part via a FIELD property assignment block (see Part Property Assignments (*FIELD)) must be used as there is no actual component to edit.

Note that a bus terminal may not be physical, as there is no means to specify the pin numbering for the individual pins.

Placing Terminals

ISIS supports an unlimited variety of terminal symbols. However, when you first select the Terminal icon, a basic set of 7 types are automatically pre-loaded into the Object Selector.

To place a terminal:

  1. If the terminal type you want is not listed in the Object Selector, first pick it from the symbol library.
  2. Highlight the terminal name in the Object Selector. ISIS will show a preview of the terminal in the Overview Window.
  3. Use the Rotation and Mirror icons to orient the terminal appropriately.
  4. Left click the mouse on the Editing Window to enter placement mode and the move the mouse to the position where you want to place the terminal.
  5. Left click the mouse again at this point to commit the changes and exit placement mode.

Having placed a terminal, you must then annotate it since an unannotated terminal will be ignored by the netlist compiler. There are a variety of approaches:

  • Edit the terminal label using any of the general methods described in Editing an Object.
  • Select the terminal label from the drop down combo box. This list contains all the existing named nets on the current design.
  • Use the Property Assignment Tool to assign the NET property of one or more terminals. This is especially effective if a group of terminals have names which run in an alphanumeric sequence.

It is quite legal to connect buses to terminals. In this case, the name for the terminal should generally define the range for the bus, as in D[0..7], although this is not mandatory. If no range is given, ISIS will use the range given for the bus section that connects to the port, or if that has no name or range then the width will be taken from whatever bus pins connect to the bus.

Placing a terminal without annotating it will be reported as a netlist error since such an object has no meaning, logically or physically.

Editing Terminals

A terminal may be edited using any of the general editing techniques (see Editing an Object). For your convenience with logical terminals a list of existing named nets is available as a drop down combo box allowing you to easily specify the net name.

The Edit Terminal dialogue form showing a drop down list of net names

In addition, since terminals often appear in groups, the Property Assignment Tool can be put to good use for annotating and setting the electrical type of terminals.

Terminal Properties

Terminals have the following system properties:

Property Name | Description
NET | The terminal net label.
SYMBOL | The symbol used for the terminal. This can be one of the standard terminal types, or else the name of a user defined terminal symbol.
NAME | The electrical type of the terminal. This can be any of PASSIVE, INPUT, OUTPUT, BIDIR or POWER.


PIN OBJECTS

Introduction

A full description of how to create and edit your own devices is given in Library Facilities. Here, we just discuss the placement and editing of pin objects. These are used to represent each drawn pin of a device element and consist of some graphics (often just a single line) plus the capacity to carry and display a pin name and a pin number.

Note that you cannot wire off a pin object - you can only connect to pins that belong to fully constituted components that have been placed in the usual way

Placing Pin Objects

An unlimited number of pin object types may be defined, and a good selection are provided in SYSTEM.LIB. However, when you first select the Device Pin icon, a basic set of 6 types are automatically pre-loaded into the Object Selector and these will suffice for most purposes.

To place a pin:

  1. If the pin type you want is not listed in the Object Selector, first pick it from the symbol library.

  2. Highlight the pin type name in the Object Selector. ISIS will show a preview of the pin in the Overview Window.

  3. Use the Rotation and Mirror icons to orient the pin according to how you want to place it.

  4. Left click the mouse on the Editing Window to enter placement mode.
  5. Move the mouse to the position where you want to place the pin object (a 'shadow' pin will follow the mouse in this mode).

  6. Left click the mouse again to commit the pin at that position and exit placement mode.

Having placed a pin, you will generally want to modify it to give it a pin name, number and electrical type. There are a variety of possibilities:

  • Edit the terminal label using any of the methods described in Editing an Object.
  • Use the Property Assignment Tool to assign the NAME, NUMBER and TYPE property of one or more pins This is especially effective if a group of ports have names which run in an alphanumeric sequence.

If a pin represents a data or address bus, you may want to use a bus pin In this case, pin numbers can only be specified using the Visual Packaging Tool. Equally, if the device has multiple elements, (e.g. a 7400) you must again specify pin numbers for each element using the packaging tool. In either of these cases, you should leave the pin numbers of the pins blank.

Please see the section on the Visual Packaging Tool for more information about packaging considerations.

Editing Pin Objects

A pin may be edited using any of the general editing techniques (see Editing an Object). In addition, since pins often appear in groups, the Property Assignment Tool can be put to good use for defining pin names, numbers and electrical types.

Pin Object Properties

Pin objects have the following system properties:

Property Name | Description
NAME | The pin name.
NUM | The pin number.
SYMBOL | The symbol used for the pin. This can be one of the standard pin symbols, or else the name of a user defined pin symbol.
TYPE | The electrical type of the terminal. This can be any of PASSIVE, INPUT, OUTPUT, BIDIR, TRISTATE, PULLUP, PULLDOWN, NC or POWER.


2D GRAPHICS

Introduction

ISIS supports the following types of 2D graphics objects: lines, boxes, circles, arcs, scalable text and composite symbols. These are intended for use both directly on the drawing, for example to draw division lines and sectional boxes around parts of a design, and also for creating new library parts (devices, symbols, pins and terminals).

Placing 2D Graphics

The following are the procedures for placing the various types of graphic objects.

To place a line:

  1. Select the Line icon from the Mode Selector.
  2. Select the graphics style you want from the Object Selector.
  3. Click left on the Editing Window to mark the start of the line.
  4. Move the mouse to the end point of the line and click left again to place.

To place a box:

  1. Select the Box Icon from the Mode Selector.
  2. Select the graphics style you want from the Object Selector.
  3. Click left on the Editing Window to mark the start of the box.
  4. Move the mouse to size the box and the click left again to place.

To place a circle:

  1. Select the Circle Icon from the Mode Selector.
  2. Select the graphics style you want from the Object Selector.
  3. Click left on the Editing Window where you want the center of the circle to be placed.
  4. Move the mouse to size the circle and the click left again to place

To place an arc:

  1. Select the Arc Icon from the Mode Selector.
  2. Select the graphics style you want from the Object Selector.
  3. Consider the arc as lying in one quadrant of an ellipse - you will first define this quadrant. Point at the position where one end of the quadrant will lie and click the left mouse button.
  4. Move the mouse roughly along the path of the quadrant and release the button when you reach the other end.
  5. To edit the arc shape enter selection mode and then left click on the arc. Sizing handles will appear allowing you to drag the arc into the desired shape.

To place a path:

  1. Select the Path Icon from the Mode Selector.
  2. Select the graphics style you want from the Object Selector.
  3. Position the mouse over the Editing Window where you wish the first vertex of the path to be and click left.
  4. To enter a straight-line segment, simply move the mouse; to enter a curved segment, press and hold down the CTRL key and then move the mouse.
  5. As the mouse is moved a rubber-banded line is displayed showing the type of segment (straight or curved) that will be created and its position.
  6. Click left to place the second vertex and continue with the third vertex in the same way. During placement, a placed vertex can be deleted or ‘undone’ by using the 'back' button on the keyboard.
  7. Repeat steps five and six until your path is complete or press ESC to cancel the path entry. The path is not completed until you place a final vertex at the same point as the first vertex, so closing the path.

To place graphics text:

  1. Select the Text Icon from the Mode Selector.
  2. Select the graphics style you want from the Object Selector.
  3. Use the Rotation and Mirror icons to orient the text according to how you want it to appear on the drawing.
  4. Point at the position in the Editing Window where you want the bottom-left of the text to appear and click left. The Edit 2D Graphics Text dialogue form is displayed.
  5. Type the text into the dialogue form and set the justification, text size, etc. if required.
  6. Press ENTER or click on the OK button to place the text, press ESC or click on the CANCEL button to abort placing the text.

To place a symbol:

  1. Select the Symbol Icon from the Mode Selector.
  2. Select the graphics style you want from the Object Selector. If the symbol you want is not in the selector, you must first pick from the symbol library. The Symbol Library Pick form can be displayed by clicking on the 'P' toggle on the selector.
  3. Use the Rotation and Mirror icons to orient the symbol according to how you want it to appear on the drawing.
  4. Point at the position in the Editing Window where you want the symbol to appear, and click left to enter placement mode.
  5. Move the mouse to the point where you wish to place the symbol and click left again to commit and exit placement mode.

Resizing 2D Graphics

Lines, boxes, circles, arcs and paths may be resized by first of all selecting them (enter selection mode and then left click on the object) and then by dragging one or more of the displayed ‘handles’ as follows:

  • Lines have two handles which adjust the start and end points.
  • Boxes have eight handles which adjust the corners and edges.
  • Circles have four handles, all of which adjust the radius.
  • Arcs have two handles which adjust the endpoints and the two Bezier control points.
  • Paths have one handle per vertex (the point between two segments) plus two Bezier control points for each curved segment.

Paths support additional editing operations that allow the path to be modified without having to be deleted and re-entered. All these operations require you to hold the ALT (think of ALT=ALTer) key down:

  • Click right on a vertex handle to delete that handle. The segments either side of the handle are also removed and a straight line replaces them.
  • Click left on a line or curve segment to break it in to two straight lines with a common vertex at the point clicked.
  • Hold the CTRL key down and click left on a line or curve segment to break the segment in to two Bezier segments with a shared vertex at the point clicked.

Don’t forget that for all three of the above path editing operations, the ALT key must be held down!

Lines, boxes, circles, arcs can also be given a set size. Place the graphic of any size and right click > Edit Properties. You can then enter the specific dimensions:

This is similar for the the Circle (set the radius), the Line (set the end points) and the Arc (again, set the end points). The X/Y coordinates allow you to set the position of the objects.

The other types of graphic objects cannot be resized - instead you should delete and replace them to effect modifications.

Editing 2D Graphics

All 2D graphics objects can be edited in the usual way by entering selection mode and then left click on the border of the object, followed by a right click to launch that objects context menu. All 2D graphic objects except 2D graphics text have an Edit Graphics Style dialogue box on their context menu that allows you to specify local, fixed, values.

You can also select a 2D graphic (as with any object) by dragging a tagbox around the object with the left mouse button depressed. That is, press and hold the left mouse button while dragging a box around the 2D Graphics object.

See The Header Block for details of how to use 2D graphics text to display design information.


MARKERS

Marker Types

Markers are used in the creation and editing of devices, symbols, terminals and pins. The following fixed set of types is provided:

Marker Type | Purpose
ORIGIN | Defines the anchor point of any part. The anchor point is the point which the object maybe rotated and corresponds to the mouse position at the time of placement.
NODE | Defines the position of the wire connection point for a pin or a terminal
BUSNODE | As above, but defines the pin or terminal as being of bus type. A bus line (thick and blue) will be drawn from the bus note to the origin.
LABEL | Defines the position and orientation of a label for a pin or terminal.
PINNAME | Defines the position and orientation of the pin name for a pin.
PINNUM | Defines the position and orientation of a pin number for a pin.
INCREMENT | Used in creating Active Component simulator models, this marker defines a Hot-Spot for incrementing the state variable
DECREMENT | Used in creating Active Component simulator models, this marker defines a Hot-Spot for decrementing the state variable

Placing Markers

Markers are placed in the same way as graphics symbols (which is really what they are!).

To place a marker:

  1. Select the Marker Icon from the Mode Selector toolbar.
  2. Select the Marker you wish to place from the Object Selector.
  3. Use the Rotation and Mirror icons to orient the marker according to how you want it to appear on the drawing (a preview of the current rotation will appear in the Overview Window). This is only appropriate for LABEL, PINNAME and PINNUM markers - orientation is irrelevant for the other types.
  4. Left click the mouse on the Editing Window to enter placement mode.
  5. Move the mouse to the location on the Editing Window where you want to place the marker.
  6. Left click the mouse to place the marker and exit placement mode.


SIMULATOR GADGETS

The interface to the ProSPICE simulator makes use of certain special objects within ISIS. The complete set consists of:

  • Generators.
  • Voltage Probes.
  • Current Probes.
  • Graphs.
  • Tapes.
  • Active Popups.

Instructions pertaining to the use of these objects are provided in the Proteus VSM Help documentation.


GENERAL POINTS

Library Discipline

The LIBRARY directory as installed with Proteus contains two symbol libraries and over 120 device libraries as well as various essential utility files. The following extensions are used :

  • Library Files (.LIB)
  • Index Files (.IDX)
  • 3D Model Files (.VML or .3DS)
  • Master Style File (.STY)
  • Configuration Files (.INI).

The path to the LIBRARY directory is set by the installer to the users ProgramData branch. You can change or add another library path from inside the Proteus application (System Menu - System Settings command).

System Settings Dialog Form.

We would recommend that you not move your LIBRARY directory (or add another one) unless you need to and that before making any changes you read the following potential issues and requirements carefully :

  • Three libraries, namely USERDVC.LIB, USERPKG.LIB and USERSYM.LIB are installed read/write and intended for users to create their own components, footprints and symbols. You can create additional libraries if need be through library manager. All other installed libraries are installed as read only and contain Labcenter supplied library parts. If you make Labcenter Libraries writable then you will lose changes to those libraries when you update your software. Labcenter libraries are overwritten by the installer to allow to continue to add support for new parts.
  • If you move your library folder onto a network then it is vital that the directory is fully read/write to all users. If Proteus cannot write the library directory it simply will not work.
  • If you elect to have more than one library folder (e.g. one local and one network) then they must be completely de-duped. Two libraries or files with the same name in different places will at best result in confusion as nobody will know which one was loaded.
  • Under no circumstances should you remove items from SYSTEM.LIB.

The Library Browser

Each part in the device libraries is assigned a Category, a Sub-Category and a textual Description. This information is displayed by the Library Browser and makes it very easy to search the libraries for the parts you require. The library browser can be launched from the Library Menu, via it’s keyboard shortcut (by default this is the ‘P’ button), or via the library browser icon on the toolbar.

The Pick Devices dialogue form. First, launch the dialogue, then type the part and finally either select from local results or click to do a web search.

To search the libraries for a part using keywords

  1. Enter keywords that describe the part into the Keywords field. The search operates by matching the keywords against the parts’ names, descriptions, categories and sub-categories.
  2. If the keyword(s) result in a lot of matches - for example ‘741’ will match many parts in the 74 TTL libraries, you can use the Category and Sub-Category fields to refine the search.
  3. Pick the part(s) you require by double clicking them in the Results list.

If the result you want is not in the installed libraries you can start a web search by clicking on the bar that appears at the bottom of the pick devices form. Users with a valid USC contract have access to over 15 miilion parts and also a free part creation service. More information available here.

To browse the libraries for a part by category and sub-category

  1. Ensure that the Keywords field is empty.
  2. Select the category for the type of part you are looking for. This will cause the Sub-Category and Manufacturer lists to show options appropriate for the chosen category.
  3. Select a sub-category and/or manufacturer to refine the search further.
  4. If you still have a large number of results, you can type in one or more keywords in order to further refine your search. Often this will be a part value or voltage. For example, a search for zener diodes will still produce a lot of result even with a specific category - ‘Diodes’, sub-category - ‘Zener’ and manufacturer. Entering a voltage for the description will quickly refine the search to a small number of components.
  5. Pick the part(s) you require by double clicking them in the Results list.

To browse a specific library (e.g. USERDVC)

  1. Ensure that the Library option is enabled (right click on the results list area and select from the resulting context menu).
  2. Prefix the partname or description with all or part of the library name. For example, typing ‘User res 10k’ in the keywords field would restrict the search to the USERDVC library and return any 10k resistors in this library.
  3. Pick the part(s) you require by double clicking them in the Results list.

To search for a part by stockcode

  1. Ensure that the Stockcode option is enabled (right click on the results list area and select from the resulting context menu).

  2. Prefix the partname or description with all or part of the vendor name. For example, typing ‘digi BNTR’ in the keywords field would filter the search to digikey stockcodes in the libraries and return any partial or exact matches. The pre-supplied libraries contain only digikey stockcodes where appropriate although you may of course add other vendors to your own libraries.

  3. Pick the part(s) you require by double clicking them in the Results list.

The crucial point to understand is that only enabled columns in the results list are searched when you enter keywords. This means that in order to filter results in the keywords search you must first ensure that the relevant fields are enabled. To do this, simply right click in the results area of the dialogue form and select the field(s) from the resulting context menu,

Other points of note regarding the keyword search include:

  • If you enter several keywords, they must all be matched against a part for that part to show in the results. In other words, it is implicitly an AND search.
  • If a keyword is purely numeric, then it will be matched against just the digits contained in any part name. So ‘7400’ will match ‘7400’, ‘74LS00’, ‘74HC00’ and so on.
  • If a keyword can be evaluated as a number, then it will compared numerically against any part values found in the description. So ‘1500’ will match ‘1k5’ and vice versa. This means that you can enter ‘res 2k2’ in order to find 2k2 resistors, or ‘zener 4.7’ to find 4.7V zener diodes. Please note that you should not enter trailing units as in ‘4.7V’ as this will disable the numeric matching function.
  • If a keyword matches a part value exactly, then that part will be automatically highlighted automatically in the results. This facilitates quick picking of parts whose name you already know. Pressing TAB and then ENTER will pick the part into the design and close the form.
  • If a keyword contains wildcard characters ‘*’ or ‘?’, then a wildcard based comparison will be made against the part name.
  • Unless you check the Match Whole Words checkbox, then partial matches are allowed, so ‘RES’ will match ‘RESISTOR’ and so on. This is useful in cases where a keyword gives a lot false positives. For example, a search for ‘or gates’ will turn up a lot of spurious matches because the pattern ‘or’ appears in many phrases such as ‘open collectOR’.

You can resize and position the pick form window and then save its position via the Save Window Position command on Windows ‘system’ menu (click on button on the far left of the window’s title bar).

Libraries from earlier versions of Proteus

Existing user device libraries from versions of Proteus prior to 6.5 will not contain category and sub-category information. Parts from these libraries will appear under the Unspecified category, and the library names will be used for the sub-categories.

Please refer to Library Indexing for details of how to index your own libraries.

Updating the Schematic from the Libraries

If you pick a device or symbol that is already loaded into the schematic, Proteus will update it from the libraries on disk.

Note also:

  • Where devices are concerned, the replacement algorithm will match pin positions or pin names, so connectivity will be maintained even if you move or renumber a devices pins.
  • Where a there are two or more devices or symbols with the same name spread across several libraries, the Pick command will load the newest one. This is particularly helpful if you have changed one of our parts and put in USERDVC.LIB, since your version will be deemed newer than ours.

See the section Basic Schematic Entry in the tutorial for details of how to pick parts using the library pick forms.


SYMBOL LIBRARIES

Introduction

The symbol libraries are used to hold both general graphical symbols for direct placement onto drawings, and also symbols for terminals, module ports and device pins.

The various types of symbol are created with different name prefixes, and thus appear to all intents and purposes to be stored in separate 'compartments' of the symbol library. A set of these objects is defined in SYSTEM.LIB and is pre-loaded into the various object selectors when you start ISIS. Thus, when you select the Terminal icon, and you see the names DEFAULT, INPUT, OUTPUT etc. you are actually accessing symbols called $TERDEFAULT, $TERINPUT, $TEROUTPUT and so on. When you place a terminal on the drawing, a terminal object is created and the appropriate symbol is assigned to it.

The significance of all this comes down to two points:

  • Graphics symbols, terminals, module ports and device pins are all stored in symbol libraries (e.g. SYSTEM.LIB and the user library USERSYM.LIB). There are no special libraries for terminals, ports or pins.
  • The procedures for making the various symbol types are all very similar.

Graphics Symbols

A symbol is a group of 2D graphics objects which are treated as a single object. For instance, using three lines and two arcs you can form an AND gate symbol.

Lines and curves and be joined together and made in to symbols (N.B. These are not component devices)

To make a graphics symbol

  1. Select one of the 2D graphics icons - e.g. Line, Box etc
  2. In the Object Selector select a graphics style appropriate to the type of symbol you are creating. For a symbol that will form the basis of future components, this is generally the COMPONENT style though for some symbols, such as OP AMP, where a small line is needed to link the body of the symbol to the base of a pin this would be drawn in the PIN style.If the outline of the symbol consists of lines and arcs and you want the symbol to be filled, use the path object to create the outline.
  3. Select and place graphic objects as required to form the symbol.
  4. Any graphic that needs to have a fixed appearance should be edited, the appropriate Follow Global? checkboxes unchecked and the graphics style attribute changed.
  5. If you want to define the origin for the symbol, select the Markers icon, click on the Origin marker in the object selector and place it where you want the origin to be. If you don't place an Origin, ISIS will default the origin to the centre of the symbol.
  6. Tag the objects that will comprise the port by by entering selection mode and dragging a tag-box around them with the left mouse button.
  7. Invoke the Make Symbol command, select a name and library for the new symbol.
  8. Click OK to complete the operation.

A symbol can only consist of 2D graphics objects - you cannot tag a whole section of circuitry including components, wires etc. and make that into a symbol. To manipulate circuit sections in this way, you should use the Import Section and Export Section commands.

User Defined Terminals

ISIS permits the definition of user defined symbols for use as logical or physical terminals. These are made in the same way as ordinary symbols except that you must place a Node marker to specify the position of the terminal's connection point, and a Label marker to specify the position and orientation of its net label.

To make a user defined terminal

  • Select an appropriate 2D graphics icon - typically the Line icon - from the Mode Selector toolbar
  • In the Object Selector select an appropriate graphics style. This will nearly always be the TERMINAL style though the BUS WIRE style may also be appropriate for small parts of the symbol.
  • Select and place graphics objects as required to form the body of the terminal. Any graphic that needs to have a fixed appearance should be edited, the appropriate Follow Global? checkboxes unchecked and the graphics style attribute changed.
  • Select the Markers icon. Place a Node or Busnode marker where you want the wire or bus to connect the terminal, and a Label marker where you want its net label to be. You can also place an Origin marker to define where its origin will be.
  • Tag the objects that will comprise the port by by entering selection mode and dragging a tag-box around them with the left mouse button.
  • Invoke the Make Symbol command, set the type to Terminal and then select a name and library for the new terminal.
  • Click OK to complete the operation.

Note that the electrical type of user defined terminals will always default to passive. If you need user defined terminals to carry different electrical types you must assign them after placement with the Property Assignment Tool.

User Defined Module Ports

Module ports are the connectors used to attach wires to sub-circuits and it is possible to create user defined symbols for them. These are made in the same way as ordinary symbols except that you must place a Node marker to specify the position of the port's connection point, and a Label marker to specify the position and orientation of its label.

To make a user defined module port

  1. Select an appropriate 2D graphics icon - typically the Line icon - from the Mode Selector toolbar.
  2. In the Object Selector select an appropriate graphics style. This will nearly always be the PORT style though the BUS WIRE style may also be appropriate for small parts of the symbol.
  3. Select and place graphics objects as required to form the pin symbol. Any graphic that needs to have a fixed appearance should be edited, the appropriate Follow Global? checkboxes unchecked and the graphics style attribute changed. In drawing the port, you should orient it in a manner suitable to be placed on the left hand edge of a sub-circuit - ISIS will mirror it in X when it is placed on the right hand edge.
  4. Select the Markers icon. Place a Node or Busnode marker where you want the wire or bus to connect the port, and a Label marker where you want its net label to be. You should also place an Origin marker to correspond with where the edge of the sub-circuit will be.
  5. Tag the objects that will comprise the port by by entering selection mode and dragging a tag-box around them with the left mouse button.
  6. Invoke the Make Symbol command, set the type to Module Port and then select a name and library for the new terminal.
  7. Click OK to complete the operation

User Defined Device Pins

Device pins are, in fact, drawn as symbols and consequently you can define your own symbols for them. A variety of device pin symbols are supplied in SYSTEM.LIB. Nevertheless, there may be some situations in which it is appropriate to define your own.

To make a user defined device pin

  1. Select an appropriate 2D graphics icon - typically the Line icon - from the Mode Selector toolbar.
  2. In the Object Selector select a graphics style. This will nearly always be the PIN style for a standard pin or the BUS WIRE style for a bus pin.
  3. Select and place graphics objects as required to form the body of the terminal. Any graphic that needs to have a fixed appearance should be edited, the appropriate Follow Global? checkboxes unchecked and the graphics style attribute changed.
  4. Select the Markers icon. Place a Node or Busnode marker where you want the wire or bus to connect to the pin, a Pinname marker where you want the pin name to be, and a Pinnum marker where you want the pin number to be. You can also place an Origin marker to define where its origin will be.
  5. Tag the objects that will comprise the port by by entering selection mode and dragging a tag-box around them with the left mouse button.
  6. Invoke the Make Symbol command, set the type to Device Pin and then select a name and library for the new pin.
  7. Click OK to complete the operation.

Editing an Existing Symbol

Any type of symbol may be edited by placing an instance of it and then using the Decompose command.

To edit a symbol:

  1. Place an instance of the symbol. This will be a Graphics Symbol, Terminal, Module Port or Device Pin, as appropriate.
  2. Tag the objects that will comprise the port by by entering selection mode and dragging a tag-box around them with the left mouse button.
  3. Select the Decompose command. This will break the symbol into graphics and markers.
  4. Add, delete or edit the graphics and markers as required.
  5. Reconstitute the symbol according to the procedure from the previous sections appropriate to its type.

Hierarchical Symbol Definitions

ISIS quite happily allows a symbol to contain other symbols and/or other graphic objects. This allows you to make, for instance, a NAND gate out of the previously defined AND gate plus a circle. Note that symbols defined from other symbols are not "linked" to them in any way - if the lower level symbols are changed or even deleted, this will not affect the new one. This also means that a symbol can be defined as a modification of itself without difficulty, although this will destroy the old version.


DEVICE LIBRARIES

Introduction

A device (in Proteus terminology) is a type of real world component such as an NPN transistor or a PIC microprocessor. It follows that a component placed on the drawing is an instance of a device. There are essentially three types of device:

  • Single element devices. These are parts for which there is a one to one correspondence between the schematic symbol and the PCB package. Each pin has a single name and a single pin number.
  • Homogenous multi-element devices. These are parts for which there are several identical elements in the one PCB package. Typical examples would be a 7400 quad NAND gate or a TL072 dual op-amp. The same pin will have a different pin number for each element, except for the power pins which tend to be common.
  • Heterogeneous multi-element devices. These are parts where there are several different elements in the one PCB package, but where you wish to draw each element as separate component on the schematic. The most common example by far is a relay, in which you wish to have the coil and one or more sets of contacts on different parts of the schematic.

Proteus also provides support for bus pins. Devices such as microprocessors and their associated peripherals can thus be drawn in very compact forms since their data and address buses may be represented by single pins. Wiring them up becomes a lot less tedious, too. Devices with one or more bus pins also require a pinout to specify the pin numbers for each physical pin of the bus.

Whereas a single element device will have just one physical pin number associated with each schematic pin, multi-element parts and parts with bus pins all have multiple pin numbers for each device pin. This aspect of the device creation process is handled by the Visual Packaging Tool. In addition, this tool will allow you to create alternate packagings (each with its own set of pin numbers) for the same schematic part. A typical application of this would a microprocessor chip such as the PIC16F877 which is available in both DIL40 and PLCC44.

Important Note

While the following topics are a detailed explanation of how to create component parts in Proteus, in practise this should almost never be necessary. In addition to the many installed libraries Proteus includes free access to over 15 million component parts and footprints via two other means:

1) Integrated web search and import. This works directly from the library picker dialogue on the schematic and requires a valid maintenance contract.

Integrated Web Search.

2) The universal part import dialogue. This provides support for almost all third party part vendors (Ultra-Librarian, Samacsys, SnapEDA, etc.). If the part doesn't exist in Proteus itself the next step is to search for and then import it directly from a third party vendor.

Universal Part Import Dialogue

Tutorial movies on both techniques can be found on our Youtube Channel.

Making a Device Element

Most of the devices you will encounter will involve only a single element. That is to say that by placing one component object, you account for all the pins in the physical part. This is in contrast to a multi-element part like a 7400 for which you need to place four gates to account for all the pins. Either way, the first stage in making a new library part is to place the graphics and pins for the device element or elements.

To make a device element:

  1. Place graphics objects to define the device body in the appropriate graphics style(s).
  2. Place device pin objects to represent the pins.
  3. Annotate the pins to assign name and types using any of the standard editing techniques (see Editing an Object) or the Property Assignment Tool.
  4. Tag all the objects that comprise the element. Then invoke the Make Device command and assign any default properties.

These stages are worthy of further discussion:

Defining the Device Body

The device body is essentially the complete graphic for the device, excluding its reference designator and pins. Very often, it will just be a box, in which case you should simply select and place a graphics box of the appropriate size in the COMPONENT graphics style as shown below.

Select the Component Graphics Style in ISIS

For components with more complex graphics such as transistors, op-amps and so forth you can use any of the graphic objects that ISIS provides in whatever graphics styles are appropriate and perhaps editing the objects and assigning local, fixed values to some or all of the graphics style attributes.

It is important to think carefully about what graphics styles you choose for the graphics in the new component. In general most graphics will be placed with the COMPONENT style selected and the graphic objects will not need editing as they default to fully following this parent COMPONENT style. Occasionally, however, you will want part of the graphics of the new device to be ‘fixed’. For example, you may want the solid body of a transistor to always be filled, perhaps to black. In these cases it is appropriate to edit the graphic object after placement and uncheck some or all of the graphics style attributes and to set local values though where possible you should endeavor to leave as many attributes as possible following the parent, COMPONENT, style. Your other consideration should be how the graphic object placed will fit in to a schematic. For example, if you are designing an OPAMP you may wish to use short lines between the slope of the body and the base of power, compensation or some such pins in which case it is best if these lines are placed in the PIN style so that they look like part of the pin.

If you wish to define the origin for the device, you should also place an Origin marker at the appropriate point. If you don't specify an origin, ISIS will default it to the top leftmost pin end

See 2D Graphics for more information about placing and editing graphics objects.

See Editing Local Styles for more information on customizing individual graphic objects

See Editing Global Styles for more information on defining a global or ‘house’ style for a type of object.

Placing the Pins

When making a device, you use the special device pin objects, available with the Device Pin icon selected to place each pin in turn. Several types of device pin are pre-loaded into the Object Selector when you first select the Device Pin icon, and further types can be picked from the symbol libraries as required. You may also define pin types of your own.

As you place each pin object, you need to be sure that it is oriented correctly. The blue cross that appears at one end of each pin object designates the connection point for the pin; the other should generally be in contact with some part of the device body.

A correctly orientated device pin being placed on a component outline

For further information about pin objects see Pin Objects.

Annotating the Pins

This third phase of the device creation process is probably the trickiest, and can lead to some obscure problems much later on in the design cycle if not carried out correctly. It is therefore extremely important to get right!

Each pin can carry a pin name, pin number and electrical type. The latter is used for electrical rules checking, and also by the ProSPICE simulator. The electrical type of pins must be correctly specified for digital simulator models in particular.

You have two basic approaches available to you in annotating the pins:

  • Edit each pin in turn (point at it and use the keyboard shortcut for ‘Edit Object under mouse’ – CTRL+E by default – will probably be easiest), and proceed to edit its properties using the dialogue form.

The Edit Pin dialogue form being annotated

  • Use the Property Assignment Tool to assign to the PINNAME, PINNUM and TYPE properties of the pins.

The PAT dialogue form being primed to assign Electrical Type as Bi-directional

In most cases, you will find it appropriate to use a mix of these techniques. In general, it is easier to assign pin numbers using the Visual Packaging Tool, and this is the only way to assign pin numbers for a multi-element part or a part with bus pins. However, for a simple single element device, you can enter pin numbers at this stage, if you wish.

In assigning pin names and numbers, bear in mind the following:

  • A pin must always have a name. If you type in a number when there is no name, the pin name will automatically be made the same as the pin number
  • To place pins with overbars in their names, , use dollar ('$') characters to mark the start and end of the overbar. For example RD/$WR$ would display with an overbar on the 'WR' letters .

If you give two or more pins the same name, they will be deemed to be electrically interconnected in the netlist and thus on the PCB layout. While extremely useful this can cause serious problems if used improperly.

In assigning pin types, the following table may be helpful:

Pin Type | Type ID | Example Uses
Passive | PS | Passive Device Terminals
Input | IP | Analogue or digital device inputs
Output | OP | Analogue or digital device outputs
BiDir | IO | Microprocessor or RAM data bus pins
Tri-State | TS | ROM output pins
Pull Down | PD | Open Collector/drain outputs
Pull Up | PU | Open emitter/source outputs
Not Connected | NC | An NC pin. Note that you should still connect an NC terminal as discussed here.
Power | PP | Power/Ground supply pins

If you are unclear how to actually perform the required editing operations, the following sections of the manual are also relevant:

See Pin Objects for a full discussion of the Edit Pin dialogue form.

See The Property Assignment Tool for examples of how to use the Property Assignment Tool.

The final stage of creating a single element device is to tag all the objects (graphics and pins) which comprise the device, and then invoke the Make Device command.

The Make Device Command

The Make Device command is a multi-stage dialogue form sometimes referred to as a Wizard in other applications. There are four pages:

  • Device properties - these are things like the name of the device, the prefix to use for new components and also properties associated with component animation as used by Proteus VSM
  • Packaging - this page displays the packagings that have been defined (for an existing component) and provides access to the Visual Packaging Tool.
  • Component Properties - this page provides the means to create and edit property definitions and default property values.
  • Datasheet & Help - this page allows you to assign a datasheet and/or help file to the component.
  • Library selection - the final screen allows you to specify indexing information and choose the library in which the device will be stored.

Detailed context sensitive help is provided for all the fields on these pages. If you are unsure of the purpose of a particular field, click the '?' at the top right of the dialogue form and then click the field itself to see an explanation of its purpose.

Device Properties Page

This page has two major sections:- General Properties and Active Component Properties.

The Device Properties page of the Make Device dialogue form

The General Properties section determines the name of the device, and the reference prefix. This is the letter or letters that appear in front of the part ID for newly placed components. Note that if you make this blank, newly placed components will be un-annotated and that their part value and properties text will also be hidden. This is useful for block diagram type drawings, or for components such as the Virtual Oscilloscope, which are not really part of the design.

The Active Component Properties section is used for creating animated components for use with Proteus VSM. More information on this is provided on a limited basis (and at our discretion) under NDA terms within the Proteus VSM SDK.

Packagings Page

This page displays the set of packagings that have been defined for the device; for a new device the list will be empty.

The Packaging tab of the Make Device form

Pressing the Add/Edit button will launch the Visual Packaging Tool . More information on the tool can be found in the following sections.

Tutorial: Making a New Device

The Visual Packaging Tool Explained .

Note that a different procedure is required to package a heterogeneous multi-element part. In this case, the packaging tool must be invoked for the complete set of elements as placed on the schematic.

Component Properties & Definitions Page

This page is used to define property definitions and default values for the component's properties. The selector on the left shows the properties that have been defined, whilst the Property Definition and Property Defaults sections determine the type, visibility and default value of the property.

The Properties Definitions page of the Make Device dialogue form

See Property Definitions for more information about component properties and property definitions

Data Sheet and Help Page

This page allows you to associate a data sheet (PDF file) and/or a help topic with the device. If a data sheet is defined, a Data button will appear on the Edit Component dialogue form and if a help topic is defined, a Help button will appear. You will see these buttons for many of the components in the supplied libraries.

The Data Sheet and Help page of the Make Device Dialogue form

The Data Sheet and Help page of the Make Device Wizard.

Data sheets can be located in one of two places:

  • In the Data directory of your Proteus installation. You can change the location that Proteus searches for data sheets by clicking the Path Settings button on the Data Sheet Not Found dialogue form that appears when Proteus cannot find a data sheet.
  • On an HTTP or FTP server - either on the Internet or on your company Intranet. You may need to enter a user ID and password for some servers.

The general idea is that there should be a central repository for data sheets, and that Proteus copies them to individual users installations on as-needed basis.

Referencing a help topic is most useful if you are creating complex models for the ProSPICE simulator, and need to create documentation to be associated with the model. This is likely to be of relevance onto to advanced users and model developers.

Library Selection Page

The final page allows you to specify the library indexing data for the new part and also to select into which library the new device will be stored. Only read/write (as opposed to read only) device libraries are displayed.

Committing the device to a user assigned library

The Device Category drop-down menu displays a list of existing categories, whilst the sub-category list contains existing sub-categories for the currently selected category. You can add new categories and sub-categories by clicking the adjacent New buttons. Note that a category or sub-category will disappear automatically from the lists when there are no parts in the libraries that match it.

The Device Notes field allows you to enter more extensive notes that relate to the device These notes can be viewed from the Edit Component dialogue form; a good use is to provide helpful information regarding simulator model parameters or limitations.

Once you click the OK button, the device will be stored to the selected library. Also, if it exists within the design you will be prompted as to whether you wish to update all the components that use it with the new definition.

The Visual Packaging Tool

The visual packaging tool provides a graphical environment in which to assign one or more PCB footprints to a schematic part. For each PCB package, a table mapping pin numbers to pin names is created such that different packagings can have different pin numbers for the same schematic pin.

The packaging tool also facilitates the entry of different pin numbers for each element in a multi-element part, and each bit of a bus pin.

The Visual Packaging Tool

The packaging tool can be invoked in one of two ways:

  • By clicking the Add/Edit button of the Packaging Page in the Make Device dialogue form.
  • By placing the element or elements of the device to be packaged on the schematic, tagged them and selecting the Packaging Tool command from the Library menu or the packaging tool icon.

The second method is the only way to package heterogeneous multi-element parts.

As with the Make Device command, detailed context sensitive help is available on all the fields. To see the help on a particular field, click the '?' at the top right of the form, and then click the field itself.

Packaging Selector

The Packages section of the packaging tool shows a list-selector for the packagings that have been defined so far and buttons for adding, renaming, deleting and ordering them. One package may be selected as the default, and this is the one that will be used for newly placed components.

Assuming that you have ARES installed, the Add button will launch a copy of the package library browser enabling you to choose a footprint for the new packaging.

Browsing and adding a package to the device

Pin Grid

The main business of the packaging tool is carried out using the pin grid. Here you can enter pin numbers for each pin in each element, and also select which pins are common between the elements of a multi-element device.

You can assign pin numbers either directly by typing in the number or by clicking on the associated pad in the package viewer.

Clicking on a Pad in the package viewer will hilight the pad and assign the pin number

The electrical type is displayed for information only, and cannot be changed here - you must define it when placing the individual pins around the device element.

Automatic Pin Mapping

For large BGA's you can automatically apply Altera Quantas or Xilinx Pinout files via the 'Load Pin Information Script' command on the context menu of the pin grid.

For other large pin count devices it may be worth using the Proteus pin information script format which is basically a comma separated list of pin names and pin numbers. For example,

*PINSCRIPT

PKGNAME=DIL08

PIN1,1,

PIN2,2,

PIN3,3,

PIN4,4,

PIN5,5,

PIN6,6,

PIN7,7,

PIN8,8,

*ENDSCRIPT

Please be aware that the script is case sensitive.

See Also:

BSDL Import topic.

Number of Elements

This field determines the number of pin-number columns that appear in the pin grid. For a multi-element heterogeneous part, it should represent the total number of elements.

Package Viewer

The package viewer displays the PCB footprint chosen for the current packaging. As each pin is assigned to the pin grid, it is highlighted such that you can see which pins remain unassigned. Also, if you point at a pin with the mouse, ISIS will display the associated name (if assigned) and the pin number.

If the text cursor is in the pin grid, then clicking on a pin in the package view will enter its number into the pin grid and the pin will highlight to show that it is now assigned.

Hidden Pins

Hidden pins are generally used to specify power supply connections to components in such a way that they do not clutter up the schematic. A hidden pin can be defined in one of three ways:

  • By clearing the Draw Body checkbox in the Edit Pin dialogue form. This must be done when making the device element. Such a pin will appear in the Pin Grid when the packaging tool is first invoked, and will be present in all packagings.
  • By clicking the Add Hidden Pin button. This creates a hidden pin that is specific to a given packaging, and is implicitly common to all its elements.
  • By selecting 'Hide Power Pins' in the BSDL Import dialogue. This will hide power pins with the same name and add them to the packaging tool as hidden pins.

Hidden pins connect by pin name to the net with the same name. For example, hidden pins named VCC will connect to the VCC net.

Common Pins

A common pin is one which has the same pin number on all the elements of a multi-element device. Typically this will apply to power pins and enable/strobe pins that are common to all buffers within a multi-element driver.

If a common pin is not hidden, then any wiring to it on one element will be connected wiring on the other elements.

A common pin is also deemed to be associated with all the elements in a heterogeneous multi-element part, even if it is not present on some of them. This has implications for the gate swap rules within ARES.

Gate Swap

Selecting this checkbox will flag to ARES that the gate elements can be swapped.

Swapable Pins

The swappable pins section allows you to define groups of pins that are electrically interchangeable. For example, the two inputs A and B of a 7400 quad NAND gate are electrically identical can could be swapped on the PCB for convenience of wiring.

You can add a swap-group to the list by highlighting the pins in the pin grid (hold the ctrl key down and click left on the pin names), and then clicking the Add button.

Assigning pins as swapable pins in the Visual Packaging tool

NC (Not Connected) Pins

When packaging a large device, it may be useful to 'prove' that all the pins have been accounted for by verifying that all the pins are highlighted in the Package View. Since some pins may be specified as non-connected, it is useful to be able to record that they have been accounted for. This can be achieved by entering their numbers in the NC Pins field. Use commas to separate the pin numbers.

For added redundancy you can add physical pins to the NC pin list. For example, if you are not using certain pins of an IC in your project you can add the pad that they would connect to the NC pins list. The system will not permit routing to an NC pin in ARES.

Alternatively, If you wish NC pins to be explicitly visible or wired to something on the schematic then you can do so with an NC terminal. This on-schematic method of specifying NC pins is increasingly popular but large devices as, from a QA perspective, design intent is visible on the schematic.

See Also:

Connecting NC Pins to Terminal

Making a Single Element Device

It will almost always be faster to simply import the part directly.

Most of the devices you make will have a one-one correspondence between the schematic symbol and the PCB package. In these cases, the procedure is pretty much the same as that for creating a device element.

To make a single element device

  1. Place graphics objects to define the device body in the appropriate graphics style(s).

  2. Place device pin objects to represent the pins.

  3. Annotate the pins to assign name and types using any of the standard editing techniques for Pin Objects or the Property Assignment Tool.

  4. Tag all the objects that comprise the device. Then invoke the Make Device command.

  5. Enter a name and reference prefix for the device in the Device Properties page, then click Next to move to the Packaging page.
  6. Assuming that the device has a PCB footprint, click the Add/Edit button and use the Visual Packaging Tool to assign a package and pin numbering. When you are done, click Assign Packages to return to the Packaging page.
  7. Click Next to move to the Component Properties page and enter any property definitions and default values for other component properties.
  8. Click Next to move to the Data Sheet page and specify the location of any data sheet or help topic that you wish to associate with the device.
  9. Click Next to move to the Library Selection page and choose the library in which you wish to store the device.
  10. Finally, click OK to complete the process.

If you prefer, you can also assign pin numbers for single element devices at step [3]. In this case, the pin numbers will appear automatically within the Visual Packaging Tool.

Making a Multi-Element Homogenous Device

A multi-element homogenous device is one like a 7400 in which the physical part consists of several identical elements which you wish to place as separate components on the schematic. To handle such a device, ISIS must allow for different sets of pin numbers to be applied to the same element. For a 7400, there are 4 sets of pin numbers - one for each gate - and which set is used for a given gate is determined by the component reference suffix. For example, if you label a 7400 gate as U1:C then ISIS will use the third set of pin numbers: 8, 9 & 10.

The question then arises as to where to store these sets pin numbers, and how best to allow for their entry and editing. This is all handled by the Visual Packaging Tool.

An example of a multi-element homogeneous device in the Visual Packaging Tool

To make a multi-element homogeneous device

  1. Make the device body and place its pins as discussed see Making a Device Element.
  2. Annotate the pins to assign name and types using any of the standard editing techniques for Pin Objects or the Property Assignment Tool.
  3. Draw a tagbox (left depress and drag the mouse to encompass all the elements) to tag all elements that comprise the device. Then invoke the Make Device command.
  4. Enter a name and reference prefix for the device in the Device Properties page, then click Next to move to the Packaging page.
  5. Click the Add/Edit button on the Packaging page to launch the Visual Packaging Tool.
  6. Specify the number of elements in the device and then fill out the pin number fields for each element in turn. Check the common column to indicate pins (such as power pins) that have the same number on all elements.

  7. Proceed as for a single element device from step 7.

Making a Multi-Element Heterogeneous Device

A multi-element heterogeneous device is defined as a part which consists of several different elements, each of which will be placed as a separate component on the drawing. The most common example is probably a relay where you have a coil and one of more sets of contacts. The requirement is to place the coil at one point in the drawing, and the set(s) of contacts elsewhere.

It is important to understand that you need only create an element for each distinct part of the heterogeneous device. In the case of a relay with one coil and two contacts this means that you need to create two elements; one to represent the coil and the other to represent the contacts. You should not create three elements because the two contacts are instances of the same element. See the example below.

As with a multi-element homogenous device, the Visual Packaging Tool is used to deal with the assignment of pin numbers to each element.

Example : Making a multi-element heterogeneous device (Relay with coil and two contacts)

  1. Place graphics objects and device pins to define appearance of the elements. Make sure the elements are sufficiently separated in the Editing Window so that you can tag the objects that comprise each one by themselves. The process for creating a device element is described in detail here.

  2. Annotate the pins to assign pin names and types only
  3. Tag all the objects that comprise the first element. Then invoke the Make Device command from the Library menu. Enter the Device Name with in the form
    NAME:A
    where NAME is whatever you want to call the part as a whole. The suffix :A tells ISIS that this is the first element of a heterogeneous device.

  4. Walk through the wizard in the normal way, noting that we do not attempt to package the part at this point (skip past this page) and storing the element in a library..
  5. Repeat the procedure from step [3] for the other element, naming it as NAME:B

  6. You should now have two parts in the library. Select the Component icon and place one instance of element A (the coil) and two instances of element B (the contact) in a free area of the schematic.

  7. Edit the RL?:A and RL?:B (second element only) to be RL1:A and RL1:B

  8. Edit the second element B and re-annotate to be element C.

  9. Drag a tag box around the placed elements, and then invoke the Packaging Tool from the Library menu. You should see that there are pin number columns for each element, but that pins which are unavailable for a particular element have '---' in the number column.

  10. Create a packaging and enter the pin numbering in the usual way (as picture above).
  11. Click the Assign Packages button to store the packagings into the library parts. Note that the library part that you created for each element of the device will be updated.

Placing Heterogenous parts is different from placing homogeneous parts. Where Homogeneous parts will automatically change to the next U1:X the Heterogenous devices must be placed as there are saved in the libraries. So for example, if you require Element :C then you will need to pick the RELAY:C from the object selector. You will also need to edit the '?' in the reference to be the required number.

Making a Device with Bus Pins

The ISIS device library system has the capability to support devices in which a single pin on the drawn component represents several pins on the physical part. Such a pin is called a bus pin and is intended to facilitate the efficient representation of microprocessors and their support chips. As with multi-element devices, the process of entering pin numbers for each bit of the bus is achieved with the Visual Packaging Tool.

To make a device with bus pins

  1. Make the device body and place its pins in the same way as for a single element device. You must use the Bus pin, or a user defined pin with a Busnode marker, for the bus pins.

  2. Tag all the objects that comprise the device, invoke the Make Device command.
  3. Enter a name and reference prefix for the device in the Device Properties page, then click Next to move to the Packaging page.
  4. Assuming that the device has a PCB footprint, click the Add/Edit button and use the Visual Packaging Tool to assign a package and pin numbering. You will see that each bit of the bus is given its own row in the Pin Grid. Beyond this, the process for assigning pin numbers is exactly the same as for an ordinary part. When you are done, click Assign Packages to return to the Packaging page

  5. Proceed as from step 7 for making a single element device.

Property Definitions and Default Properties

There are a variety of applications in which it is useful to arrange for library parts to carry default user properties which are automatically assigned to each component as it is placed. Some common examples include:

  • PACKAGE properties for PCB design. Most of the library parts in the supplied libraries carry these properties pre-defined for through hole packaging.
  • PRIMITIVE, MODEL and MODFILE properties for VSM simulation. Again, all our library parts for which there is simulator support carry these default properties.
  • Stock and/or supplier order codes. If you add default properties for these to your libraries, then they can be included in the Bill of Materials report.

To add default properties to a device whilst making it:

  1. Follow the steps in Making a Device Element for making the device.
  2. When you get to the Make Device dialogue form, use the Component Properties page to assign property definitions and default values for the properties..
  3. Store the device to a library in the ordinary way.

To add to or edit the default properties of an existing device:

  1. Pick, place and tag an instance of the device. There is no need to decompose it.
  2. Invoke the Make Device command and click Next to move to the Component Properties page. Any existing property definitions will be displayed.
  3. Edit the properties as required.
  4. Click Next twice more and then store the device back to a library by clicking OK.

Default properties may also be assigned to library parts en masse through the Bill of Materials Property Editor or by applying an ADI script.

Dealing with Power Pins

The handling of power pins tends to be a somewhat confusing subject with different schematic capture packages doing different things. Further difficulty arises from the need to accurately define what happens with the power rails whilst not cluttering up the drawing with what is essentially trivial information.

ISIS provides you with a variety of approaches to handling power pins:

  • Make the power pins visible and physically wire them to the appropriate points in the circuit. This has the advantage that you can see exactly what is connected where, but tends to be very inconvenient where there are lots of ICs on a schematic.
  • Hide the power pins and let ISIS default their connections to like named nets. A hidden VCC pin will thus connect to the VCC net, and a hidden GND pin to the GND net.
  • Hide the power pins and specify explicitly which nets they connect to using like named user properties. For example, the user property
    VCC = +5V
    applied to an object with a hidden VCC pin will cause that pin to be connected to the +5V net.

You can, of course, use a mix of these techniques as appropriate to different parts of a drawing. In general, we have found the use of hidden power pins to be almost essential for digital designs whereas in analogue work, it is often simplest just to wire up the power pins to the appropriate supply rails. This state of affairs is reflected in the construction of the supplied library parts.

To create a hidden pin on a simple, single element device:

  1. Place a pin object for the pin in the usual way.
  2. Bring up the Edit Pin dialogue from by clicking right then left on the pin.
  3. De-select the Draw body checkbox. This hides the pin body, name and number irrespective of the settings of the Draw name and Draw number checkboxes.
  4. If the pin is to be a power pins, set the pin type to Power.

The existence of the pin object will then be marked only by a dark blue cross at its node end, and the pin will not be drawn at all on any device in which it is included. At netlist time, it will be automatically connected to a net with the same name as its pin name, unless explicitly overridden with an appropriately named user property.

To create a hidden power pin within a packaging :

  1. Create the device element(s) in the usual way, but do not place pin objects for the hidden pins.
  2. When creating the packaging(s) inside the visual packaging tool use the Add Pin button to create an extra row within the Pin Grid for the hidden pin.
  3. Type in a name for the hidden pin e.g. VCC, and then assign the pin a number

The Virtual Pin is called named as VCC

As with the other type of hidden pin, at netlist time ISIS will connect all hidden pins specified in the packaging to nets with the same name as the given pin names, unless you override this action with an appropriately named user property.

To override a hidden pin's net:

  1. Tag all the elements of the component for which the hidden pin exists. This is most easily achieved using the Search and Tag command with its Begins With option.
  2. Use the Property Assignment Tool to assign a user property of the form.
    PINNAME=NET
    where PINNAME is the name of the hidden pin, and NET is the name of the net you want it connected to.

Editing an Existing Device

Any device element, whether a self contained, single element device, or a constituent of a multi-element may be broken into its constituent pins and graphics using the Decompose command.

To edit device graphics or pins:

  1. Select component mode and place an instance of the device as a component on the schematic.
  2. Tag the object by pointing at it and clicking left.
  3. Select the Decompose command. This will break the device into 2D graphics, pins and possibly an Origin marker. You will also get a text script which contains the device name, prefix, packaging and any default component properties.
  4. Add, delete or edit the 2D graphics, pins and markers as required.
  5. Reconstitute the device using the Make Device command as previously described. If you tag the text script generated by the Decompose command as well as the graphics before making the device then you can avoid having to re-enter the device properties.

Invoking the Make Device form

If the library part is in use in the current drawing, you will get a prompt requesting whether to perform a Design Global Update. If you select this, then all components on the design that use the device will be updated with the new one using the same mechanism as described for the Pick command. Note that the properties of already placed components will not be modified as ISIS doesn’t know which properties have been manually edited.

Note that the properties of already placed components will not be modified in such circumstances as ISIS doesn’t know which properties have been manually edited.

To edit device properties

  1. Pick, place and tag an instance of the device. There is no need to decompose it.
  2. Invoke the Make Device command and click Next to move to the Component Properties page. Any existing property definitions will be displayed.
  3. Edit the properties as required.
  4. Click Next twice more and then store the device back to a library by clicking OK.

As with device elements, you will be prompted as to whether you want to update components in the current design.

To edit device packagings:

Pick, place and tag an instance of the device. There is no need to decompose it.

Invoke the Packaging Tool command.

Modify the packagings as required.

Click Assign Package(s) to store the changes back into the device library.

As with device elements, you will be prompted as to whether you want to update components in the current design.

Two other points are worth making:

  • Remember that all design files carry with them their own copies of the library parts that they use. Consequently, changing a part in a library will not directly change any designs that make use of it. To effect such a change, you must load the drawing into ISIS and use the Pick command from the Library menu to effect a replace operation.
  • When ISIS is installed, our own libraries are set to be read-only. This is to deter you from changing them - an action which would backfire on you when we issue updates. It follows that if you which to change any of the supplied library parts, you should store them to USERDVC.LIB, or some other library of your own.

Indexing Libraries with ASCII Data Import (ADI)

If you have upgraded to Proteus from a version prior to V6.5, you will likely have existing user device libraries that do not contain indexing data (Category, Sub-Category, Manufacturer and Description). This section explains how you can index such libraries without needing to re-make each part individually.

The easiest and most convenient way to add categories, subcategories, manufacturers and descriptions to existing device libraries is using ASCII Data Import (ADI). ADI allows you to apply textual properties to a schematic or library by listing the information in an ADI file and then load it in to a design or library. The format of the ADI file lets you apply data to parts selectively by allowing you to specify one or more ‘match’ criteria.

Example ADI File

For the purposes of indexing device libraries created with an earlier version of Proteus, an ADI file of the following format is suitable:

; ADI File For My Component Library.

; Last updated 1st January 2004.

BLOCK=INDEX

; Start by removing all data from the part:

IF TRUE

CAT,REMOVE

SUBCAT,REMOVE

MFR,REMOVE

DESC,REMOVE

END

DATA DEVICE : CAT-, SUBCAT-, MFR-, DESC-

74LS00 : "TTL", "Low Power Schottky", "TEXAS", "Quad NAND Gate"

74HC00 : "TTL", "High Speed CMOS", "TEXAS", "Quad NAND Gate"

74F00 : "TTL", "Fast TTL", "Fairchild", "Quad NAND Gate"

7400 : "TTL", "Standard TTL", [SKIP], "Quad NAND Gate"

END

When the ADI file is loaded, it is applied to each part (in the design if brought in to a design, or to the selected items in the source library, if brought in to the Library Manager).

All lines beginning with a semi-colon character are comments and are ignored by the ADI system. All comments must be on separate lines – you cannot have comments with in a ADI statement or at its end.

For the purposes of indexing a design or a library, all ADI files must have the statement

BLOCK=INDEX

at the start to tell the ADI system that the properties being assigned are those used for indexing.

The property names used by ISIS for indexing a part are CAT for the category, SUBCAT for the subcategory, MFR for the manufacturer and DESC for the description.

We then use an ADI IF TRUE…END block with a TRUE test condition so that the statement always executes when applied to any part. The lines within the block (indented for clarity) remove all current assignments to the category (CAT), subcategory (SUBCAT), manufacturer (MFR) and description (DESC) of the part and ensures we start with a clean, un-indexed part.

To assign index data to the part we use an ADI DATA…END block. In this example, the DATA statement has been set to test just the DEVICE property of the part (its name in the library) and, if matched, to assign CAT, SUBCAT, MFR and DESC properties (the minus signs after the names cause the properties to be ‘hidden’ with the script if the part should be decomposed).

The lines within the DATA…END block specify the match criteria and values to be assigned. In our example, we are matching just the DEVICE name but if you want, you can modify the DATA statement to specify additional properties to be matched if you want a more selective test. To the right of the colon are the values to be assigned to the properties specified in the DATA statement, in the order they are specified – i.e. the first item is assigned to CAT, the next to SUBCAT, and so on.

Occasionally, you will find that you want to ‘skip’ assigning a property because either it isn’t pertinent or you don’t have the information. In these cases, use the special statement [SKIP] (the word SKIP inside square braces) to skip assignment. We’ve shown an example in the last line. Here, a 7401 device, would be assigned a category ‘TTL’, a subcategory ‘Standard TTL’ and a description ‘Quad NAND Gate’. The manufacturer would not be specified and, as we force its removal in the IF…END block means this part will not have a manufacturer specified for it.

ADI File for Library where all Parts have same Category

If you are writing an ADI file for applying to a library and all the parts in it require, say, the same category, you can use a simpler ADI file:

; ADI File For My Component Library.

; Last updated 1st January 2004.

BLOCK=INDEX

; Start by removing all data from the part:

IF TRUE

CAT="TTL",HIDE

SUBCAT,REMOVE

MFR="TEXAS",HIDE

DESC="A TTL Part",HIDE

END

DATA DEVICE : SUBCAT-, DESC-

74LS00 : "Low Power Schottky", "Quad NAND Gate"

74HC00 : "High Speed CMOS", "Quad NAND Gate"

74F00 : "Fast TTL", "Quad NAND Gate"

7400 : "Standard TTL", "Quad NAND Gate"

END

In this ADI file, we used the IF…END block to specify the category, manufacturer and a (default) description. As before, with the test condition TRUE the IF statement is always applied to every part so all parts start with their category, manufacturer and description specified. A DATA…END block is then used to assign the subcategory and a proper description. Thus, for example, a library containing, say, a 74HCT00 (which isn’t in the DATA…END block), will still get a category, manufacturer and default description assigned to it by way of the IF…END block.

Using Wild Cards

Finally, note that you can use asterisk and question-mark wild-cards within the matching of a DATA…END block but you need to think carefully about how it works. The following example endeavours to use an asterisk wild-card to match all TTL families:

DATA DEVICE : DESC-

74*121 : "A TTL 74xx121 part"

74*21 : "A TTL 74xx21 part"

END

In this, somewhat contrived, example we’ve deliberately placed the 74xx21 match after the 74xx121 match. As the statements are tested and applied in order the first statement will (correctly) match a 74LS121 but so will (incorrectly) the second statement! This means that the 74LS121 will have the description "A TTL 74xx21" part. For these reasons, it may be preferable to use either one or more question marks or to avoid wild-cards altogether!

To apply the ADI file to a library, use the Library Manager tool. Select the library you want to from the list of Source libraries and then use the Select All button to select all the parts in the library. Finally, use the ADI Library button to browse for and select the ADI file to be applied. After the ADI is complete, you can select any single library part and then use the Information button to see its indexed values.

ADI Library from within the Library Manager.


BSDL IMPORT

Introduction

The boundary scan description language (BSDL) is a description language for electronics testing using JTAG. It has been added to the IEEE Std. 1149.1, and BSDL files are increasingly well supported by JTAG tools for boundary scan applications, and by test case generators.

BSDL is a VHDL subset. Each BSDL file describes one version of an IC and has many package pin maps as are available for a particular die. This is necessary because, for example, two different BGA packages will have different balls; even if the ball has the same name it may be bonded to a different signal on the other package.

From a schematic and PCB perspective there are two main benefits in this file format:

1) The part name, number of pins, electrical type and pin names are all part of the file. This means we can automatically create a basic schematic component for the part.

2) The binding between each pin name on the schematic and the pad name of the footprint is included. This means that we can provide an assisted/automatic packaging for the schematic component.

The mechanism for importing a BSDL file into Proteus is fully explained here

Be aware that while BSDL files are commonly used in ECAD to help create schematic components and bind them to PCB footprints, their original function was for electronics testing. It is possible therefore that component pins not relevant to testing are excluded from the BSDL file, even though they are required for a correct schematic component. Manual inspection of imported parts is therefore critical.


Flat Designs

MULTI-SHEET FLAT DESIGNS

Introduction

With very large designs, or just to create some structure in smaller ones, it is common practice to draw the various sections of the design on separate sheets. Connections between the sheets are then indicated by means of common net names. For example, if two nets on different sheets are both labelled as MREQ, then they are assumed to be connected - see net names for more information on net names.

Design Menu Commands

ISIS supports multi-sheet designs and keeps all the sheets of a design in one file. The following commands on the Design menu give you all the facilities you need:

  • New Sheet - creates a new root sheet and loads it.
  • Previous Sheet – automatically moves you to the previous root sheet in the design.
  • Next Sheet – automatically moves you to the next sheet in the current design.
  • Remove Sheet - removes and deletes the current sheet. You can only delete root sheets, and you cannot delete the last root sheet.

An additional two commands – Goto Previous root or sub-sheet and Goto Next root or subsheet are not exposed on the menu but can be mapped to shortcut keys via the Set Keyboard Mapping command on the System menu (default mappings are PGUP and PGDOWN). These commands work in exactly the same way as the Previous Sheet and Next sheet outlined above except that they will traverse the entire hierarchy of a schematic, moving between both root and subsheets (rather than only rootsheets).

The Design Explorer can also be used to navigate to a particular sheet (or indeed a particular net or component) and provides a user interface for schematic navigation. Alternatively, all the sheets in the design are presented and dynamically updated at the bottom of the Design menu.

The titles presented by the Goto Sheet command are taken from the Sheet Title field of the Edit Sheet Properties dialogue form or machine generated from <module><ordinal> (e.g. ROOT10, ROOT20) where no sheet title is given.

The Edit Sheet Properties Dialogue Form in ISIS

The sheet ordinal determines its position in the design - i.e. the order in which the sheets will print if you print out the lot and which order they appear in the design menu.

The annotator init property is an extremely useful property which lets you set an annotation base for all components on the sheet. It can both be set here and also - under certain circumstances - in the Global Annotator. When working with a large design hierarchy, a little discipline with sheet annotation can add clarity to the design.


HIERARCHICAL DESIGNS

Introduction

A hierarchical design is one which consists of two or more levels of sheets. The highest level is likely to be a block diagram showing the structure of the overall system and each block will have a sub-sheet with a section of the design on it. Depending on the complexity of the design, these sub-sheets may themselves contain further black boxes or modules; ISIS sets no limit on the hierarchy depth although you are doing something very odd if you need more than half a dozen levels.

A second use for hierarchy concerns the replication of a part of a design - a simple example would be a stereo amplifier which has two mono channels and a common power supply. There is nothing to stop you simply drawing one channel, exporting it as a SEC file and then importing it to a second sheet. However, should you then wish to alter the mono circuit - even if it is only a cosmetic change - you are going to have to alter both channels. Where more than two copies of a circuit are involved this can mean serious hassle. With a hierarchical approach you have two modules labelled LEFT and RIGHT but each one is associated with the same circuit data. Naturally you still need different references for the same component in each instance of the mono amplifier and this is catered for by means of Design Global Annotation.

In ISIS, hierarchy also facilitates the creation and use of Parameterized Circuits, and is of considerable use when developing simulator models for VSM. The former subject is covered at length in Parameterized Circuits whilst the latter is dealt with in the VSM manual.

See Also:

Multi-Sheet Designs :Some Practical Examples.

Terminology

Before we delve any further into what is quite an abstract concept, we need to define some terminology...

Circuit

A circuit is a collection of components, other objects and the associated wiring in the general case. For example we can talk about the mono amplifier circuit.

Sheet

A sheet is an instance of a circuit and has a unique set of annotation data that gets mapped onto the components in the circuit. Where a sheet is attached to a module in the next level up - the parent sheet - we can call it a sub-sheet or child sheet. Therefore, we can say that the left and right channels of our amplifier are drawn on the left and right sub-sheets. The sheets at the top level of the design are called the root sheets.

Module

A module is an object which has an associated sub-sheet. There are two types of module: sub-circuits and module-components.

Sheet Property

A sheet property is a property assignment that is attached to a particular sheet, and is available for use in property expressions for any of the objects on the sheet. In hierarchical design, any user properties of the parent module become sheet properties for the child sheet.

Parameterized Circuit

A parameterized circuit is one in which one or more component values or other object properties is given as property expression involving one or more sheet properties. Since these sheet properties can be specified on the parent module (be it a sub-circuit or a module-component), it follows that the circuit itself can have different component or property values from one instance to another. Typical applications for this are filter circuits in which some resistor and capacitor values are different for each instance.

Sub-Circuits

Editing a sub-circuit in the usual way allows you to enter a reference, circuit name and possibly some user properties which become sheet properties on the child sheet. The reference would be LEFT or RIGHT in our amplifier example and the circuit name could be AMP.

Connections between the parent sheet and the sub-sheet are made by means of like named module ports on the left and right edges of the sub-circuit, and terminals on the child sheet.

Sub-circuits are most useful in cases where the exact interface between parent and child sheets is not clear at the outset - you can easily add and remove ports and terminals.

To set up a hierarchy with a sub-circuit:

  1. Select the Sub-Circuit icon left click the left mouse button and then drag out a box for the sub-circuit body, clicking the left mouse button again to place

  2. From the Object Selector, select and place the appropriate types of module port on the left and right edges of the sub-circuit body. You will need one port for each interconnection between the parent and child sheets. By convention, one generally puts inputs on the left and outputs on the right.

  3. Either directly, or using the Property Assignment Tool, assign names to the module ports. These names must correspond with the Logical Terminals that you will place on the child sheet.
  4. Edit the sub-circuit itself and give it an instance name (e.g. LEFT) and a circuit name (e.g. AMP). Several sub-circuits may share the same circuit name, but on a given sheet, each should have a unique instance name.

  5. Either launch the design explorer or point at the sub-circuit and key the shortcut for ‘Zoom to Child’ (see Keyboard Mapping for details). This will cause ISIS to load the child sheet. Unless you have specified the name of a circuit that already exists, you should now see a blank drawing.
  6. Select the Terminal icon and place terminals to correspond with the module ports on the sub-circuit.

  7. Again, either directly or with the Property Assignment Tool, annotate them to have corresponding name which correspond with the module ports. A netlist compiler warning is generate for any module port which is not matched by a terminal.
  8. Draw the circuitry for the child sheet, connecting it where appropriate to the terminals.

Circuitry inside the sub-circuit will 'connect' to the parent sheet through the sub-circuit ports. The convention is that a terminal inside a sub-circuit with the same name as a module port pin on the sub-circuit connects to it. We advise therefore giving some thought to naming.

Module Components

Any ordinary component can be made into a module by setting the Attach Hierarchy Module checkbox on the Edit Component dialogue form. The component's value is taken to be the name for the associated circuit, and the component's reference serves as the instance name.

Tick the box encircled to attached a Hierarchical Module

Connection between parent and child is achieved by having terminals on the child that correspond with the pin names of the parent module-component. This works for hidden power pins too, although this is irrelevant if the Global Power Nets option on the Edit Design Properties command is selected.

Module-components are most suited to handling components which need to be expanded in some way for simulation, but kept as a component for PCB design. The Depth control on the Netlist Generator command form (Depth) provides the means to select what will happen.

To set up a hierarchy within a module component

  1. Select and place the component itself in the ordinary way.
  2. Bring up the component's Edit Component Dialogue form (left click twice on the component or right click and select edit properties from the resulting context menu) and set the Attach Hierarchy Module checkbox. Also ensure that the component's reference and value are suitable as an instance name and a circuit name respectively. In general, the module component will be an IC of some sort, and so its value will make sense as the name of an attached circuit.
  3. Point at the sub-circuit and either launch the design explorer to navigate to the subsheet or key the shortcut for ‘Zoom to Child’ (see Keyboard Mapping for details). This will cause ISIS to load the child sheet. Unless you have specified the name of a circuit that already exists, you should now see a blank drawing.
  4. Select the Terminal icon and place terminals to correspond with the pins of the parent component.
  5. Either directly or with the Property Assignment Tool, annotate the terminals to have corresponding name which correspond with the component's pins. If you are working directly from the Edit Terminal Dialogue form, the names of existing pins are shown in a a drop down combo box for convenience. If you are using the PAT and the pin name is unknown and not drawn on the screen, the name of pin may be established by pointing at its end and applying the keyboard shortcut for ‘Edit Component Under Mouse’ (by default this is CTRL+'E') A netlist compiler warning is generated for any pin which is not matched by a terminal.

  6. Draw the circuitry for the child sheet, connecting it where appropriate to the terminals.

External Modules

Having created a module-component and its child sheet, it is possible to store the child circuit externally to the design such that it can be re-used in other designs. Furthermore, you can modify the library part for the parent component such that newly placed instances automatically bind to the child module.

To set up an external module and an associated library part:

  1. Set up a hierarchy with a module component as described in the previous section.
  2. Zoom to the child sheet, invoke the Edit Sheet Properties command, and click the External .MOD File checkbox. This will create a MOD file with the same name as the library part associated with the parent component.
    In the first instance, this file will be created in the same directory as the design file.
  3. Return to the parent sheet, tag the parent component and invoke the Make Device command.
  4. Enter the name of the module file in the External Module field.
  5. Click Next until you come to the Library Selector page, then click Ok to store the device back into its library.

Newly placed instances of the device will then attach automatically to the MOD file.

Moving About a Hierarchical Design

There are several ways to move about the hierarchy:

  • Use the Design Explorer. This provides a 'windows explorer style' user interface to the schematic and allows you to navigate through sheets as well as to both components and nets.
  • Using the Goto Sheet Command on the Design Menu.
  • The Previous Sheet, Next Sheet and Exit to Parent commands allow you to move through the sheet hierarchy. Additionally, you can right click on a parent sheet and select the 'Goto Child Sheet' command from the resulting context menu as shown below.

Goto Child Sheet on the context menu

If you zoom into a module which has not yet been given a circuit name, a new internal one will be chosen automatically. You can edit the circuit name later, but this will detach the old circuit from the module rather than re-naming the circuit. Any circuits that have been orphaned in this way remain in the design file, but can be removed using the Tidy command on the Edit menu.

Design Global Annotation

Where several sub-circuit objects share one circuit name, you will find that editing done through one of them is reflected in them all. It follows from this that you need only draw out each circuit type once. However, each instance has its own set of component references for the objects in the circuit. This is, of course, essential for PCB design where each instance will require separate physical components to make it. The automatic annotator handles this Design Global Annotation seamlessly, and you need only be aware that changing a component reference on one sub-sheet does not affect the references on other instances of the circuit. It is possible to disable this feature for specialist applications - see Non Physical Sheets below

Non-Physical Sheets

In some applications where there are multiple instances of a circuit it is preferable for all instances to carry the same annotation. If a flat netlist is produced the equivalent parts in each instance must be distinguished and this is achieved by means of Non Physical Sheets. In our amplifier example, the first IC in each channel would LEFT_U1 and RIGHT_U1 - these names being produced by concatenating the Sheet Name (not the sheet title) of the parent module, an underscore and the part reference.

A Non Physical Sheet is selected via the Edit Sheet Properties command, having first loaded the relevant sheet. Set the Non-Physical Sheet checkbox if you wish the naming of components to be local on a particular sheet.

Tick the Non-physical Sheet box

This functionality is unlikely to be useful where a PCB design is the end result but in can be useful in simulation work, or where a module represents a daughter card.

Net names on sub-sheets are always prefixed in this way, unless they are power nets and the Global Power Nets option of the Edit Design Properties command is selected. The result of this is that net names on sub-sheets are 'local'; this is more or less essential where several instances of the same circuit are used.


Multi-Sheet Designs : Examples

EXAMPLES

Overview

The following examples illustrate the various ways in which you can use sub-circuits and multi-sheet designs to split your project into logical blocks. There are also examples of how to re-use these blocks in the same design and also across different Proteus projects.

Example: Simple Sub-Circuits

An example of a logical block encapsulated in a sub-circuit.

Here we have added a sub-circuit on the parent sheet of the schematic and then added and named the ports on the sub-circuit body. We've connected all the ports to input or output terminals and given everything a sensible name. This is all covered previously in the basics of sub-circuits.

The next step is to right click on the sub-circuit, enter the child sheet and then design a block of circuitry that performs the logical function of the sub-circuit. The key thing to remember is that you 'join up' the signals on the child sheet to the ports on the sub-circuit by naming the terminals with the port names.

Terminal names matching the names on the ports transfer connections up and down the design hierarchy.

Key Concept : Scope

Everything connected inside a sub-circuit is local to that sub-circuit with the exception of nets of type POWER.

A power net is denoted by the use of a terminal of type POWER or GND. Nets with the names VCC and GND are always of type POWER.

Power nets are default design global so that you don't have to wire up and down through lots of sub-circuits.

As an example, the terminals above are all local and are wired up through the sub-circuit ports into the parent sheet. The terminals below are design global (using POWER terminals).

Power terminals default to being design global

If you want to use power terminals but still wire everything up between sub-circuits then you can un-check the Global Power Nets options from the Design Properties on the Design Menu.

Rules of Thumb

If a block of circuitry does a single job, it's best in a sub-circuit.

Decide early how you want to handle power nets for your project. You can either have them all global to the design or you can have them local to a sheet. If you want global power nets (convenience) then use power terminals. If you want them local (explicit wiring) then either use default terminal types or un-check the global power nets option.

To connect from the sub-circuit to the parent sheet wire to a terminal and give the terminal the same name as the port on the parent sheet.

Example: Single Sheet Annotation

One of the nicer properties of a sheet is that it can contain an annotation base. This allows you to separate the annotation of parts contained in one sheet from that on a second sheet. The process is simple.

Place the sub-circuit, attach and name the ports in the usual way.

Enter the sub-circuit and then visit Design Menu -> Edit Sheet Properties command.

Change the initial annotation for the sub-circuit (e.g to 500)

Place and wire circuitry in the usual way.

Initial annotation set to 500 sets an annotation base for components placed on that sheet.

If you have placed components and then decide that you want a base annotation for the sheet later, simply use the annotator in global mode and set the initial annotation count.

Global Annotator set to Current sheet and Total mode.

Note that sub-circuit annotation will typically not survive re-annotation from the layout. ARES has a command for annotating the board in a physical way (e.g. top left to bottom right) and this will re-annotate the schematic automatically. You can choose to have the logical annotation preserved by selecting the 'Use Sheet Offsets' checkbox in the ARES annotator.

Sheet Offset in the Annotator maintains the schematic annotation at the expense of directional flow on the physical layout

Example: Multi-Sheet Annotation

The Global Annotator is used to batch annotate designs, but it can also be used to annotate only a branch of a design. A branch of the design is considered to be the current sheet downwards in the hierarchy.

Re-annotating in branch mode will:

1) Set the initial count of the current sheet to the annotation specified on the dialogue form.

2) Annotate the current sheet and then propagate downwards though any child sheets.

3) Preserve any initial annotation counts specified in child sheets.

Branch Scope, Total mode will annotate downwards in a hieirarchy.

This mode is ideally suited to re-annotating after a copy and paste of a sub-circuit hierarchy.

Example: Duplicating Circuitry (Project Clips)

Suitable for duplication of sub-circuits containing sub-circuits (multi-level hierarchy). Project clips are single sheet only!

Suitable for re-use between projects.

Simple and easy to use.

Step 1: Create Project Clip

Create the Project Clip and store to disk.

Step 2: Set up Sub-Circuits

Place a sub-circuit, along with it's ports and then name the Sheet and Circuit appropriately.

Select and block copy the sub-circuit as many times as you need and then rename the sheets. Do not rename the circuit as this is the binding.

Step 3 : Import the Project Clip

Enter the first sub-circuit (CHANNEL1 in our example) and import the Project Clip. This will populate and correctly annotate all of the other sub-circuit channels as well.

Step 4: Place the layout clips

On the layout side, you will have five clips in the parts bin, each of which will place as a single entity with the correct annotation.

If you decide to add another channel (e.g. CHANNEL6) once the project clip has been imported you will need to place the sub-circuit and import the project clip into it manually. It's best to set up all the empty sub-circuits with the same name and then import the project clip into one of them.

If you haven't set a sheet annotation offest and then decide you want one later, you can use the annotator in ARES or the annotator in ISIS in branch mode as decribed above.

Example: Duplicating Circuitry (Replicate)

Suitable for duplication of sub-circuits containing sub-circuits (multi-level hierarchy).

Suitable for re-use between projects.

The following process shows how to duplicate circuitry inside a project :

Step 1: Lay out the first schematic sub-circuit.

Place the first sub-circuit and lay out the circuitry.

Edit the circuit name and sheet name to reflect the contents of the sub-circuit

The Circuit inside SUB_NAME1 also contains a sub circuit which in turn contains another circuit:

Step 2 : Copy and Paste

Block copy the sub-circuit on the root sheet (the top level of the hierarchy branch) as many times are required and rename the sheet. Do not rename the circuit as this is the binding.

The two sheets now contain the same circuit. Making a change to one will also make the same change in the other one.

Step 3: Re-Annotate the Copies

Note that at this stage you will have duplicate annotations in the various sheets. You need to run the Annotator in global mode to generate unique annotations for all of the copies. If you prefer, you can work in branch mode inside each circuit with a different annotation count. This will set sheet annotation for you.

OR

See Also

Multi-Sheet Annotation

Step 4: Layout one Circuit

Place and track the first section of circuitry in ARES. It's easiest if you do this in open space for now so that you can easily select it.

Step 5 : Replicate the other Copies

Carefully draw a selection box around the circuitry and invoke the replicate command. If the Bind command is disabled, you have selected parts not contained in the sub-circuit. Select the second sheet to bind to, an X-Y offset for the placement.


NETLIST GENERATION

Introduction

A schematic diagram contains two sorts of information: graphical and electrical. The process of generating a netlist is that of extracting the electrical data and writing it in a form that other CAD programs can use. Sadly there is no single standard for netlist files with most vendors 'doing their own thing'. In such circumstances only an international standards committee or a very large and successful vendor can hope to rectify the position. The former has produced EDIF which is so complex as to be virtually useless, and no single vendor has become large enough to set a de facto standard. Like many others we have decided to use our own format and provide also for conversion to some of the other file formats in common use.

Our format is called SDF standing for Schematic Description Format. SDF is designed to be compact, human readable, and exceptionally easy to process - BASIC will do nicely. SDF is also intended to be an open format - the technical specification will be provided to anyone who asks.

When working entirely within Proteus the user has no real need to know about the netlist format. The ISIS capture package will create and maintain a netlist automatically and the ARES layout software will similarly read, manage and verify the netlist. Knowledge of netlist formats and netlist files are only relevant where you are exporting for reading into a foreign package for PCB Layout.

See Also

ISIS and ARES


NET NAMES

Overview

So what exactly is a netlist? A netlist is a list of nets and a net is a group of pins that are connected together. In ISIS, a pin is defined by the reference of the component to which it belongs, its type (determined when the relevant device was created) and the pin name or number.

A net can also be named and one of the jobs of the netlist compiler is to merge all nets that have been given the same name. Connections between groups of pins can thus be indicated without having to draw wires between them. This facility is useful for avoiding clutter within a sheet and essential for specifying connections between sheets in a multi-sheet design. The following cause a name to be associated with a net:

  • Attaching a wire label to any wire in the net - the net takes a name from the wire label.

  • Connecting to a Logical Terminal - the net takes a name from the Terminal.

If several of the above occur with different names, the net takes on all the names and will be merged with any other nets which have any of the names. The final netlist will choose one name for the net and a precedence scheme based on the types of the various name-donors is used to choose it - specifically in order of decreasing priority the ranking is:

  • Power Supplies (as defined in the power rail configuration)
  • Power Terminals & Hidden Power Pins (see below)
  • Bi-Directional Terminals
  • Output Terminals
  • Input Terminals
  • Generic Terminals
  • Bus Entries & Wire Labels

As a special case, unnamed Power Terminals assume the name VCC and unnamed Ground Terminals assume the name GND.

Net names can contain any alphanumeric characters plus the minus sign ('-') and the underscore ('_'). Spaces can be used in the PROTEUS environment but may cause problems for other software. The exclamation mark ('!') and asterisk ('*') characters have special meanings which are documented later in this section. Net name comparison is case insensitive.


DUPLICATE PIN NAMES

If a device element has more than one pin with the same name, these pins will be considered to be internally interconnected. For example, in a simulation of the circuit below, the light bulb will light, because the two X pins are deemed to be connected.

Connector and Lamp circuit

Typically, this is relevant for devices which have multiple power or ground pins, but it can also be handy when drawing schematics for wiring matrices such as keypad switch or led arrays.


HIDDEN POWER PINS

Introduction

Many of the integrated circuits in the Device Libraries have hidden power pins. When the netlist generator encounters these, it creates a new net and assigns the name of the hidden pin to it. A 7400 gate will thus generate two power nets - VCC carrying pin 14 and GND carrying pin 7. Since all like-named nets are merged, all like-named pins will get connected together.

Connecting to Hidden Power Pins

You can make further connections to these nets by placing name-donor objects (e.g. Logical Terminals) with the same name and then connecting off them. For example, to connect a resistor to VCC, you would place an unnamed Power Terminal (which automatically takes the name VCC) and then wire from that to the appropriate end of the resistor.

Connecting Hidden Pins to Different Nets

In some cases, you may want hidden power pins to connect to different nets from the pin name. This can be achieved by adding appropriately named user properties to the parts which carry the hidden power pin. For example, if attached to a 7400, the property

VCC = VCC1

would force pin 14 to be connected to VCC1. Note that in the case of a multi-element part such as a 7400, you must add the property to all the gates.

You can view and edit the net names assigned to the hidden pins of a component by clicking the Hidden Pins button on the Edit Component dialogue form.

Note that if you place several pins with the same name, and only some of them are hidden, then they will all be connected together, but not net name will be generated. Instead, they will be connected to the wiring attached to the visible pin(s).

Determining what Power Nets have been Created

Where your design contains components which have hidden power pins, it may not be immediately obvious what power nets have been created, and more importantly, whether these nets have been connected to the actual power supply rails within your design.

Fortunately, ISIS will detect any power nets which have not been connected to a power rail and report any such unbound power nets as an error during netlist compilation. You can then use the Power Rail Configuration dialogue form to specify appropriate bindings.

See Power Rail Configuration for more information.


DESIGN WALK

Introduction

It is often useful to follow a net through the various sheets of the schematic. The design walk feature provides a convenient way to do this using net tagging on the schematic sheets as a visual indicator.

The Design Explorer module by contrast provides a full data driven analysis of net contents and can also be viewed per sheet.

Tagging a Net on a Sheet

The design walk is started by specifying the net. This is done on schematic by right clicking on a wire, terminal or pin of that net and selecting the 'Highlight net on sheet' option from the context menu.

Highlight net on a Sheet shows both which sheets contain the net and also the current sheet (with a tick).

All of the sheets on the schematic are listed in order with those not containing the net disabled. The checkbox on the left hand side shows the current sheet. Left clicking on a sheet will tag it and navigate the schematic to that sheet.

3.3V net tagged on a sheet.

You can also tag a net on a sheet from the Design Explorer Module. First make sure you are in Netlist Mode and then right click on a net and select the Show Schematic Net option from the context menu.

Selecting a net on a sheet from inside the DXP module.

Walking the Design

Once you have the net tagged on one sheet you can cycle the sheets with the page up and page down arrow keys. Navigation on a multi-sheet hierarchical design is down then across.

Use the PgUp and PgDn arrow keys to switch through the sheets.

Alternatively, if you want more control just right click on the wire again and select your next destination sheet from the list.

Following a Signal

Let's assume you want to follow a signal on the schematic. In our case, we'll choose an RS232 line. It's very likely that this will be on only one or two of the sheets. The best solution is therefore to use the context menu twice since it shows you on which sheets the signal is present. So:

  1. Right click and tag on current sheet.
  2. View.
  3. Right click and tag on next sheet signal is present.
  4. View.
  5. etc

Use the Sheet states for faster navigation.

Checking Power

The other common use case will be to look at the IC's on the schematic and check that everything is powered. In this case the net will be a power net and is likely to be on most every sheet on the schematic. In this case cycling through the sheets with PGUP/PGDOWN after the initial tag is probably going to be easiest. So:

  1. Right click and tag on current sheet.
  2. View.
  3. PGDN.
  4. View.

  5. PGDN

  6. ...

Needless to say this is only going to work well if you have visible power pins. If you use hidden power pins then they can't be highlighted because they are hidden ! You should use Design Explorer data view in this situation.

Status Bar

The sheet name is shown on the status bar after you switch to it so you have some idea of where you are on the design hierarchy when cycling through sheets.

It will also tell you if there is no net presence on the sheet. Assuming this is intentional (!) you can then just continue Pgup/Pgdown cycling to the next sheet.


Net Name Syntax

SPECIAL NET NAME SYNTAXES

Global Nets

Occasionally, in a hierarchical design, it is useful to be able to make a connection on a child sheet directly to another sheet (root or child) without running up and down the hierarchy. Typically, this requirement arises either when debugging a design with VSM, or else relates to signals such as clocks which are global to the design. Either way, ISIS recognises a leading exclamation mark ('!') in a net name as defining a global net. Hence a terminal labelled as !CLK will be deemed connected to any other terminal labelled !CLK, as well as to any terminals labelled just CLK on the root sheets.

It is not necessary to do this for power nets, unless you have de-selected the Global Power Nets option on the Edit Design Properties dialogue form.

Unnamed power and ground terminals in fact donate the names !VCC and !GND and so are global unless labelled otherwise

Inter-Element Connections for Multi-Element Parts

This feature was introduced specifically to deal with an obscure problem in the creation of VSM models and is unlikely to find general use. However, we document it here for completeness.

Consider a model for a 1458 dual op-amp. Clearly two instances of this model are required and they share the same power connections. However, the 1458 device only has power pins drawn on op-amp A. How then does one specify the power connections for op-amp B?

We solve this by declaring that the terminal net name *V+ on a child sheet specifies an interconnection between the nets on all child sheets attached to the same parent part, and between those nets and any V+ pins on the parent component elements. The trigger for this mechanism is the leading asterisk ('*') character


BUS CONNECTIVITY RULES

The Base Alignment Rule

ISIS supports bus pins and wiring between bus pins. In the main, this operates intuitively, but it is necessary to be aware of the behaviour of ISIS in some of the more subtle cases that can arise with this feature.

Within the netlist compiler, all bus entities (pins, terminals and module ports) are assigned a bus range. This is held internally in terms of a base and width so the bus D[0..7] has a base of 0 and a width of 8.

The fundamental basis for ISIS bus connectivity is that all entities on a bus (except for bus labels around a junction dot) are connected by Base Alignment. This means that, for example, if two bus pins D[0..3] and Q[4..7] are connected by an unlabelled bus wire, then D0 will be connected to Q4, D1 to Q5 and so on.

The base alignment rule applies, even if the bus pins being connected are different segments of the same bus. For example, the diagram below will be interpreted as making a 4 bit bus which connects Q0 to Q4 to D0 to D4 and Q1 to Q5 to D1 to D5 and so on.

4 bit bus with the base alignment rule

If this is not what is required, then you must use bus labels to designate the required connectivity as explained in the next section.

Using Bus Labels to Change the Connectivity Rule

The only exception to the Base Alignment Rule is in the situation where several labelled bus sections are combined at a bus junction dot. In this case, the bus sections are combined on a Like Bit basis.

The following example shows how some bus pins can be cross-connected using bus labels:

Bus ins cross-connected

In this case, Q0 connects to D4, Q1 to D5, Q4 to D0, Q5 to D1 and so on. It is worth emphasising here that the choice of name stem for the bus labels is completely unconnected with the names of the bus pins - you could have used D[0..3] etc. but it would make no difference whatsoever to the connectivity.

It is also worth re-emphasizing that the Base Alignment Rule applies in all cases except bus labels at a junction dot, so that the connection between Q[0..3] and X[4..7] connects Q0 to X4 and so on.

Using Bus Terminals to Interconnect Buses

As with ordinary wires, it is possible to connect sections of bus without actually drawing in bus wiring. This can be achieved using bus labels and/or bus terminals as shown below:

Terminals on busses

If you omit the range specifier of a bus terminal or label, then it will take its range from the bus section to which it connects. The bus range is determined as follows:

  • If there are bus labels present in the section, then these are combined on a like bit basis so that the meeting of X[0..3] and X[4..7] at a dot creates a range at the dot of X[0..7]. X[4..7] meeting X[8..11] would create a combined range of X[4..11].
  • If there are no bus labels in a section, then the base of its range is 0 (since pins are always base aligned) and the width is that of the widest pin. To put this another way, an unlabelled bus section is always deemed to have a base of 0, irrespective of the ranges of the pins that connect to it.

The latter point does carry the potential to trap the unwary. Consider the diagram below:

Joining bus pins together

Since the X terminals all get ranged as X[0..3], the diagram in fact connects all four bus pins together on a 4 bit bus, rather than creating an 8 bit bus between Q and D. The moral of this is to use explicitly ranged bus terminal labels in all but the simplest cases and always if you are in any doubt.

Note that an isolated section of bus wiring in which there are no bus pins, and in which none of the labels or terminals carries a bus range, is not allowed since ISIS cannot then determine the names and number of individual bits to be interconnected. Instead, you should use a scheme such as the one shown below:

Failure to do this will result in a netlist compiler error.

Connections to Individual Bits

In most circuits, even where all the major ICs use bus pins, it becomes necessary to connect to individual bits of a bus. To do this, you need to know about the net names that ISIS generates when it encounters a bus label or terminal. You should by now appreciate that when the netlist compiler encounters an ordinary Logical Terminal, or a Wire Label, the object donates a net name to the partial net. All partial nets which have one or more net names in common are then taken to be connected.

When a bus label or terminal is encountered, it generates a set of net names, which are assigned to the partial nets that constitute each bit of the bus. The bus label D[0..7] thus generates the net names D0, D1 ... D7.

In the circuit, both the NAND gate and the 74154 are connected to Q[0..3] by this mechanism.

Notice that the bus is not tapped

There are several things to note from this example:

  • Connections to the bus bits can be made without actually drawing a wire coming out of the bus. The bus label Q[0..3] gives the bus bits the net names Q0-Q3 and these can then be referred to and connected up in the usual way.
  • The bus label Q[0..3] is mandatory. The bus pin Q[0..3] does not contribute any net names as this could lead to unwanted connectivity if there were several like named pins on the design. This behaviour is also consistent with the behaviour of ordinary, non-bus pins which do not donate net names either.
  • In fact, the junction between a wire and a bus has no significance at all, as far as ISIS is concerned.
  • In the above circuit, you could just label the bus as Q, since the bus pin Q[0..3] will contribute the range information.

Tapping a Large Bus

A not uncommon situation that arises in the use of buses is that of the need to break a large bus into several smaller buses which connect to chips which are perhaps 4 or 8 bits wide.

Here, the 8 bit Q output of the BUSBOX8 is split into two four bit buses which are then fed into the 4_BIT_WOTSIT sub-circuit modules. The Base Alignment Rule applies at the connection of X[4..7] to D[0..3] to give the desired result. The label X[0..7] is actually redundant in this case but it does no harm to be explicit.

This diagram also shows how bus connectivity can be combined with hierarchical design to give a very powerful scheme for representing array like circuitry. The module ports behave in the same way as pins for bus connectivity purposes.

Some Simple Examples

The first example is a simple connection between A and B. This connects A[0] to B[0], A[1] to B[1] etc. The bus does not need a label as it is not tapped

In the next example the bus is not labelled. The bus doesn't get a name automatically (would it be A[0..3] or B[0..3] ?) and so the resistor is not connected to the bus. This is a common mistake when tapping buses - remember that the bus itself must be labelled!

What we want instead is something like the screenshot below. In this case the bus has a label, X[4..7], so A[0] connects to [X4] connects to B[0], A[1] connects to X[5] connects to B[1] etc. The resistor connects to X4 and thus also to A0 and B0.

The example below connects A[0] to B[0] to C[3], A[1] to B[1] to C[4] etc. (remember the Base Alignment Rule). C[7] to C[10] are not connected and again, as nothing is tapped, no bus label is required.

The final example is a little more involved

This connects as follows :

A[0] to B[0] to C[3] to Z10

A[1] to B[1] to C[4] to Z11

A[2] to B[2] to C[5] to Z12

A[3] to B[3] to C[6] to Z13

C[7] to Z14

C[8] to Z15

C[9] to Z16

C[10] to Z17

The resistor R2 is connected to Z10 and therefore to A[0], B[0] and C[3].

The resistor R1 is connected to a terminal labelled Z17 and therefore connects to net Z17 which is C[10] on part U12.

General Comment and Warning

The preceding sections describe the behaviour of bus pins and labels in the contexts that we envisage them being used. Clearly, other (bizarre) possibilities may be drawn and the hope is that the explanations of how bus pins work will enable you to perceive what will happen.

However, if you are in any doubt whatsoever as to what connectivity will result from what you have drawn, we strongly recommend that you check the resulting netlist with the design explorer before simply assuming that what you have drawn will result in the connectivity that you expect.

This said, you will not easily go wrong if you remember the following two points:

  • The Base Alignment Rule always applies, except for the case of labelled bus sections being merged at a bus junction dot.
  • Use un-ranged bus terminal labels only in simple cases; an unlabelled bus terminal or module port will take a base of 0 if there are no other bus labels in the bus section


POWER RAIL CONFIGURATION

Introduction

ISIS provides a special dialogue form for viewing and/or modifying the power supply connectivity within your designs. This allows you to create one or more power supplies and then to specify bindings between power supply nets and the actual power supplies. This is particularly useful for handling designs in which there are ICs with hidden power pins as you can then determine exactly what power nets there are in the design and also specify interconnections between them where appropriate.

Each power supply has associated with it a Voltage which is used during simulation, and a Routing Class which determines the PCB design rules that will be used for all nets bound to the power supply.

Dialogue Form

The Power Rail Configuration dialogue form is divided into two sections. The top section labelled Power Supplies allows you to create, edit and delete named power supplies whilst the bottom section allows you to view and manipulate the power nets that are bound to each power supply. In a correctly configured design, there should be no unconnected power nets.

Context sensitive help is provided for the individual controls on the form.

Power Rail Configuration Dialogue form

Power Rail Bindings and Design Connectivity

Where more than one net is bound to a power supply, these nets will then be treated as interconnected for both simulation and PCB layout. The Power Rail Configuration dialogue form thus provides a means to specify interconnections between power nets that have been created by the hidden power pins of TTL and CMOS logic ICs and NMOS microprocessor parts. In particular, some parts have pins VCC/GND and some have VDD/VSS and it is very common to need an interconnection between VCC/VDD and VSS/GND.

Notes

  • If you name a net with the same name as the power supply it will bind to the power supply. For example, creating a supply called CHASSIS and then naming a net CHASSIS would automatically bind the net to the supply.
  • A power terminal denoting a voltage (+<num> or - <num>) will automatically create a power supply with that voltage. The prefix is required to avoid ambiguity.

Default Power Rail Configuration

To make life really simple for new users, ISIS provides a default power rail configuration. This is specified in the file PWRRAILS.INI as follows:

POWER SUPPLY | VOLTAGE | NET BINDINGS | NET CLASS
VCC/VDD | +5.0 | VCC/VDD | POWER
VEE | -5.0 | VEE | POWER
GND | 0 | GND, VSS | POWER

When you create a new design, these rules will be applied automatically. Note also that the default power supplies and their associated bindings cannot be renamed or deleted unless you uncheck the Use Default Power Rail Connections checkbox on the Power Rail Configuration dialogue form.

Note that the GND power supply can never be renamed or deleted and its voltage is fixed at 0V. You can, however, edit the routing class.

On Schematic Power Rails and Bindings

Power Rails specified on the schematic

You can also specify power supplies and power rail bindings on the schematic. On-schematic power supplies are created by placing power terminals with labels such as +5V or -12V.

Power supplies created in this way cannot be renamed or deleted from the dialogue form and the voltage cannot be changed. You can, however, still edit the routing class. Note also that power terminals of this type create both a power supply and a power net so you will also see a fixed binding between the +5V net and the +5V supply, for example.

On Schematic Power Rail Bindings

You can also specify on schematic net bindings. For example, if you wanted to connect VCC and VDD to +5V on the schematic you would draw wiring that interconnected logical terminals labelled +5V, VCC and VDD. Note that, in this case, any hidden VCC and VDD pins would acquire the +5V supply as well.

Legacy Designs

Designs created with ISIS versions prior to 6.6 will not contain power rail configuration data and will load with the Use Default Power Rail Connections option cleared.

To enable the power rail configuration features for old designs, you should visit the Power Rail Configuration dialogue form and then click the Use Defaults checkbox. At this point, the power rail configuration features will be enabled, and you must then ensure that all power nets are bound to a power supply.


Netlist Generation

GENERATING A NETLIST FILE

Introduction

The Netlist Compiler command first presents the Netlist Compiler dialogue form and then a file selector from which you choose a filename for the netlist. In most cases, the default settings will suffice; they cause a flat, physical netlist to be generated in SDF format for all sheets in the design. The functions of the various controls are as follows:

Format

A variety of netlist formats can be generated - SDF is the Labcenter Native format, the others are used for interfacing to 3rd party software. Some brief notes are provided in Netlist Formats and detailed application notes regarding some packages are available from our technical support department. Since 3rd party software is subject to changes beyond our control, it is preferable to supply up to the minute application notes rather than commit things to the printed manual.

Logical/Physical/Transfer

A logical netlist contains pin names whereas a physical netlist contains pin numbers. A more subtle effect is that in a physical netlist, the elements of multi-element parts such as the 7400 will be grouped (appearing, for example, as U1) whereas in a logical netlist they are kept separate (appearing, for example, as U1:A, U1:B, U1:C, U1:D). A logical netlist will generally be used for simulation whilst a physical netlist is best suited to PCB design.

Transfer mode is used in specialist applications of ISIS only, for which separate documentation is provided.

Scope

The default scope is the whole design. Current scope restricts the netlist generator to just the sheet that is loaded. This is generally used when you wish to extract the netlist from a child sheet - perhaps a daughter card which is to be represented as a layout in ARES, but which is part of a larger design that needs to be simulated whole. It is also possible to create a 'virtual test jig' by having a parent sheet which contains circuitry to simulate the components on the child sheet.

Depth

The default mode is to flatten the design. In this case objects with sub-sheets will be replaced by their implementation. If the netlist is not flattened then this replacement will not occur and objects with sub-sheets will appear as-is in the partslist and netlist.

The most common reason for not flatting a design is if some components have attached child sheets representing their simulator models, but you wish to produce a purely physical netlist for PCB design. Note that if you wish to use this approach, you cannot have a hierarchical design as well - even ISIS does not cater for selective flattening! However, with VSM, this is not an issue since you can easily link external model files to the design proper, using MODFILE properties. See the VSM manual for further details.

Errors

Various kinds of error can occur whilst a netlist is being generated. If any errors do occur, they will be displayed in the pop-up text viewer window.

Common errors include:

  • Having more than one component with the same name - each component on the schematic must have a unique reference designator.
  • Conflicting property assignments on different elements of a multi-element part - for example U1:A specifies a DIL14 package but U1:B specifies an SO14.
  • Failure to connect power nets to a power supply - this usually arises because you have components on the schematic that have hidden power pins, and you have not specified which power supply rail then should connect to. You should use the Power Rail Configuration dialogue form to resolve this error.


NETLIST FORMATS

SDF

Schematic Description Format - the native Labcenter format - used by VSM, ARES and any future Labcenter EDA products. Also very easy to read in and process to other forms. Contains all textual/connectivity information contained in the DSN file.

BOARDMAKER

Netlist format for Tsien Boardmaker II.

The user property PACKAGE is used for the package name if the file is generated from the Netlist Compiler dialogue form. If you want to use a different field, you must invoke the netlist generator from a script file.

Use Physical mode.

EEDESIGNER

EE Designer III netlist format.

Comment on packaging as for Boardmaker.

Use Physical mode.

FUTURENET

Netlist format used by Dash design tools. Also popular for general purpose netlist transfer.

Use Physical mode for Pin List, Logical mode for Net List.

MULTIWIRE

Multiwire netlist format. Also used by EAGLE PCB design.

File format does not contain packaging data.

Use Physical mode.

RACAL

RACAL netlist format. Used by RedBoard, CADSTAR etc.

Comment on packaging as for Boardmaker.

Two files are created with CPT and NET extensions.

Use Physical mode.

SPICE

SPICE netlist format, also ideal for P-Spice.

Ground net will be node 0, unnamed nets start at 1000; numeric net will be fed straight through. The file SPICE.LXB can be re-named to SPICE.LIB to obtain a set of SPICE compatible models.

Use Logical format.

Do not use this format for creating PROSPICE models - use the normal MDF output from the Model Compiler - it is far more flexible.

SPICE-AGE FOR DOS

SPICE-AGE netlist format for Those Engineers analogue simulator (available direct from ourselves).

The file SPICEAGE.LXB can be re-named to SPICEAGE.LIB to obtain a set of SPICE-AGE compatible models.

TANGO

Tango netlist format, also used by Protel and others. A good general purpose format too.

Comments on packaging as for Boardmaker.

Use Physical mode.

VALID

Valid netlist format used for transfer of ISIS designs to VALID Transcribe package.

Use Transfer mode.

VUTRAX

Netlist format for use with VUTRAX PCB design software as used by several design bureaux

Comment on packaging as for Boardmaker.


ASCII Data Import

Introduction

ASCII Data Import is a scriptable language for assigning properties to components. For the most part users will have no need to use this method of property manipulation as the Bill of Materials Property Editor provides a convenient GUI driven front end to the language.

However, there may be times where the full flexibility of writing ADI scripts is preferred and for completeness of documentation the following is a reference guide to the language.

The idea of ADI is that much of the data you would store within components (e.g. costs, stock codes, tolerances) will remain the same for each component type across all your designs. ADI allows you to specify data for different component types in a simple ASCII file and to import it all into a design with just one command.

The ADI source file can be created with any ASCII text editor - for example Ultraedit or Notepad. The file can contain any number of separate commands, each of which starts on a new line with its command keyword and ends on a new line with the keyword END. There are two ADI commands, the IF...END command and the DATA...END command.

The ADI 'interpreter' is run by invoking the ADI command and then selecting an ADI file with the file selector. The commands within the ADI file are then loaded and pre-compiled - any errors will be written to the error log, which is automatically displayed if errors occur. ISIS then applies each command in the ADI file, in order, to each component in the design.

See Also : Using ADI to Index Libraries.

The IF...END Command

The IF...END command allows you to test the existing properties of each component via an expression, and if the expression evaluates TRUE, then the sub-commands within the IF...END block are applied to the component is succession. The syntax is best explained by example:

IF DEVICE="CAP ELEC" AND NOT VALUE=10p

VALUE=1n,HIDEKWD

TOLERANCE,HIDE

STOCKCODE,REMOVE

END

The expression to be applied to the component follows the keyword IF. Expressions consist of one or more terms separated by operators. Each term consists of a property value, optionally followed by an equals sign and a value.

  • A term only evaluates TRUE if the property named exists, and in the case where a value has been specified, the property value matches the value specified character-for-character, case-sensitive.
  • Operators consist of brackets - which may be used to enclose sub-expressions, and the keywords AND, OR and NOT. The operators AND and OR are executed left to right - there is no precedence. The AND operator evaluates TRUE only if the evaluation so far is TRUE and the term or sub-expression following it evaluates TRUE. The OR operator evaluates TRUE if the evaluation so far is TRUE or the term or sub-expression following it evaluates TRUE. The NOT operator is unary and has the affect of negating the result of the evaluation of the term or sub-expression that follows it.
  • A special expression, consisting of the single keyword TRUE allows you to affect all components in the design.

In the example, the expression tests that the component is an instance of the CAP ELEC library device and that it does not have a value of 10p. If this is the case, then the three sub-commands after the IF expression and before the closing END keyword are applied to the component. Note that, because the device beginning tested for contains a space (CAP ELEC), it is enclosed in double quote ('"') characters.

Each sub-command consists of a property name optionally followed by an equals sign and a new value and/or a comma and a command. If a value is specified, the property named is either created with the new value or has its existing value modified. If a command is specified it is executed following any assignment, as follows:

Command | Description
SHOW | Both the property name and its value are made visible.
HIDE | Both the property name and it's value are hidden.
HIDEKWD | The property name is hidden; the visibility of the property value is unchanged.
HIDEVAL | The property value is hidden; the visibility of the property name is unchanged.
REMOVE | The property name and any value is removed from the component.

If no command is specified then the existing visibility of the property name and value is unchanged.

In the example, the property VALUE is assigned the value 1n and the property name is hidden, the value of the property TOLERANCE is left unchanged but the property/value pair is hidden and finally, the property STOCKCODE is removed from the component.

The DATA...END Command

The DATA...END command allows multiple test values to be tested against a fixed list of property names, and given a match, allows a set of separate values to be assigned to a separate set of fixed properties.

Consider the following example of a DATA...END command:

DATA DEVICE + VALUE : COST+, TOLERANCE, STOCKCODE-

RES 1k : 0.01, 1%, 100-1001

RES 1k2 : 0.01, 1%, [REMOVE]

"CAP ELEC" 1n : 0.03, 5%, 200-1001

SWITCH * : 0.25, [SKIP] , 300-1001

END

The DATA keyword is followed by the name or names of the properties to be tested, separated by plus characters. This list is followed by a colon and then a list of the name or names of the properties to be assigned, separated by commas. Each property name may optionally be directly followed by a plus or minus character that reflects whether you want the property named and the value assigned to it to be shown or hidden respectively; no character indicates that existing visibility should be maintained.

In the example, the DEVICE and VALUE properties are tested. Given a match, new values are assigned to the COST, TOLERANCE and STOCKCODE properties; the COST property and its value being made visible and the STOCKCODE property and its value being hidden.

Each line between the DATA keyword line and the END keyword consists of a list of the property values that you want to test for (separated by one or more spaces), a colon, and then the list of property values you want to assign, separated by commas. Each line is executed in turn; the value of each property named in the list to the left of the colon on the DATA line is tested against the corresponding test value on current line. If all property values match, then each property named on the right of the colon on the DATA line is assigned the corresponding assignment value on the current line.

In the example, the first line tests the DEVICE property for the value RES and the VALUE property for the value 1k; if both match then the COST property is assigned a value of 0.01, the TOLERANCE property a value of 1% and the STOCKCODE property a value of 100-1001. Similarly the third line tests the DEVICE property for the value CAP ELEC (because the device name contains a space it must be enclosed it in double quotes) and the VALUE property for the value 1n; if both match then the COST property takes a value of 0.03, the TOLERANCE property a value of 5% and the STOCKCODE property a value of 300-1001.

Note that the CAP ELEC device name is enclosed in double quotes. You must do this for any of the match values to the left of the colon as these are space delimited. If this were not done, ISIS would have complained it was expecting a colon since it would have assumed you wanted to test DEVICE property against the value CAP and VALUE property against the value ELEC; the 1n would then be unexpected. Similarly, the assignment values to the right of the colon are comma delimited, so if you wanted to assign a new value that contains a comma, then you would have to enclose the value in double quotes.

There are two unusual features of the property values that ADI tests for.

  • The values can contain the wild-card characters: '?' and '*'. The question mark indicates that any single character may appear in the property value being tested in same position as the question mark. The asterisk indicates that any number of characters may appear in the property value being tested between the sets of characters to the left and right of the asterisk. In our example above, we test for a DEVICE property with the value SWITCH but choose not to test such a component's VALUE property by specifying a test value of a single asterisk.
  • Numerical values (including values that contain exponent suffixes such as 'k' or 'u'). Such values are converted by ISIS in to a textual representation with six decimal places and an exponent and the textual representations are then compared character by character. In our example, component placed from the library device RES and assigned the values 1k, 1000 and 1.0k would all match the test condition in the first line.

Whilst the list to the right of the colon normally consists of a new value to be assigned to the respective property named on the DATA line, you can instead specify a command, as follows:

Command | Description
[NULL] | Assign the respective property an empty string. Only the property name and the following equals sign will appear in the component's properties text block.
[REMOVE] | Remove the property; the property name and its value are removed from the component's text property block.
[SKIP] | Skip assignment to the respective property. This keyword is required as an empty assignment (nothing between the commas) will cause an error. Any existing property in the component's text property block is left unchanged.

The second line of the example specified that the STOCKCODE property of any component placed from a RES device with a VALUE of 1k2 should be removed. Similarly, line four, specifies that there should be no assignment to the TOLERANCE property of a component placed from a SWITCH device.


ELECTRICAL RULES CHECK

Introduction

ISIS can check for simple errors in a design by examining the various pin types connected to each net. Obvious examples of errors are outputs connected together or several input pins connected together without a driving source. Terminals are also regarded as having an electrical type - an input terminal connected to an input pin provides a driving source for it.

Generating the Report

You can generate the ERC report by invoking the Electrical Rules Check command on the Tools menu. The results are displayed in the Text Viewer from where they can be saved or printed as required.

Do bear in mind that not all entries that appear in the report may actually be mistakes (e.g. some input pins might deliberately be left NC) and that more subtle mistakes such as wrong part values will not be detected. Nevertheless, many silly mistakes can be detected at an early stage.

ERC Error Messages

The first part of the ERC process involves compiling the netlist, and this in itself can result in warning or error messages.

The actual ERC process itself detects two basic categories of error:

  • Nets so wired as to be likely to result in contentions - i.e. two outputs trying to drive in different directions, resulting in a large flow of current.
  • Nets so wired such that there is no driving source. A net containing only INPUT pins will result in an UNDRIVEN error.

The detection of the first type of error is determined by the following table:

 | PS | IP | OP | IO | TS | PU | PD | PP | GT | IT | OT | BT | PR
PS |  |  |  |  |  |  |  |  |  |  |  |  |
IP |  |  |  |  |  |  |  |  |  |  |  |  |
OP |  |  |  |  |  |  |  |  |  |  |  |  |
IO |  |  |  |  |  |  |  |  |  |  |  |  |
TS |  |  |  |  |  |  |  |  |  |  |  |  |
PU |  |  |  |  |  |  |  |  |  |  |  |  |
PD |  |  |  |  |  |  |  |  |  |  |  |  |
PP |  |  |  |  |  |  |  |  |  |  |  |  |
GT |  |  |  |  |  |  |  |  |  |  |  |  |
IT |  |  |  |  |  |  |  |  |  |  |  |  |
OT |  |  |  |  |  |  |  |  |  |  |  |  |
BT |  |  |  |  |  |  |  |  |  |  |  |  |
PR |  |  |  |  |  |  |  |  |  |  |  |  |

No Warning or Error [image] Warning Issued [image] Error Issued

KEY:

PS: Passive Pin

IP: Input Pin

OP: Output Pin

IO: I/O Pin

TS: Tri-State Pin

PU: Pull Up Pin

PD: Pull Down Pin

PP: Power Pin

GT: Generic Terminal

IT: Input Terminal

OT: Output Terminal

BT: Bi-directional Terminal

PT: Passive Terminal

PR: Power Rail Terminal

ok: No warning or error.

wn: Warning issued.

er: Error issued.


COMPONENT PLACEMENT REPORT

Introduction

The component placement report list the grid square on the schematic sheet (e.g. A1, C3) where a component can be found. It is typically used in review sessions with schematic printouts.

Create a component placement report requires two steps, namely:

1) Placement of grid markers on the master sheet border.

2) Generation of the report in Project Notes.

Grid Markers

The good news is that if you are using one of the Labcenter standard templates which come with a border grid (e.g. Landscape A4) then this step is done and there is no action required. If on the other hand you are using your own template you have a little setup work to do. Bear in mind that you only have to do this once because you can in turn save your border as a Template of your own so it's available to you in future designs.

Basic Procedure for creating a smart grid with a sheet border.

Start by creating a border with numbers on one axis and letters on the other on the Master sheet.

Sheet border with numbers (Y-Axis) and Letters (X-Axis) along with separators

Alternatively, just start a design based on one of our templates of the right size and then modify as normal.

Remember that the border should be created on the Master Sheet so that it is visible on all sheets.

Once the border is in place you need to place and orient grid markers along the separators.

To place a grid marker:

1) Select Marker mode and then the GRID marker from the parts bin.

2) Left click on the editing window to start placement.

3) Use the '+ and '-' keyboard buttons on the num keypad to orient the marker such that it aligns with the separator.

4) Move the marker over the separator and left click again to place.

5) Repeat for the other separators.

Placing a grid marker over the separator between two named cells.

If you can't rotate live just place the marker beside where you want it to go then right click on it and select one of the rotation commands to align it. Finally, right click again and select drag to pick it back up again and move it over the separator.

You are aiming to place a grid marker over each separator on the Y-axis. Then you need to rotate the grid marker so that it aligns with the separators on the x-axis and place a grid marker over each separator. You don't need to place grid markers on all four sides. One horizontal size and one vertical side is enough. Proteus will extend these markers internally across the sheet to slice the sheet into sections and will then identify which components are in each section. This data, along with the section names (A4, C2, etc) is what populates the component placement report.

You may want to save this border as a template at this stage so that you can re-use in future designs. You can do so from the Template menu.

Generating the Report

To generate the report simply open the Project Notes module and select the Component Placement Report from the resulting templates.

Component Placement Report selected in Project Notes module.

If you already have a report open in Project Notes you can select New Note from the File menu and then select from the template list. If you want to add the information to a custom report you'll find it available in the Project Data menu for manual insertion.

Adding the data to a custom report.

The table itself is very simple and, for each component in the design, lists the sheet and grid reference where the component can be found. This makes for quick lookup when the schematic is printed out onto sheets of paper.

Note of course that inside the Proteus software you can cross probe using design explorer or use search and tag to quickly zoom in to a part.


VARIANT COMPARISON REPORT

Introduction

When you have multiple variants of a project it's often useful to list the differences between the variant and the base design. The variant comparison report does precisely that and can be launched from the Project Notes module.

If you are starting the Project Notes module you can select it from the list of available templates

Creating a Variant Comparison Report from Project Notes

If you already have a report open in Project Notes you can select New Note from the File menu and then select from the template list. If you want to add the information to a custom report you'll find it available in the Project Data menu for manual insertion.

Adding the Variant Comparison table to a custom report.

Report Data

The table itself is very simple and, for each variant in the design, lists components that are different from the base design. The difference could be a not fitted status or it may be an alternative value part.

Example variant report showing not fitted parts in one design variant.

Reports are time stamped at the top and are static unless manually reloaded via the right click context menu. First, check that the project note is unlocked and then reload the data from the right click context menu on the data table.

Reloading the data in the variant table.


PRINTER OUTPUT

Printer Output

Output through standard Windows device drivers is performed using the Print command on the File menu whilst the device to print to may be selected using the Printer Setup command. Context sensitive help is available on all fields within these dialogue forms.

Specifying a Printer Device

You can specify the printer device in one of two ways :

  • Use the Printer Setup command from the File Menu. All printer settings including the printer device specified will be remembered across ISIS sessions and the printer device selected will be the default for future ISIS sessions.
  • Use the Printer button from the Print command on the File Menu. Under these circumstances no printer settings will be retained. This is useful if you want to print to a different printer for a specific design.

Print Preview

The Print Preview appears on the far right of the Print dialogue form and displays the position and size of the schematic relative to the specified paper size. It will ‘live update’ as you configure the dialogue (scaling,colour,etc..) to your requirements.

The Print Dialogue Form with the preview area on the right hand side

You can adjust the position of the printed schematic area by left depressing the mouse on the print preview and dragging to the desired position. Alternatively, you can choose a preconfigured position by right clicking the mouse on the preview pane and selecting the desired position from the context menu.

The context menu for positioning can be launched by right clicking on the preview area

Print Preview is disabled when ‘All Sheets’ is selected from the ‘What to Print’ section of the dialogue as it is not possible to show a preview of all sheets simultaneously. In this case printer output will be centered on the printable area.

Configuring Margins

When not printing all sheets you can manually configure the position of the output within the printeable area. Right click on the Print Preview and select Position Output Numerically and enter the margins that you want between the edge of the printeable area and the edge of the output area. This is, in effect, an absolute method of positioning the output area within the printable area. In general, however, we would anticipate most users to position the output area via the mouse drag method detailed above.The graphical illustration below depicts the use of margins.

A graphical illustration of Printer Margins

If you turn off the option to Use Printer Margins on the context menu the margins you specify will be from the edge of the paper itself. In most cases this is not recommended as, depending on your printer driver, you are likely to lose part of your schematic if you position it absolutely at the edge of the paper (outside of the printable area).

Scaling

In addition to a number of standard scaling options you can select Fit to Page.

In the case where the output area is larger than the printable area both dimensions are examined and both X and Y dimensions of the output area are shrunk according to the dimension with the largest offset (thus ensuring that the entire output area is within the printable area).

In the case where the output area is smaller than the printable area both the X and Y dimensions of the output area are expanded according to the dimension with the smallest offset (again ensuring that the resulting output area is entirely contained within the printable area). Note that this option is only available if you uncheck the checkbox for Only Shrink to Fit.

Printer Information

The Printer Information option will dump a log of your printer details and capabilities. This is primarily for support purposes. Whilst our experience of printing support issues is that they are almost invariably the result of a defect in the printer driver we can make a better determination of the problem with the information detailed via this command.


Graphics Output

GRAPHICS FILE GENERATION

Introduction

As well as printing directly to Windows print devices, ISIS for Windows can generate output for use by other graphics applications. You have the choice of generating this output as either a Bitmap or a Windows Metafile, and you can transfer the output to the other applications either through the clipboard, or by saving it to a disk file.

Bitmap Generation

The Export Graphics Bitmap command will create a bitmap of the board and place it either on the clipboard or in a disk file. The dialogue form offers several additional options, each of which has an associated help topic.

Metafile Generation

The Windows Metafile format has the advantage of being truly scaleable where a bitmap is not. However, not all Windows applications (e.g. Paintbrush) can read a metafile.

The Export Graphics Metafile command will create a bitmap of the board and place it either on the clipboard or in a disk file.

SVG File Generation

Scalable Vector Graphics (SVG) is an XML-based vector image format for two-dimensional graphics with support for interactivity and animation. The SVG specification is an open standard developed by the World Wide Web Consortium (W3C) since 1999 and is directly supported by all major browsers.

SVG images and their behaviors are defined in XML text files. This means that they can be searched, indexed, scripted, and compressed. As XML files, SVG images can also be created and edited with any text editor.

DXF File Generation

The DXF format can be used to transfer output to DOS based mechanical CAD applications (it is better to use a clipboard metafile to transfer to Windows based CAD programs). The file is generated by a Labcenter output formatter, rather than by Windows, and as such many of the Windows based drawing appearance attributes will be lost.

Our current experience is of considerable incompatibility and disagreement between applications on what constitutes a valid DXF file. To put this another way, given six applications supporting DXF, only about 30% of file exchange pairings seem to work! This not withstanding the fact that our DXF has been tested with the official Autodesk applications (AutoCAD, AutoSketch etc.). For Windows work, the Clipboard provides a much more reliable transfer medium.

EPS File Generation

An EPS file is a form of Postscript file that can be embedded in another document. Although popular in the world of DTP, for Windows based DTP work you are much better off transferring graphics using a clipboard metafile.

EPS file generation shares the same output options as Printer Output

PDF File Generation

ISIS can also export to the universal Adobe PDF format directly (no need to install PDF printer drivers etc.). Option include colour output and current sheet or all sheet export; in the latter case one page is produced per sheet on the schematic.


INTRODUCTION

The ARES high performance PCB design system is an integrated part of the Proteus software suite and works seamlessly with the ISIS schematic capture software. It launches into a separate tab in the Proteus application and can then be separated into a seperate frame for those users who prefer to work with a side-by-side view.

There are two technologies in Proteus that facilitate the integration between ISIS and ARES, one for component/footprint data and the other for connectivity information. These are summarised below:

Common Database

The ISIS and ARES modules share a common database (CDB) which contains information about all the parts and elements in the project. Parts represent the physical components on the PCB whilst elements represent the logical components on the schematic. The CDB also stores the 'binding' between elements and parts. The upshot of all this is that changes to one element (e.g PACKAGE property) of a multi-element part can now be reflected to the other elements automatically whilst changes to the part (in ARES) can be reflected to all the elements. Functions like pinswap, gateswap and back-annotation are much more robust whilst we have also made clearer the effect of changing part IDs (reannotation - all elements get a new part ID) as opposed to element IDs (rebinding - the connectivity is changed) within ISIS.

Live Netlist

Proteus 8 maintains a 'live' netlist enabling changes made on the schematic to be reflected in ARES, Design explorer and the Bill Of Materials in real time. Changes to the PCB are shown in such a way that they can still be rejected before components and tracking are actually removed from the layout. A batch mode (live netlisting off) is also available should you prefer to work that way.

This chapter primarily deals with the relationship and communication between the ISIS Capture module and the ARES Layout module and is therefore likely to be of limited interest to users of only our simulation software.


ROUTING CLASSES

Introduction

In ARES, every net is associated with a routing class which defines track and via styles, net type, routing layers and so forth. Net Classes are also integrated into the design rule system, allowing you to better control clearances on a per class basis. By default, all nets take the SIGNAL net class except.

  • Nets bound to power rails which for which a net class has been specified on the Power Rail Configuration dialogue form.
  • Nets with names such as D[0] which take the BUS net class. It is the presence of the square brackets which is important. This syntax is really provided for use with schematics packages which could not otherwise convey a net property for a bus

One of the most important things you can do to make your PCB layout easier is to create and assign net classes as you design the schematic. This will automate both the trace and via selection when routing and give you full control over board constraints and clearances.

Changing the Net Class Assigned to a Power Rail

The most common reason for assigning a net class other than SIGNAL is because the net is part of the power wiring and will carry heavier currents. With this in mind, ISIS allows you to specify a routing class for each power supply defined in the Power Rail Configuration dialogue form which you can access from the Design menu.

To do this you need to edit the name displayed in the Net Class field of the Power Rail Configuration dialogue form as shown below:

Changing the Routing Class assigned to a Power Rail

Note that the class will be applied to all the nets which are bound to the power supply - VCC and VDD in this case.

For further information about changing the power rail configuration see Power Rail Configuration

Changing the Net Class using a Net Property

You can also override the default class assignment for a given net by attaching a Net Property to one of the wires on the net. This is achieved by placing a wire label and defining a net class as shown below.

Assigning a custom routing class via a wire label

Using a wire label to specify a net class

If the named net class does not exist, ARES will create it and add it to the net class selector in the Design Rule Manager in ARES when the netlist is loaded. Trace and via styles for the net class can be edited via this dialogue form and design rules created to constrain clearances as required.

The net class 'fred' is available for Desgin Rule Config in ARES

Sometimes it is appropriate to specify a net class for all the nets on a given sheet. For example, you might want all the nets on the power supply sheet to be assigned to the POWER net class.

This could be done by placing a script block as follows:

*NETPROP

CLASS=POWER

on the appropriate sheet of the design.

Wire and bus label net properties take precedence over sheet global net properties.


PACKAGING

Introduction

In order that the ARES module knows which library packages must be used for given components, this information must be entered somewhere in the design process. You can do this either when creating new library parts or when editing the schematic or when placing the part on the PCB. The property to use for this purpose is, not improbably, called PACKAGE. Most of the library parts in the supplied libraries have this property embedded.

The advantage of making packaging changes or additions in the schematic is that you can then run Make Device and store them for future projects. A component in ISIS can contain multiple packagings so you don't lose anything by adding a new package, provided you do so via the packaging tool

Default Packaging

Most of the library parts supplied with ISIS have suitable packages for PCB layout associated with them, and these packages can be viewed when you browse the libraries. Note that some parts - e.g. simulator primitive models do not represent real world components and so do not have packages.

ISIS supports multiple packagings for a single schematic symbol, and where appropriate we have utilized this to offer both through hole (PTH) and surface mount (SMT) packagings for the parts in the libraries.

Note, however, that the responsibility lies wholly with yourself to check that the defaults we have used are suitable for your particular application. We cannot and will not accept any liability for losses due to boards being wasted as a result of unsuitable PCB packaging, however this may have arisen. We recommend most strongly that you make a one off prototype before commissioning the manufacture of large numbers of PCBs.

Manual Packaging in Proteus

Manual packagings can be edited or created in a variety of ways. The best and safest way to package a part for a single part is via the Visual Packaging Tool which provides both an intuitive user interface and visual verification that your packaging is correct. Simply highlight the part and invoke the Visual Packaging Tool to edit or add a packaging.

Where many components have the same package - e.g. resistors with 0805, you can use the Design Explorer to quickly change all the package properties.

See Also:

Design Explorer - Changing Packages..

Manual Packaging in ARES

You can also continue through to ARES and board design without a packaging for a part. When you attempt to place the part on the layout ARES will prompt you to choose a footprint for it and - once selected - that footprint will appear in the schematic component as well.

Not Connected Pins (NC Pins)

There are three ways to have Not Connected (NC) Pins:

1) Physical pins that are of electrical type NC. This will ensure that NC pins are not internally connected on the layout but will not prevent a connection to the NC pin being made.

2) Physical pins that you wire to an NC terminal. This will explictly assign the pin to the NC net and any connection on the layout will then be an error.

3) Virtual pins that you assign to be NC in the packaging tool. This will explicitly assign the pin to the NC net and any connection on the layout will then be an error.

We recommend you use NC terminals when you have physical terminals.

To make a pin NC with a terminal :

This is especially useful for large parts, or where the mapping of pins may change during design. In Proteus, you do this as follows:

1) Select terminal mode and the NC terminal type.

2) Place the terminal against the pin ends with the cross facing outwards.

You can rotate the terminal using the + and - keys while placing.

There is no need for wiring - simply place the terminal against the end of the pin to make the connection.

The packaging tool will determine which pads of the footprint that these pins are assigned to in the normal way. Then, in the layout package those pads will automatically be on the NC net and you will be unable to connect a track to them.

As an off-schematic alternative you can also assign NC pins entirely within the packaging tool. This is discussed in the library facilities topic linked below. Your choice of method depends on your QA requirements (if you need to print the schematics and therefore see the NC status this method is better), on how custom this particular design is (if you use this method you need to connect the terminals on each project) and on personal preference.

See Also:

Packaging Tool and NC Pins.

Automatic Packaging

The ASCII Data Import feature can be used for the automatic packaging of component types which always take the same package. As an example of this, the file DEVICE.ADI is supplied with ISIS and shows how packages and other properties were assigned to the parts in DEVICE.LIB.

The file is set up such that packages are loaded into the PACKAGE property which is then hidden. You can change this by editing the ADI block headers - see report generation for more information on ADI.

Some components such as ordinary and electrolytic capacitors come in many different shapes and sizes. Furthermore, we cannot know what particular capacitor families you will want to use. Nevertheless, it is possible to build ADI files that operate on part values as well as device library names. For example, the extract below packages capacitors from our favourite suppliers, and at the same time, loads the order codes for them into property ORDER.

Note that packaging is only done for capacitors which are not of the default size specified in DEVICE.LIB. Running CAPS.ADI would override the default assignments to achieve the desired result.

;CAPACITOR PACKAGING FOR TYPES REQUIRING

;OTHER THAN CAP10 / ELEC-RAD10 PACKAGES

DATA DEVICE + VALUE : PACKAGE-

CAP 1u : CAP20

"CAP ELEC" 470u : ELEC-RAD20

"CAP ELEC" 1000u : ELEC-RAD30

"CAP ELEC" 2200u : ELEC-RAD30

END

;CAPACITOR ORDER CODES

;These are Ceramic, Polyester types and

;Electrolytics at 25V or better.

DATA DEVICE + VALUE : ORDERCODE-

CAP 100p : F146-447

CAP 680p : F146-457

CAP 1n : F149-100

CAP 1n5 : F149-101

CAP 3n3 : F149-103

.

.

.

"CAP ELEC" 47u : R11-0235

"CAP ELEC" 100u : R11-0245

"CAP ELEC" 220u : R11-0260

"CAP ELEC" 470u : R11-0280

END

In general, there will always be a final phase of manual packaging to do for unusual parts, or for special components used in that design only. We suggest that you make the PACKAGE properties of manually packaged parts visible as a reminder that they are non-standard.

Using the Design Explorer to Verify Packaging

In the case of largish designs, it can become difficult to ascertain whether all the components have been packaged, and which packages have been assigned. You can check this quickly by launching the design explorer which - as well as telling you what footprints have been specified. Anything that has NONE assigned in blue means that the part has the check box 'Exclude from PCB Layout' ticked in the Edit Component form. Parts that have MISSING in red means that the part does not have a package assigned to it at all.

You can then right click on the part in the design explorer and cross-probe to navigate to the schematic part and adjust the packaging.

If you have multiple missing packages it is much easier to separate the design explorer into a second frame so you can view side-by-side with the schematic. The design explorer will update live as you edit the schematic and package parts that are missing.

The Package Verifier

Proteus can verify that all the packages specified for components on a schematic exist in the ARES libraries, and that all the pin numbers specified in the ISIS library parts exist in the specified packages.

Whilst this facility is most useful when creating library parts en masse, it is also useful if you wish to verify that all the packaging is correct prior to netlisting to ARES.

Apply the verification pass via the Verify Packaging command.


DESIGN ITERATION

Overview

The term 'Engineering Change' refers to a situation in which an existing schematic is modified, and the resulting netlist re-loaded into ARES. This can occur both during the development of an original design, and also at a later date where a 'Mark II' version of the product is being produced. Proteus fully supports engineering changes, but what happens in a given situation depends largely on whether you are working with live netlisting enabled or with live netlisting disabled (batch mode).

  • When live netlisting is enabled data is received whenever the ARES module is open and visible.
  • When live netlisting is off data is received when you manually click on the padlock icon at the bottom of ARES. The padlock icon will appear when changes to the netlist have occurred (ISIS has changed) but have not been received.

Live netlisting can be turned on and off from the toggle command on the Tools menu in ARES. We would advise that during development users should work with live netlisting switched on. The only time where live netlisting switched off may be of use is on larger layouts with multiple zones where there may be a performance penalty because all of the zone connectivity will be re-calculated on each schematic change. Note however that leaving Live Netlisting On and simply closing the ARES tab or frame is just as optimal - netlist updates do not occur in the background.

Note that live netlisting must be turned on following an import from an older version to perform an initial sync.

See Also:

Importing an Version 7.xx DSN & LYT Project.

Adding New Components

Live Netlisting On

When you place a new component on the schematic it will automatically appear for placement in the parts bin in the layout module.

Wiring up the connections on the schematic will add the connections to the live netlist.

  • If the parts are placed on the layout before the connections are made in ISIS then ratsnest lines will appear in ARES as you complete wires in ISIS.
  • If the ARES footprints are still in the parts bin then ratsnest lines will appear as you place them on the layout.

Live Netlisting Off

When you place a new component on the schematic, ARES will enter a locked state indicated by a padlock on the connectivity status widget.

When you click on the padlock to unlock ARES the updated netlist will be sent and the part will appear in the ARES parts bin for placement.

Wiring up connections in ISIS will similarly lock the layout. You can click the padlock to unlock at any time and the current connectivity situation will be updated on the PCB.

More information on the above procedures with reference to ARES can be found in the ARES help documentation.

Removing Existing Components

Live Netlisting On

When you delete the component from the schematic ARES will automatically enter a changes pending state and the corresponding parts and tracks on the layout will appear dimmed.

When you click on changes pending to accept the changes both the footprint and its tracking will be removed from the layout.

Alternatively, an undo operation will revert both the schematic and the layout to their previous status.

Live Netlisting Off

When you delete the component from the schematic ARES will enter a locked condition.

When you click on the padlock to unlock the current connectivity is sent to ARES. The deleted part and tracking will then appear dimmed and the connectivity status will indicate changes pending.

Clicking on changes pending will commit the deletion and the schematic and layout will be back in sync.

Removing a component or wire is an operation which affects objects that the board designer has already placed on the layout. As such, it requires you to manually confirm by clicking on the changes pending button to sync the layout.

If you find the dimmed state hard to see you can change the colour (e.g. bright yellow) from the View Menu, Layers Command in ARES.

Changing the Connectivity

Live Netlisting On

Adding connectivity is an action which does not affect the existing tracking on the layout. A ratsnest line will appear in ARES as soon as you complete the wire in ISIS and the system will automatically synchronize.

The effect of removing connections in ISIS depends on whether they have been tracked in ARES.

  • If a connection is untracked in ARES (still a ratsnest line) then removing the connection in ISIS will simply remove the ratsnest line and the software will remain in sync.
  • If a connection is tracked in ARES thn removing the connection in ISIS will put ARES into a changes pending state and the corresponding track will appear in a dimmed state. Confirming the deletion by clicking on changes pending will remove the track and the software will return to a synchronized state.

Live Netlisting Off

Any changes to connectivity will render ARES in a locked state. When the editing is complete, clicking on the padlock icon to unlock ARES will update the layout with the new connectivity information.

If the only changes were the addition of new connections then ratsnest lines will appear in ARES.

If connections were removed which involve existing tracking then ARES will enter the changes pending state and the corresponding track(s) will appear in a dimmed state. Confirming the deletion by clicking on changes pending will remove the track and the software will return to a synchronized state.

Re-Annotating Components, and Re-Packaging Gates

Live Netlisting On

Re-annotating components is fully automatic. The layout will update and the system will remain in sync.

Gate-swapping multi-element parts from the schematic is also fully automatic. The layout will update and remain in sync.

Use the Annotator from the Tools Menu in ISIS to automate the task on the Schematic or the Automatic Annotator from the Tools menu in ARES to automate the task according to your needs. Context sensitive help on both dialogues is available via the question mark at the top right of the dialogue form.

Live Netlisting Off

Re-annotating components will lock the layout. Unlocking the layout will auto-sync with the schematic.

Gate-swapping multi-element parts from the schematic will also lock the layout. Unlocking the layout will auto-sync with the schematic.

In either case above, the assumption is that you have only re-annotated or gate-swapped. Clearly, if you re-annotate, delete, add and re-wire then you will enter a changes pending state when you unlock the layout. The re-annotation changes however will be applied - confirming changes pending serves to confirm any removal operations from the layout.


RE-ANNOTATION

In some circumstances you may wish to renumber components on the PCB to suit manufacturing or assembly activities. This can be done either manually or automatically.

Manual Re-annotation

To re-annotate manually

  1. Ensure that ARES is synched with ISIS and then make sure that live netlisting is swiched on.

  2. Choose the Component Mode icon in ARES, and the correct layer for the component(s) you wish to annotate.
  3. Click on the component labels to edit them.
  4. Changes will automatically be reflected on the schematic.

You can re-annotate manually with live netlisting switched off but each annotation will involve a netlist change which in turn will require you to manually unlock the layout. Much easier to perform this type of operation with live netlisting enabled.

Be careful that you do not end up with two components with the same reference (e.g. two R2 components). Proteus will cope with this and will warn you in the pre-production checker but it almost always leads to confusion.

Automatic Re-annotation

Automatic re-annotation will globally re-annotate the PCB and reflect the changes back to the schematic. You can select both a direction and a starting point for the annotator.

To re-annotate automatically

  1. Make sure that ARES is synched with ISIS and then launch the automatic annotator from the tools menu in ARES.

  2. Choose the direction and starting point for the re-annotation and click the OK button to start..
  3. Changes will instantly be reflected on the schematic.

How it Works

The annotator starts by scanning along the direction you specify from your starting point. It takes a 'strip' of footprints from one side of the board to the other and the width of the strip is the 'thickest' footprint outline. This strip is annotated in the direction you specified and another strip is then scanned using the same metric.

What this means is that while generally you will get good results it is quite possible to see what appears to be illogical annotation. An example would be where a big IC footprint is mostly but not completely in the same strip as a row of small resistors. In this case the annotation of the resistor outside of the strip may be markedly different from the other ones.

You can easily resolve this kind of thing by manually re-annotating any oddities.

Caution

The ARES annotator will annotate the physical layout without consideration of the logical schematic. The annotation in the schematic will change automatically to match the new layout annotation but rules for annotation defined in the schematic will be ignored by the ARES annotator unless you check the box to preserve sheet annotation bases on hierarchical designs.

Depending on the user, the logical annotation of sheets may be preferred over the geometric annotation on the board. If this is true for you, it may be easier to sort your annotation using the Global Annotator from the Tools menu in the schematic module.


CROSS PROBING

Introduction

Cross-probing is a powerful technique for analysing and checking both your schematic and your PCB layout simultaneously. Essentially it allows you to take a schematic component and tag/zoom to the PCB footprint on the layout corresponding to that component. The Proteus design suite also enables you to look at a net on the schematic and highlight the same net on the PCB layout, thus allowing you to easily establish and check routing strategies and completeness.

Much of the cross-probing can be actioned directly from the application module you are working in (ISIS or ARES) and/or you can work from within the Design Explorer. Where appropriate, we'll discuss both methods below.

See Also : Design Explorer

Automatic Cross-Probing Mode (Design Explorer)

You can automate navigation to both schematic and layout modules by switching on the live cross-probing mode in the Design Explorer.

When enabled the clicking on an component in Design Explorer automatically tags the component part on the schematic and/or the footprint on the layout.

The difference between automatic mode and those described below is that there is no switch of tabs to the schematic and/or layout in automatic mode. The most useful way to cross-probe in this way is therefore to detach the design explorer from the frame containing the schematic/layout (drag the tab and drop it). With the design explorer is a separate frame you can then click on a component and view the corresponding schematic/layout.

Cross Probing to a Footprint

Direct from ISIS

  1. Locate the component part that you want to cross-probe from.
  2. Right click and select 'Show in PCB Layout' from the resulting context menu.

Proteus will switch to (or launch) the ARES tab and navigate to the footprint corresponding to the component part in ISIS. Of course, if the footprint has not yet been placed on the layout not much will happen!

Design Explorer

To cross probe to a footprint in ARES :

  1. Make sure that both ISIS and ARES are open, have the design/layout file loaded and that they are synchronised (that is, that all changes in ISIS have been netlisted through to ARES).
  2. Launch the Design Explorer in ISIS.

  3. Make sure that you are in Physical Parts View - this is shown on the title bar of the design explorer.

  4. The right hand pane should be displaying a listing of component parts on the current ISIS sheet.

  5. Right click on the schematic part of interest within this pane and you should get a context menu with an option to 'Go to PCB Part'. Select this menu option and ARES will both zoom to and highlight the footprint corresponding to the component you selected.

If the 'Go to PCB Part' option is grayed out then either ARES is not open, doesn't have the layout corresponding to the open schematic loaded, or the schematic and PCB are out of sync (close design explorer, re-netlist to ARES and repeat from step 2 above).

The Design Explorer is a top level window which means that it can be minimised to the system tray. It will automatically detect when the schematic has changed and will close. This is required to ensure that the information displayed in the design explorer is entirely consistent with that on the schematic.

Cross Probing to a Net

To cross probe to a net in ARES :

  1. Repeat steps 1 & 2 in Design Explorer above.
  2. Use the net icon at the top left of the design explorer to switch into Physical Netlist View - this will be reflected on the title bar.

  3. The right hand pane will now be displaying a list of nets used in the schematic.

  4. Right click on the net of interest within this pane and you should get a context menu with an option to 'Go to PCB Net'. Select this menu option and ARES will both zoom to and highlight the footprint corresponding to the component you selected.


PROJECT CLIPS

Overview

Project clips (or snippets) provide a formal way to reuse parts of an existing project in future work. The basic idea is simple; select an area of schematic and/or an area of layout and then export them to disk for import into future projects. There are however some important rules and limitations which are explained below.

Project Clips Practical Examples

Schematic and Layout Project Clip

A schematic and layout project clip is the normal scenario. You have a section of circuitry and a corresponding section of layout that you either want several copies of in a board and/or you want to re-use in future projects.

Creating

To create a schematic and layout project clip

  1. Organise your schematic so that everything you want in the project clip is on a single sheet. Drag a selection box around the circuitry in ISIS.

  2. The layout selection in ARES must precisely match the schematic selection in ISIS. If you are creating the project clip from a completed or existing project this will almost certainly require some surgery so save your project under a temporary name before you begin! Use the selection filter or simply move and delete as appropriate until you can drag a selection box around the parts and tracking that you want. When you are finished drag a selection box around the area of PCB.

  3. Right click inside the selection box and select the Export Project Clip command from the context menu. By default, this will save the project clip (*.PDSCLIP) into the SNIPPETS directory of your Proteus installation.

This is an operation involving a selection box on the schematic and a second selection box on the layout. If your monitor is big enough it's useful to split the layout tab into a separate frame so that you can see both at the same time.

You need to manually arrange the selection box on the layout as, apart from footprints, we cannot make decisions on which objects are included. Your selection box therefore tells us whether enclosed tracking, 2D Graphics, enclosed zones, etc. should form part of the project clip.

Rules for Project Clips

Importing

To import and place a schematic and layout project clip

  1. Start from the schematic module (ISIS) and go to file menu and insert project clip command.

  2. Place the project clip on the schematic.

  3. The corresponding project clip will then appear in the parts bin in ARES, denoted by a scissors icon at the right hand side.

  4. Click on any component part of the project clip and place on the layout.

Schematic Only Project Clips

A schematic only project clip is an area of schematic design that you wish to re-use in future schematics but for which there is no accompanying board layout in place. For example, an Arduino shield may be created for simulation purposes and re-used in several projects.

Creating

To create a schematic only project clip

  1. Organise your schematic so that everything you want in the project clip is on a single sheet. Drag a selection box around the circuitry in ISIS.

  2. Right click inside the selection box and select the Export Project Clip command from the context menu. By default, this will save the project clip (*.PDSCLIP) into the SNIPPETS directory of your Proteus installation.

Importing

To import a schematic only project clip

  1. Start from the schematic module (ISIS) and go to file menu and insert project clip command.

  2. Place the project clip on the schematic.

A schematic only project clip replaces the old Proteus 7.xx Section file technology. You can import existing section files via the Import Project Clip command and change the file type selector to section files. You should then create a project clip from the imported data.

Layout Only Project Clip

A layout only project clip is an area of PCB layout that you wish to re-use in future boards that does not have a direct schematic equivalent. This is both extremely unusual and potentially unsafe (annotation clashes) but is included here for completeness.

Creating

To create a layout only project clip

  1. Organise your layout so that everything you want in the project clip is on a single sheet. Drag a selection box around the circuitry in ARES and use the selection filter to define selected object types.
  2. Right click inside the selection box and select the Export Project Clip command from the context menu. By default, this will save the project clip (*.PDSCLIP) into the SNIPPETS directory of your Proteus installation.

Importing

To import a layout only project clip

  1. Start from the layout module (ARES), go to file menu and insert project clip command.
  2. Place the project clip on the layout.

Importing a PCB only project clip (or indeed copy and pasting parts of a layout) when you have a schematic and live netlisting is on can have unintended consequences. If no duplicates exist, the annotation of the clip is preserved but the footprints will bind to schematic components with that annotation which may well not be what you want to do. If you are unsure then you should first clear the netlist (tools menu in ARES), then import the project clip and fix up the annotation as desired and finally turn live netlisting back on to sync.

A layout only project clip replaces the old Proteus 7.xx Region file technology. You can import existing region files via the Import Project Clip command and change the file type selector to region files. You should then create a project clip from the imported data.

Rules for Project Clips

  • A schematic and layout project clip requires that exactly the same parts are selected in both the schematic and the layout. You cannot have a selection in ARES that contains components with different part references than those selected in ISIS, nor can you have parts highlighted in ISIS which are not highlighted in ARES.
  • A project clip on the schematic will operate only on the current sheet. Do not create a schematic snippet that contains a sub-circuit. Snippets do not propagate down through the schematic hierarchy and the sub-circuit contents will not be saved/imported.
  • A schematic and layout project clip must first be imported into the schematic. This will initialise the parts such that placement on the layout is correct and there are no annotation clashes with other circuitry.
  • If a power plane is not completely enclosed by the selection on the layout it will not be included in the project clip. The assumption is that the clip will be placed on a board where an equivalent plane is in use. If not, then clearly there will be missing connections on import.
  • Once placed on the PCB layout the project clip is no longer a single entity. Each object (component, track, via, etc.) is moved or edited independently.
  • If you import a project clip into a schematic sub-circuit it will replicate across circuits with the same name that are already placed. Subsequently adding a sub-circuit and giving it the same circuit name will not however automatically create a snippet instance. You should either import multiple snippets onto a root sheet or make very sure that you have all your sub-circuits in place before importing the snippet to one of them.
  • If you are working with Assembly Variants and are exporting a project clip then the property set of the current variant will be exported. The fitted or not fitted status is not exported because the imported project clip will also import onto the base design of the destination.


ASSEMBLY VARIANTS

Introduction

Assembly Variants, sometimes called design variants, cater for situations where components that exist on the schematic are not to be installed/fitted on the final PCB in certain situations. For example:

  • You may have a design in which functionality is removed from a basic or intermediate version of the product.
  • You may want to test two prototypes of similar but not identical circuitry to evaluate performance,noise,efficiency, etc.
  • You may use pull-up and pull-down resistors to indicate the PCB/hardware revision to the microprocessor.

It is important to note that the bareboard PCB itself is unchanged between different assembly variants. Proteus will enable you to change the fitted status of components in a given configuration and will then automate the effects of this on the reporting and output systems to ensure consistency. You can also switch in alternative parts between variants provided that they have the same footprint (i.e. the board doesn't change).

Golden Rule

Always work in Base Design on the Schematic.

Base Design is the master or superset of all of the variants. This means you should always design the product in base design. This holds true even with things like debug headers that won't be present on the production PCB. You can't exclude items from base design so in this case you would most likely create two variants called TEST and PRODUCTION.

How it Works

It's really important to understand that an Assembly Variants is just a deviation from the Base Design. The Base Design must contain all of the elements and wiring and so you should always work on the schematic in Base Design. Assembly Variants are then created from the Design Explorer module in Proteus.

Where you have several variants you can choose to initialise a new one from an existing variant rather than from base design. This can be done from the copy existing variant checkbox in the dialogue form above. Always remember though that you can never have a part in a variant that doesn't exist in base design. All development must take place in base design.

Once created, a variant will be listed in a new column in the Design Explorer and each component in the design will have either a tick or cross to indicate whether the part is fitted or not fitted in that variant.

The variant that you have created will be available for selection in the variant toolbar. This combo-box is system global so switching to a different variant will affect various parts of the software (schematic, 3D Viewer, BOM, etc.)

You can quickly manage variants for a group of parts by first drawing a selection box on the schematic and then filtering the search tab in the design explorer to the result set from the tagbox.

You can remove a part from a particular variant by either :

1) Clicking on it's entry in the variant column of design explorer to change to a cross.

2) Switching to the variant in the variant toolbar and then editing the part on the schematic and selecting the 'Remove from Active Variant' checkbox.

You cannot remove a part from the base design.

If you then want to add a part back into a variant simply repeat the process in reverse.

Parts that are not present in the active variant are indicated with a cross in the column in design explorer and their part reference is greyed out on the schematic.

Remember that the schematic is a reflection of the Active Variant for the system as selected from the variant combo box, but that you can see a components status on all variants at the same time in design explorer.

You can add an alternative part for a passive (with the same footprint) in a variant by editing the value property.

If you need to change other properties such as stock code or supplier you do so by first adding the properties as columns and then changing their values in the current variant.

Finally, you can delete or rename a variant from the Variant menu in the Design Explorer module.

See Also:

Design Explorer Manual : Assembly Variants

Design Explorer includes several visual cues to help you with variants:

1) The active variant column header will appear in blue. If base design is selected all the variant column titles will be in black.

2) Properties that have been changed in the active variant will be in blue when the active variant is selected.

3) Components that are different in different variants will have their name in bold regardless of the selected variant.

Assembly Variants & Output Files

The selection of a variant in the combo-box will affect the following files, views and reports:

Schematic Capture

The state of a component in the active variant is indicated by a dimmed part reference.

You can add the @VARIANT keyword to the Header Block in order to identify the variant during hard copy printing or simply for clarity.

See Also:

The Header Block

Bill of Materials

If an assembly variant is selected in the combo-box then a row with the variant name is added to the header block at the top of the BOM. All parts excluded from this variant are also excluded in the BOM report.

If 'base design' is selected from the combo-box then the header block will not have an extra row inserted.

PCB Layout Module

Assembly variants have no effect on the 2D Layout by default, although the Assembly drawings generated will obviously reflect the status of the current variant.

We do support fabrication variants in so far as you can use the @VARIANT keyword in silkscreen text to allow you to identify the current variant on the layout. It does mean that in such cases you will then need to carefully manage the export of the manufacturing data files.

See Also:

PCB Manual: Assembly Layers

3D Visualisation

If you have turned off live netlisting in the Layout module (Tools Menu) then the 3D Viewer will not receive notifications when you switch the active variant..

Parts excluded from the active variant will not appear in the 3D Viewer because they are not to be fitted in this variant. All output filesets designed for MCAD such as STEP, IGES and IDF will also have such parts excluded.

Pick and Place Files

If you have turned off live netlisting in the Layout module (Tools Menu) then you may not have the latest netlist information and the Pick and Place output may not match the active variant.

Pick and place files will not include any parts excluded from the active variant.

Reporting

Using the Project Notes module you can automatically generate a report detailing all of the differences between each product variant and the base design.

See Also:

Variant Comparison Report


PIN-SWAP/GATE-SWAP

Introduction

Many types of component have either interchangeable pins - for example the two enable pins on a 74138, or interchangeable elements - for example the six inverters in a 7404. Some components such as the 7400 have both - there are four interchangeable gates each of which has two identical inputs. This phenomenon can be exploited when routing complex PCBs in that it may turn out to be easier to route to an alternate pin or gate to the one specified in the netlist. Clearly, making such a 'spur of the moment' decision will affect the connectivity of the design, and this change needs to be recorded and eventually reflected back on the schematic.

Proteus provides an extremely comprehensive degree of support for this aspect of the EDA problem. Specifically, the following features are provided:

  • A scheme for specifying swappable pins and gates within ISIS library parts.
  • The ability to mark a pin or gate in ARES and see a graphical display of which other pins and gates it can be swapped with based on the data from the ISIS library parts.
  • A gate-swap optimiser which will attempt to find the optimum gate allocations based on achieving the shortest possible ratsnest length.
  • Automatic back-annotation of both manual and automatic changes into ISIS.
  • A locking mechanism which prevents changes being made to both schematic and PCB simultaneously, thus preventing conflicts and ambiguities.

Specifying Pin-Swaps in Single Element Devices

This is achieved through the use of the Visual Packaging Tool, using the 'swappable pins' field at the time of packaging the component to specify the pins that can be swapped on the footprint.

The Packaging Tool showing the swappable pins on a single element part

Specifying Pin-Swaps in Multi-Element Devices

As with single element devices you should use the Visual Packaging Tool to specify pinswaps on multi-element parts such a the 7400 shown below.,

The Visual Packaging Tool launched on a 7400 showing the pin swap area

To add a pinswap group to a packaging:

  1. Highlight the pins to be swapped in the Pin Grid by holding down the CTRL key and clicking on each row in turn. In the above case, pins A and B are swappable, so you would highlight their rows as shown.
  2. Click the Add button to create the pinswap group.

You can define multiple swap groups by repeating the above procedure.

Specifying Gate-Swaps in Multi-Element Devices

It is a happy fact that ISIS can work out the much of the gate-swap information for a multi-element device entirely by itself. For example, in the case of the 7400 , the packaging script contains sufficient information to tell that the swappable element consists of pins A,B and Y and that there are 4 of them.

The only requirement is that we tell ISIS to allow gate swaps using the Gateswap checkbox in the Visual Packaging Tool

Note that the power pins VCC and GND are automatically excluded from the swappable element because they are hidden. They are also required to be on the same nets if a swap is to be made between different packages, since they are marked as being common

Once set up, you can perform gateswaps in ISIS from the Edit Component dialogue form.

Our final example is of a heterogeneous multi-element part - in this case a DPDT relay consisting of a coil and two pairs of contacts

Specifying gate-swaps on a heterogeneous multi-element device

In this case, both pins of the coil are both common and swappable. Omitting the common would, of course, be disastrous as it would allow swaps of contacts between different relays!

Performing Manual Pin-Swaps and Gate-Swaps in ARES

Pin-swaps and gate-swaps are both carried out in exact the same way using the Ratsnest mode in ARES.

To swap two pins or gates:

  1. Make sure that the layout is synched with the schematic - it must not be in either locked (live netlisting off) or changes pending mode.
  2. Select the Ratsnest icon in ARES.
  3. Click Right on the source pin. The Ratsnest lines connected to it will highlight.
  4. Click and hold down the left button. All pins with which the source pin can be swapped will highlight. This set includes all the valid pin-swaps within the source gate and all the same pin-sets in any valid gate-swaps.
  5. Drag the source ratsnest lines to the destination pin you want to swap with. If this pin is in the same gate then just a pin swap will be performed. If it is in another gate, then a gate-swap and possible also a pin-swap will occur.

There is little more to it than that. Note, however, that ARES will not allow swaps where any of the source or destination pins have tracking attached. In the case of a gate swap, all pins of both gates must be unrouted.

Pin-swaps and Gate-swaps constitute changes to the connectivity of your design. ARES uses the pin-swap and gate-swap data specified in the ISIS libraries to decide what is, and is not, a valid swap. If there are errors in this data, then ARES may well suggest illegal swaps. We will not, under any circumstances, be held liable for any costs incurred or losses arising as result of such mishaps, whether the error be in your library parts or ours or in the software itself. We strongly recommend that you check that the swaps you make are legal, and that you prototype your PCB prior to manufacturing large quantities.

The Gate-Swap Optimiser

In cases where a design has large numbers of swappable gates, it can be very hard to see what the best gate-allocation should be. The number of possible combinations can become literally astronomical even for small numbers of gates. The sample design SHIFT16 contains many more combinations than there are grains of sand in the sahara!

To help you find a near optimum solution, ARES incorporates and automatic gate-swap optimizer which will perform thousands of trial swaps in such a way as to find what is technically called a 'local minima' for a given board placement. In many cases this is very near optimum, and almost invariably gives some reduction in the total ratsnest length.

To use the Gate-Swap Optimiser:

  1. Make sure that the layout is synchronized with the schematic - you cannot perform this operation if ARES is in a locked (live netlisting off) or changes pending state.
  2. Place all the components in the usual way, aiming to achieve as low a ratsnest length as possible. The swap optimizer is no excuse for bad placement!
  3. Invoke the Gate-Swap Optimizer command from the Tools menu.

The algorithm makes repeated passes until such time as it can make no further improvement. Run times can be quite long (5-10 minutes) if there lots of possible swaps.

The Gate-Swap Optimizer relies entirely on the gate-swap data specified in the ISIS component libraries to decide what is, and is not, a valid swap. If there are errors in this data, then the swap-optimizer is likely to make erroneous changes to the connectivity of your design. We will not, under any circumstances, be held liable for any costs incurred or losses arising as result of such mishaps, whether the error be in your library parts or ours or in the software itself. We strongly recommend that this command be used only if you are going to prototype your PCB prior to manufacture.


MULTI BOARD PROJECTS

Introduction

This topic discusses using a single schematic to design a system with multiple PCB boards. For information on using a single schematic with multiple boards for simulation purposes please refer to the Proteus VSM help file.

When your product design includes more than one PCB you need to create a multi-board project in Proteus. A multi board project comprises of a single schematic design but multiple separate PCB boards where each PCB board can have it's own design rules and board stackup.

At the time of writing it is intended for use with multiple discrete rigid boards (e.g. mini connector boards) but we intend over time to enhance the scheme to more fully support flexi-design as well.

Setup

To create a multi-board project:

1) Run the New Project Wizard in the normal way. This will create a project with a single schematic and PCB board.

2) Switch to the PCB tab. Add any additional boards one at a time from the new board command on the File menu.

This creates additional boards with customisable stackup and drilling.

3) When you have multiple boards in the project you'll see a board selector appear at the top of application. This is the board selector and is a global combo box listing the boards in the project. You'll most likely want to rename the boards so switch to the design explorer tab and right click on the board names to change them.

Design Explorer is the module in Proteus that provides a global view of the project. It's a great place to look at project overview and for navigation via the right click context menu..

Don't try to have multiple boards on a single PCB view. You won't be able to configure stackups or design rules, the connectivity will become confusing and the scope for costly mistakes is high. You should create new boards and work within the framework outlined above.

Navigation

Now that we have created multiple boards it's important to understand how the system is intended to work. At any time you are working on a single board as defined in the global combo box at the top of the application. This has advantages for performance since only one board is rendered at a time and also provides clear separation between the boards to allow different design rules and layer stacks on each PCB. You can quickly switch between boards at any time by toggling the board selector.

Switch between boards with the selector.

On the schematic side you need to remember that a sheet belongs to a board. So, to work on the design for a particular board you need first to select the board and then select the sheet in the normal way from the Design menu.

Navigate to a sheet on the schematic.

If you prefer to navigate globally you can do so from the Design Explorer as shown earlier or you can use the Global Goto Sheet command on the Design menu in the Schematic Module.

Using Goto Sheet Command for Global Navigation

It's useful to map the Goto Sheet command onto a keyboard shortcut for quick navigation if you choose to use this method (System Menu -> Set Keyboard Mapping).

It can help with clarity if you name the schematic sheets as well. You can do this for the current sheet from the Edit Sheet dialogue form on the Design Menu:

Renaming Sheet with Prefix indicating the Board.

Development

Now that the basic setup is complete you can start design and development in the same way as normal. You work on one board at a time and simply use the board selector to switch between the different boards in the product. That said, there are a few areas where some extra thought and consideration are required.

Annotation

The question here is whether the annotation should be global to the project or global to the board. The default is global to the board rather than the project but you can change this by unchecking the box on the Edit Sheet properties dialogue. You only need to do this for one sheet per board.

Uncheck this on each Board for Project Global Annotation.

The top level for tools like the Global Annotator is Board Level. If you re-annotate in total mode at board level you will either get completely independent annotation (Board Local Part ID's) or completely unique annotation (Project Global Annotation)

In practise, we'd recommend board local annotation since it makes documentation like the BOM and Assembly Drawings more easily understood.

Multi-Element Parts

You clearly can't have different elements of multi-element parts on different boards since the footprint needs to be housed on one board. The system will try to detect this but with manual annotation it's possible to get this wrong.

Keep all elements of a multi-element part on the same board.

Power

Power rail configuration is global to the project, not the board. If you need board specific power rails you can create extra in the Power Rail Configuration dialogue form.

Since Net Classes relate to Design Rules they are Board Local.

Assembly Variants

Assembly variants are global to the project. You cannot for example have Variant 1 of Daughter Board 2 along with Variant 2 of the Main Board. Instead you should create a new variant and use the 'copy from variant' option in Design Explorer to initialise the whole project from the nearest variant. You can then make the necessary changes to the board or boards required for the new variant.

Create a new Variant based on an old one.

Sub-Circuits

You can build a sub-circuit hierarchy on a board in exactly the same way as you would in a single board project. You can even have mirrored sub-circuits on different boards, although it may be a little hard to keep track if you do so.

Header Block

The standard header block items are project global and set in the Edit Design Properties command on the schematic editor. If you want board specific content on the header block you can use the @BOARD syntax.

See Also:

The Header Block

Design Rules

Design Rules and Net Classes are board local. This allows you to set object clearances and routing widths for each board in the project independently. Coupled with the individual board stackup and drilling it means that each board is treated as a separate entity in the project.

Output

All of the output systems work on a per-board basis. Whether it's the Bill or Materials or the CADCAM Output you will need to generate the fileset for each board.

Board Switching

Switching boards automatically saves the current board to disk and then loads the requested board from disk. With multiple large boards in a project there may be slight delay while this happens.

File Size

It's possible with several complex boards that the file size on disk of the PDSPRJ file becomes quite large. However, we don't anticipate problems in development since only one board is loaded at any given time.

Deleting a Board

If you have added a board, or have decided that you no longer need a second or third board you may wish to remove it from the project. In order to do this you need to delete the schematic board associated to the board.


ICON REFERENCE CHART

Command Icons

New Layout | Load Design | Save Design
Import Section File | Export Section File | Print Schematic
Print Area | Refresh | Grid On/Off
False Origin | Pan | Zoom In
Zoom Out | Zoom to Schematic | Zoom to Area
Undo | Redo | Cut to Clipboard
Copy to Clipboard | Paste from Clipboard | Block Copy
Block Move | Block Rotate | Block Delete
Pick Device from Library | Make Device | Packaging Tool
Decompose Package | Toggle Wire Autorouter | Search & Tag
Property Assignment Tool | Design Explorer | Add a New Sheet
Return to Parent Sheet | Bill of Materials | Electrical Rules Checker
Netlist to ARES |  |

Mode Selection Icons

Selection Tool | Component Mode | Junction Dot Placement
Wire Label | Script Mode | Bus mode
Sub-circuit Placement | Pin placement mode | Graph Placement Mode
Tape Recorder Mode | Generator Mode | Voltage Probe placement
Current Probe Placement | Virtual Instrument Mode | 2D Line Mode
2D Square Mode | 2D Circle Mode | 2D Arc Mode
2D Path Mode | 2D Text Mode | 2D Symbol Mode
2D Marker Mode | Rotate Clockwise Mode | Rotate Anti-clockwise Mode
Mirror Mode | Flip Mode |


Save Incompable with Older Versions

SAVE INCOMPATIBLE WITH OLDER VERSIONS

The current release of the software includes feature requests and functionality which necessitate a change to the filing structure of the layout. Older versions of the software cannot therefore load files that have been saved in this version.

An example of this type of feature driven change is the introduction of off-schematic power rail configuration. Loading a schematic from a new version (containing this feature) into an older version (without this feature) could result in radically different connectivity when the file has been loaded..

If you absolutely need to save changes for loading into an older version you can use the 'Save As V7.0' filter on the Save As dialogue form. However, you must understand that while such files will load in older versions we will in no way guarantee the integrity of the design.

In particular, if your layout makes use of features which either did not exist or were implemented differently in Version 7.0 then the design may well be different when loaded into an older version of the software.

Labcenter do not recommend this process for production projects. Responsibility for design integrity lies entirely with the engineer.

Due to the impossibility of maintaining full backward compatibility with older versions of the software, Labcenter does not recommend the design of projects across multiple versions.


PACKAGING TOOL ERRORS

Packaging Errors with Mixed Device Types

This error occurs because you are trying to package a number of elements of which one or more elements are homogeneous and one or more are heterogeneous.

Solution

First of all, check that the only devices highlighted on the schematic are those which you want to package. This normally happens if, for example, you are trying to package a simple, single element device (such as a resistor) but another element elsewhere on the schematic is highlighted.

Should this not be the case and you are trying to package a multi-element device, follow the instructions below according to the type of device you want to package.

Packaging Multi Element Homogeneous Parts:

  1. Highlight a single element.
  2. Click on the Make Device icon.
  3. Launch the Visual Packaging Tool from the Packaging screen on the Make Device wizard.
  4. Specify the number of elements via the No. of Gates field as shown below.

Packaging Multi Element Heterogeneous Parts:

  1. Place all the elements that make up the device ensuring that all elements are annotated correctly with a sequential sequence of element Ids (U1:A, U1:B, etc.) as is shown in the example below.

  2. Highlight all the elements of the device ensuring no other components are tagged.
  3. Click on the Visual Packaging Tool icon.
  4. Proceed with packaging in the normal way.

See Also:

Making a Device Element.

Making a Multi Element Homogeneous Device.

Making a Multi Element Heterogeneous Device.

The Visual Packaging Tool.

The Make Device Command.

Packaging Heterogeneous Devices

The Visual Packaging Tool has encountered problems while trying to package a multi-element heterogeneous device. The correct techniques for packaging this type of device are covered in detail in the following help topics:

Making a Device Element.

Making a Multi Element Heterogeneous Device.

The Visual Packaging Tool.

The Make Device Command.

A listing of the possible error messages and a summary of the solutions is given below. Please refer to the help topics for more detailed information.

Error : A tagged component with a reference containing element ID 'x' was expected but not found.

Where ‘x’ is the element ID (A, B, C, etc.) that was expected but not found.

Cause

This means that the heterogeneous elements are incorrectly annotated. An example is shown below where the elements are annotated RL1:A, RL1:C but there is no RL1:B element.

Solution

Re-annotate the elements such that each element is annotated sequentially. In the above example, the correct annotation is shown below.

Error: Expected component element 'x' to be an instance of 'y' or a later device element.

Where ‘x’ is the element ID (A, B, C, etc.) that is in error and ‘y’ is the device name (library part name) that was expected.

Cause:

An element of a multi-element heterogeneous device is placed (i.e. is an instance of) a device that is not the same device or a later device to that used in the previous element.

Consider the generic case of a multi-element heterogeneous device consisting of elements U1:A, U1:B, U1:C, U1:D, etc. where each element is an instance of a device DEVICE:A, DEVICE:B, DEVICE:C and so on. It is a requirement that if, for example, U1:A is an instance of DEVICE:A, then U1:B (the next element) must either also be an instance of DEVICE:A or a later device (i.e. DEVICE:B, DEVICE:C, etc.). The same applies to U1:C in regard to U1:B, and so on.

Solution:

Re-annotate the elements such that moving through the elements (U1:A, U1:B, etc.) each element is the same or a later device to the device in the previous element.

Error: A tagged component with a reference 'x' (i.e. element 'y') was found but not expected.

Where ‘x’ is the component reference of the element that was found and ‘y’ is the actual element ID.

Cause:

This error occurs where the annotation of elements in a multi-element heterogeneous part are not sequential. In the example below, this error would occur for element ‘C’ ; given that only two elements are highlighted, an element ‘C’ is unexpected.

Solution:

Re-annotate the elements such that the annotation is sequential and consistent with the number of elements. In the example above , having two elements highlighted they should be annotated as RL1:A and RL1:B as shown below.

Error: For a multi-element heterogeneous device with N elements there should be N tagged components with element ID's A,B,C, etc. in the correct sequence with no omissions and no extra elements.

Cause:

This is a postscript and is applied to any the bottom of any of the previously discussed errors. It is intended as a reminder to how to correctly annotate the elements of a multi-element heterogeneous device.

Solution:

Review the help on the actual error messages to determine how to correct the error.

Packaging Errors with Pins

The Visual Packaging Tool has encountered problems with the pins on the device you are trying to package. Below is a listing of possible error messages and the steps you should take to correct the error.

Error: There are two more pins with the same name (‘x’) in legacy device ‘y’.The device cannot be packaged until it is re-made via the Make Device command (you do not need to rename the pins)

Where ‘x’ is the pin name that is duplicated and ‘y’ is the name of the device (library part) containing the duplicate pins.

Cause:

You have a device (created in an earlier version of the software ) in which more that one pin has the same name.

Solution:

Edit the pin names on the device (you may first have to decompose the part) such that each device pin has a unique name.

With Proteus it is possible to have more than one pin with the same pin name on a device and these pins are considered internally connected. This is useful if, for example, you want to want to wire ‘through’ a device and so would place one pin on either side of the device body. You must, however, remake the device in Proteus to avoid any possible legacy issues with older library parts.

We consider this functionality to be for advanced users of the software and should not be attempted if you are unsure of the consequences.

Error: Pin 'x’ found in two different heterogeneous devices (y and z). This is not allowed.

Where ‘x’ is the name of the pin and ‘y’ and ‘z’ are the two devices (library parts) that contain the pin.

Cause:

You are attempting to package a multi-element heterogeneous device where two or more different devices (library parts) that make up the overall device contain a pin with the same name.

Note that this error does not occur where you are making a multi-element heterogeneous device where two or more elements are instances of the same library part – for example, a relay consisting of a coil (an instance of RELAY:A) and two sets of contacts (two instances of RELAY:B). In this case the two contact elements will, by definition, have like pins, but since both elements are the same device, this is legal. However, if the coil (RELAY:A) and contacts (RELAY:B) both contained a pin with the same pin name, this would be an error.

Solution:

Re-make one or more of the devices that make up the multi-element device such that its pin names are unique (i.e. decompose the device, reannotate the pins and re-make the device). Ensure you say ‘yes’ to update the existing devices in the schematic when prompted before re-starting the Visual Packaging Tool.

Packaging Tool Warning Messages

The Visual Packaging Tool has encountered one or more warnings while packaging the device. The possible warning messages along with explanations are listed below:

Warning : Bus pin ‘x’ of device ‘y’ has no range.

Where ‘x’ is the name of the bus pin and ‘ y’ is the name of the device.

Cause:

You have used a bus pin for which there is no range specified. Each bus pin must have a range specified in order that you can tap off the bus and that you can correctly package the device.

Solution:

Edit the bus pin (you may first have to decompose the part) and specify a range for the bus. The example below shows the Edit Pin dialogue form for a bus pin and the syntax for a standard eight pin bus. Note that you can choose to have the bus range hidden on the schematic if you prefer it but you must specify a range.

See Also:

Buses.

Labelling a Bus.

Bus Properties.

Warning: Packaging ‘x’ specified in 'y’ is different to packaging specified in 'z’

Where ‘x’ is the name of a packaging and ‘y’ and ‘z’ are two devices.

Cause:

This occurs only with legacy devices only and means that you are packaging a multi-element device where different elements specify the same package name (e.g. DIL40) but the pinouts (which specify the pin numbering) for each element is different. This is ambiguous and only one of the pinouts (sets of numbering) will be used.

Solution:

You can safely continue from this warning but be sure to double check that the pin numbering for the named packaging is correct in the Visual Packaging Tool.

Warning: Device 'x’ was not found in any library.

Where x is the name of a device that was not found.

Cause:

The device you are trying to package cannot be found in any of the ISIS libraries. This may be because you have not created the part (i.e. the schematic has been passed to you from another user who has created the part in his libraries) or that the location of the library containing the part is not included in your system path.

Solution:

This warning can in general, be safely ignored. Its purpose is to indicate that if you subsequently bring in to play the original library containing the original device, you will have two instances of the same device in two different libraries. It is good library discipline to ensure that a device only occurs in one library.

Warning: Device 'x' was found in a read-only library 'y'.

Where ‘x’ is the name of the device you are packaging and ‘y’ is the name of a device library that is set as read-only.

Cause:

The device for which you are trying to assign packages exists in a library that is read-only. This is either because it is in a library supplied with the software, because you have specified one of your own libraries to be read-only, or because your user permissions prevent you from writing to the library.

Solution:

The purpose of this warning is to indicate that if you now store the part in a writable library, the same named device will be in two different libraries and this will may lead to ambiguities later on.

At the stage of getting the warning message it is probably best to immediately store the newly packaged device in any suitable writable library and then resolve the issue as follows:

  • If the original part exists in one of the system libraries (i.e. a library supplied with the software) then use the Library Manager (launched from the Library menu) to change the name of the newly packaged device such that its name is unique.
  • If the part exists in one of your own user libraries which is set to read-only then use the Library Manager (launched from the Library menu) to temporarily remove the read-only setting on the library and to then move the part from the library you saved it in to your own library and then restore the read-only setting.
  • If your access permissions prevent you from writing to the library you will need to contact your Network Administrator to resolve the issue.

Bear in mind that it is important to maintain Library Discipline to avoid future complications.

You should always avoid having the same named library part in two or more libraries to avoid ambiguities.

You should never update parts in the system libraries (those supplied with the software as these may be overwritten by a future update of the software.

Warning: Device 'x' was found in a different library (y) to other tagged devices.

Where ‘x’ is the name of the device you are packaging and ‘y’ is the name of a library.

Cause:

You are attempting to package a multi-element heterogeneous device where not all the devices that make up the heterogeneus device exist in the same library. For example, if you are packaging a relay, where the coil exists in one library and the contacts are in another, then you will get this warning message.

Solution:

Use the Library Manager (selectable from the Library menu) to move the element(s) such that all elements are in the same library and are not duplicated in any other library. You can then safely package the device.

Warning: Device 'x’ was found in several libraries.

Where x is the name of the device you are packaging.

Cause:

The device you are trying to package exists in more than one library. This is either because you have created the device more than once and placed it in a different library each time, or because you have altered a device that exists in the system libraries (those supplied with the software) and placed it in one of your own libraries without using a different name.

Solution:
  • If the device exists in more than one of your own libraries you should either delete the device from one library or, should the devices be different in appearance or functionality, rename the devices via the Library Manager (selectable from the Library menu).
  • If the device exists in one of the system libraries and also in one of your own libraries you should rename the part in your library such that it has a unique name.

You can then safely package the device.


Configure Diagnostics

Overview

Diagnostic messaging in Proteus is an extremely powerful debugging tool. This dialogue allows you to configure what messages you wish to be output and at what severity level for the parts on the current schematic. The list is dynamically updated with parts on the schematic that contain the ability to output diagnostic messages.

Turning on diagnostics for a particular part or onboard peripheral is one of the best ways to quickly find problems in a design but it does come at the expense of simulation performance as large amounts of ASCII text can be output.

All diagnostic messages are written to the simulation log and can be viewed either during simulation, when single step debugging or after a simulation is completed.

Options

Trace Categories

Expand the treeview where appropriate to enable additional options and select the option for which you want to change the diagnostic levels. The contents of the treeview reflect the current schematic so all components on the design containing diagnostic information are available for selection here.The icons to the left of each item indicate the currently configured diagnostic level for that item.

Trace Information Level

These options allow you to configure the level of detail if the diagnostic reporting (from Disabled, through Warnings Only, down to Full Trace). Bear in mind that the more detail you specify the slower the simulation will run as more data is required to be written to the simulation advisor.

Additionally, the Suspend checkbox allows you to suspend the simulation every time an event is logged to the simulation advisor. This is exceptionally useful when you need to closely monitor activity on a processor peripheral for example but enabling this when full trace is configured will almost certainly result in the simulation pausing frequently!

Log From

This option allows you to specify a start or arm time after which the diagnostics will become active. Typically, you might use this to bypass initialization or where you know the approximate time at which a certain problem is occurring. Together with the Run Time option this allows you to control the amount of trace data output this making it easier to assimilate the data.

For

This option allows you to specify the amount of time (in seconds) subsequent to the specified start time for which the configured diagnostic options will be active. For example, if you wanted diagnostic reporting between 15s and 25s you would set the start time to be 15s and this option to be 10s.


Execute for Specified Time

Overview

This dialogue form allows you to specify the time that the simulation will run for before it stops. For example it could be used to check if a program runs well up to a point before a bug, or to stop a program if automatically after a certain time if the program loops.


Edit Design Properties

Overview

This dialogue allows you to provide design information for use both in the Bill of Materials report and during design netlist.

Options

Filename

Click to specify a path and filename for the file to be exported.

Title

Specify the title of the design. This will appear at the top of any reports generated from the design (BOM Scripts, Netlists etc.). Note that this is not the same as the filename.

Doc. No.

Specify the document number for the design. This will appear in any reports (e.g. BOM scripts, Netlists etc.) that are generated from the design.

Revision

Specify the revision number. This will appear on any report generated from the design

Author

Specify the author of the design.

Nestlisting Options

These design configuration options each have their own context sensitive help topic.

  • Global Power Nets? - Specify whether power nets are to be assigned locally or globally (across all sheets).
  • Cache Model Files? - Specify whether or not model ( .mdf ) files are saved within the design files. If checked, this means that a design can be loaded and simulated by a third party who does not have the models used in the design. Note, however, that VSM Model DLLs cannot be cached.


Edit Sheet Properties

Overview

This dialogue allows you to specify various properties relevant to the current sheet.

Options

Module Name

The module name is the name of the current hierarchy level on the schematic design. For a single board project the root level of the schematic design is called ROOT and for a multi-board project it will be BOARD1, BOARD2 etc at the root level. Root level module names are not editable but modules names for other modules further down the sheet hierarchy (e.g. sub-circuits) can be changed.

Sheet Title

Specify the title of the sheet. The title is displayed on the Design Menu and other tools and can be changed to reflect the contents of the sheet.

Sheet Ordinal

The sheet ordinal serves only to determine the presentation order of the child sheets of a module. Only root modules can have multiple child sheets.

Annotator Init

Specify the annotation offset for the sheet. This value is used by the automatic annotator to determine the starting value for component references on the sheet and, in conjunction with the replicate command in ARES, can allow you to duplicate identical blocks of circuitry on the layout.

Board Local Part ID's

This option is relevant only for multi-board projects. The question here is whether the annotation should be global to the project or global to the board. The default is global to the board rather than the project but you can change this by unchecking this option. You would only need to do this for one sheet per board but if you choose to work with project global annotation it's really important that you do uncheck this option for every board otherwise you will end up with an annotation muddle.

In practise, we'd recommend board local annotation since it makes documentation like the BOM and Assembly Drawings more easily understood.

Non-physical sheet?

Specify whether or not the components on the sheet are to be included a a netlist for PCB layout. Check the checkbox for any sheet which is a simulator model as opposed to a physical part of the design.

Synchronise Siblings

It is possible in Proteus to have identical sub-circuits by providing the same circuit name to each sub-circuit. Then, whatever you place and wire on one sub-circuit is mirrored onto all others with the same name (E.g. left and right channels of an amplifier). By default, the property values on sub-circuits will also be maintained / kept the same (this option selected). For example, if you change a resistor to 470Ohm on one sheet the equivalent resistor on the other mirrored sheets will also change to 470Ohm. If you want to customize different sub-circuits and allow the parts on to have different properties on different sheets you need to uncheck this box.

External .MOD file?

Specify whether or not you want the sheet to be linked to an external .MOD file. This allows child circuits to be shared between designs. External MOD files are kept in the MODELS directory. Recommended for advanced users only.


Goto Sheet

Overview

This dialogue form allows you to quickly navigate between sheets, this can also be done by using the page up and down keys on your keyboard.


Power Rail Configuration

Overview

This dialogue form allows you to configure power connections and to connect supplies to rails. If you prefer you can do the same thing by wiring power terminals together on the schematic (e.g. VCC & +5V) - all such connections will be honoured by this configuration tool.

Options

Power Supplies

This groupbox contains a series of controls (each with it’s own context sensitive help) which allow you to configure the characteristics of all the power supplies on the schematic.

  • Name - Displays a list of existing power supplies for the current design. This list is populated both from the default set of power supplies (preconfigured and shipped with the software) , with any explicitly defined power supplied on the schematic and with any power supplies you have added via this dialogue form. For each power supply a list of power nets connected to the rail is displayed towards the bottom right of the dialogue.
  • New - Specify a new power supply. This allows you to create a power supply which you can then configure via the other options on the dialogue form.
  • Rename - Rename an existing power supply. This allows you to rename the currently selected power supply. Note that if the power supply has been explicitly specified on the schematic (e.g. a power terminal annotated +12V) this field will be disabled.
  • Delete - Delete the currently selected power supply. Note that you cannot delete a power supply via this dialogue form where the power supply has been explicitly specified on the schematic.
  • Voltage - Set the voltage for the currently selected power supply. Note that power supplies which have been explicitly specified on the schematic (e.g. a power terminal annotated +12V) cannot have their voltage altered via this dialogue – this field will be disabled for such supplies.
  • Class - Set the strategy for the currently selected power supply. By default all supplies will be assigned the POWER strategy but, should a rail require particular consideration you can specify a custom strategy name here and configure design rules etc. for the strategy in ARES. Note that where a strategy has been specified explicitly on the schematic (e.g. a wire label annotated STRAT=FRED) you cannot change the strategy via this dialogue form.

Unconnected power nets

This listbox contains all the power nets currently on the schematic which have not been bound to a power rail. You can assign a net to a power supply by selecting the desired supply from the combo box above (or creating a new supply via the New button), left clicking on the net name within this listbox to highlight the net, and then clicking the mouse on the Add button to assign the net to the power supply.

Nets connected to GND

This listbox contains all power nets assigned to the power supply currently selected via the combo box at the top of the dialogue form. You can add unassigned power nets or remove existing power nets via the Add/Remove buttons to the left of the listbox.

Add

Use this button to assign a highlighted (unconnected) power net to the currently selected power supply. In the case where two (or more) power nets have been wired together on the schematic, assigning one net to a power supply will assign all the conjoined nets as well.

Remove

Use this button to remove a highlighted (assigned) power net from the currently selected power supply. In the case where two (or more) power nets have been wired together on the schematic, removing one net from a power supply will remove all the conjoined nets as well.

Use default power rail connections

When checked the default power supplies will be applied to the current design. Note that at the point of activation this will supersede any manual edits that have been made to power supplies with the same names as those in the default set. We recommend that you leave this option enabled unless you specifically require customisation of the default power supplies.


Align Components

Overview

This command allows you to automatically align selected objects on the schematic according to the set criteria. To select multiple objects for aligning either :

  • Drag a tagbox around the objects.
  • Left click to select an object and then hold the CTRL button down while left clicking to select additional objects.

Options

Action

This determines what the reference point for the aligning operation should be. You can choose to align to any edge or to center either vertically or horizontally.

Align Point

This combo box allows you to choose between using the Object Bounds or the Connection Points as the Align Point. This determines which part of the object is considered when aligning in the manner specified through the Action options.


Diff Pair Configurator

On the schematic there are two tasks required for a diff pair, namely to identify the differential pair pins and then to name the diff pair itself. Both of these are done with the diff pair configurator tool which is launched from the right click context menu on one of the two diff pair wires.

The differential Pair Configurator when opened.

1. Diff Pair Class.

Name of the diff pair class. This is used when setting clearances and separations for the diff pair. Can use an existing one if , for example, you have multiple channels.

2. Start Component.

The start component and the two diff pair pins on the start component.

3. Signal Path Indicator

Shows whether the diff pair signal path is completely specified from source to destination.

Examples of how the Signal Path Graphics inform you of configuration progress.

4. End Component.

The end component and the two diff pair pins on that component.

5. Manage Pass through components.

Manually specify pass through components if the heuristic fails to do it correctly. A deduced pass through will be suffixed with a question mark. If correct save will commit, if incorrect specify manually via the Manage Passthroughs button.

A pass through has 2 pins on at least one of the diff pair lines. A tap, branch or shunt is not a pass through component and will be ignored by the configurator. The goal of managing the passthroughs is to specify the two pins of the component that are on the line - a simple task for a two pin passive but possibly needs manually specifying for a 4-pin part spanning both lines.

6. Component pin count.

Since the start and end component are unlikely to be 2 pin devices this setting serves only to remove the clutter from the component pin listings.

See Also:

Schematic Setup Workflow and Examples


Edit Component

Overview

This dialogue form is the main editing window for the object. Users can add fields to the dialogue form by specifying additional properties for the component in the Make Device dialogue form. This means that each component can contain arbitrary information relevant to that particular device. The options detailed below are therefore simply some of the most common that will be found in Labcenter produced library parts.

Options

Component Reference

Specify the part ID for the component. If the component is part of a multi-element part such as a 7400, use the naming syntax U1:A, U1:B etc. to select the different gates. ISIS will update the pin numbers automatically, when the part reference is so edited.

Hidden - If checked the component reference will not be visible on the schematic.

Resistance

Specify the component's part value.

In ISIS 5.1, the data type, description and value range for this field can be defined for each device type by giving a property definition for the VALUE property.

Hidden - If checked the component value will not be visible on the schematic.

Model Type

If present, this field specifies whether a component is considered digital, analog or mixed mode by the Proteus simulation engine. Only applicable for parts with simulation models and therefore typically only present in Labcenter produced library parts.

PCB Package

When present, this field allows specification of one or more PCB footprints which are associated with the component for the purposes of PCB layout. This field is present on most physical devices and is used when netlisting to the ARES layout software to load the footprint for placement.

Other Properties

A free format text block in which you can add as many additional properties as you require. Text enclosed between curly brackets ('{' and '}') is hidden.

See also the Edit all Properties as Text button.

Exclude from Simulation

This option provides the means for a user to exclude parts from a simulation but leave them present on the schematic for physical netlist purposes. For example, connectors and crystals should not be simulated but would need to be present for PCB layout.

Exclude from PCB Layout

This options provides the means for a user to exclude parts from a PCB but to include them when simulating the schematic. For example, non-physical parts such as oscilloscopes and logic analysers are used in the simulation but are not present in the physical layout of the board.

Edit all properties as text

If checked, then all component properties are placed into the free format text block. This bypasses the syntax checking present when property definitions are in use, and allows you to enter parameterized expressions for the property values.

In addition properties specified as HIDDEN by their property definitions can be viewed and/or edited.

Recommended for advanced users only.

Attach hierarchy module

If checked, this option causes a child sheet to be attached to the component. You can access the child sheet by pointing at the component and pressing CTRL+'Z'. The name used for the child sheet is determined when the device was made via the External Module field of the Make Device Dialogue form. If no external module was specified, ISIS uses the name of the device itself.

This behaviour is different from ISIS versions prior to 5.1. Backward compatibility for old designs is retained.

Hide common pins

When checked, all the common pins on the element being edited will be hidden. This is intended for use with multi-element homogeneous parts where you only want the common power pins on one or more elements to be hidden. For example, with a quad op-amp you might only want power pins visible on one element and would therefore use this option to suppress the common power pins on the other elements.

This option will be disabled for components with no common pins.


Edit Script Block

Overview

This dialogue form allows you to change the text and style of a script block on the schematic. Changes to the style via this dialogue form are local to the script you are editing; persistent or default changes should be made via the Set Text Styles command on the Template Menu

Options

Text

Modify the properties of the script block here. You can exit the form using Ctrl & Enter. You can change the default size of the script block window by clicking on the ISIS icon at the top left of the dialogue form and selecting Save Window Size.

Rotation

Select whether the text is oriented horizontally or vertically.

Justification

Select whether the text is left, centre or right justified, and whether it its origin is at the top or bottom.

External File

  • Import - Imports text from a text file on your hard disk.
  • Export - Export the script block to a text file.


Find and Edit Component

Overview

This dialogue form allows you to enter the name of a component which will then lead to another dialogue form allowing you to edit the component you named.

Options

Component

Enter the name of the component to be searched for.


UpdateAllInstances

Update All Instances with Local Changes

Introduction

A global update to a device has taken place on the schematic but some of the instances of the device have got local changes as well. This is an ambiguous situation and the user needs to inspect and correct.

The global update has been triggered by:

  • Right clicking and selecting Make Device on one of the components on the schematic.
  • Picking the part back into the project from the libraries.
  • Right clicking on the parts bin and selecting update on the device.

Local changes to component instances are simply changes to the schematic properties so that they are different from the device properties. This can happen in many ways such as:

  • Edit component dialogue form
  • Property Assignment Tool
  • Design Explorer
  • Bill of Materials Property Editor

It is not safe for the software to quietly replace all of the local changes when you do a global update since they were clearly intentional at the time they were changed. What happens therefore is that properties without local changes are updated and the user is provided with two methods to review and correct local changes as necessary. This is quite an important process to follow since orphaned local changes can result in an incorrect bill of materials report.

Design Explorer Review and Correct

If there are several instances with local changes the best place to review them is going to be in design explorer. This will give you a spreadsheet like view of the parts with changed properties in bold. Start by opening design explorer and then go to View Menu -> Property Columns. Select the checkbox for adding columns for properties with local changes. This will leave you with a grid of parts and properties that you can change as needed.

Add columns for each property that is changed compared to the device.

Make sure to switch to base variant if you are using assembly variants. You cannot make changes like this in an assembly variant

In this example, we see that the package has changed for several of the parts and so the package property is shown in bold.

The Package Properties in bold are different than those in the device.

What this means is that someone has edited the parts or otherwise changed the package on the schematic such that it is different from that in the device. This may or may not now be what the user wants the package to be. You can see what the value of the property in the base device is by hovering the mouse over the property.

Tooltip provides information about the base device value for the property.

This allows you to compare the base device value and the locally changed value to decide which you intend to keep. You can right click on a cell and restore to the default value from the resulting context menu.

Reset Local Change to Default (device) value.

If it's a multi-sheet design it's often easier to switch to the search tab in design explorer and check the local changes checkbox there. This will give you all the parts from all the sheets in one list that can be ordered.

Switch to the search tab to review all parts with local changes on a single screen, rather than by sheet.

The local changes check box will be disabled if you are working inside a variant because by definition there will be local changes between an assembly variant and the base design. What we are looking for here are local changes between base design and the library device so you must be in base design. If you have not created assembly variants you will always be in base design.

If you want to change the value back to the main device value just click in the cell and type the old value back in. You then work through all bold items in the same way, deciding whether base device value or locally changed value is what you want to keep. The display on the search tab is live and so parts will disappear from the list when you remove the last property with local changes.

On Schematic Review and Correct

If there is only one or two parts it may be faster to review on the schematic. The parts will be tagged by default and, if you lose the tag, you can re-select them via the tag local changes option on the context menu in the parts bin.

Select instances of a part with local changes on the schematic.

You can then sheet navigate (PGUP/PGDOWN) and simply edit component to inspect and change the local values if necessary.


EXPORT PDF

Overview

This dialogue form allows you to export the current layout in PDF format.

Options

Scope

Select which part(s) of the design you wish to export from the given options. Note that not all of the options may be available at any one time.

  • Marked Area - Export the marked area as set by the Set Area command on the File menu. This option is only enabled where there a marked area and there is no maximised graph.
  • Current Graph - Export the currently maximised graph. This option is only enabled where a graph has been maximised. To maximise a graph either select the graph title from the bottom of the Graph menu or click left once on the graph's title bar.
  • Current Sheet - Export the currently displayed sheet. This option is only enabled where there is no maximised graph.
  • All Sheets - Export all sheets, including root sheets and hierarchical sub-sheets. This option is only enabled where there is no maximised graph.

Options

Specify any particular options for the dialogue form.

  • Colour Output? - Specify whether or not the output will be in colour or monochrome.
  • Background Colour - Select a background colour for the exported layer set. Some caution is required to ensure sufficient contrast and visibility of the output.
  • Launch Viewer? - View the exported PDF file in your installed PDF Viewer on completion.

Rotation

Specify the desired x-rotation for output.

Our Virtual Graphics subsystem can produce output with the x-dimension either vertical or horizontal on your peripheral. This lets you orient your work most naturally within the Layout Editor and still be able to make the best use of the size of your peripheral when producing artwork.

The terms x-horizontal and x-vertical will depend also on the whether you have selected portrait or landscape mode for the print device itself. On a portrait page we define horizontal to mean parallel to the short edge.

Output To File?

Browse your hard disk to select a directory and file into which to save the output.


EXPORT SVG

Overview

This dialogue form allows you to export the current layout in Scalable Vector Graphics (SVG) format.

Options

Scope

Select which part(s) of the design you wish to export from the given options. Note that not all of the options may be available at any one time.

  • Marked Area - Export the marked area as set by the Set Area command on the File menu. This option is only enabled where there a marked area and there is no maximised graph.
  • Current Graph - Export the currently maximised graph. This option is only enabled where a graph has been maximised. To maximise a graph either select the graph title from the bottom of the Graph menu or click left once on the graph's title bar.
  • Current Sheet - Export the currently displayed sheet. This option is only enabled where there is no maximised graph.

Options

Specify any particular options for the dialogue form.

  • Colour Output? - Specify whether or not the output will be in colour or monochrome.
  • Background Colour - Select a background colour for the exported layer set. Some caution is required to ensure sufficient contrast and visibility of the output.
  • Launch Viewer? - View the exported SVG file in your system viewer on completion.

Rotation

Specify the desired x-rotation for output.

Our Virtual Graphics subsystem can produce output with the x-dimension either vertical or horizontal on your peripheral. This lets you orient your work most naturally within the Layout Editor and still be able to make the best use of the size of your peripheral when producing artwork.

The terms x-horizontal and x-vertical will depend also on the whether you have selected portrait or landscape mode for the print device itself. On a portrait page we define horizontal to mean parallel to the short edge.

Output To File?

Browse your hard disk to select a directory and file into which to save the output.


Create New Design

Overview

This dialogue form lists all the available design templates and is created by gathering up all the design template files from your template path(s) as specified via the Set Paths command on the System menu. To initialize your schematic from a template either double click on the desired template in the list or click once to highlight and then click the OK button.


Export Bitmap

Overview

Use this dialogue form to export your design as a standard Windows bitmap. If you don't check the Output To File option, the bitmap will be placed on the clipboard.

Options

Scope

Select which part(s) of the design you wish to export from the given options. Note that not all of the options may be available at any one time.

  • Marked Area - Export the marked area as set by the Set Area command on the File menu. This option is only enabled where there a marked area and there is no maximised graph.
  • Current Graph - Export the currently maximised graph. This option is only enabled where a graph has been maximised. To maximise a graph either select the graph title from the bottom of the Graph menu or click left once on the graph's title bar.
  • Current Sheet - Export the currently displayed sheet. This option is only enabled where there is no maximised graph.
  • All Sheets - Export all sheets, including root sheets and hierarchical sub-sheets. This option is only enabled where there is no maximised graph.

Resolution

Choose from 100 to 600 DPI. Memory usage increases in proportion to the square of the resolution so a 600 DPI bitmap needs 36 times as much memory as a 100 DPI bitmap. A 100 DPI bitmap in 256 colours needs 10k bytes per square inch (5kB if in 16 colours).

Colours

Specify the colour depth of the export from the options given.

  • Mono - Print the exported graphic in monochrome (black and white)
  • 16 - Print the exported graphic in 16 colours.
  • 256 - Print the exported graphic in 256 colours.
  • Display - Print the exported graphic using the same bitmap format as your display adapter.

Rotation

The Virtual Graphics Device subsystem can produce output with the x dimension either vertical or horizontal on your peripheral. This lets you use the length of your peripheral to best effect. For example, with a wide carriage 9 pin printer it is possible to print an A2 sheet at 1:1 scaling though this will take a considerable amount of time.

Output to File?

Use these options if you want to export to a file.


Export Metafile

Export Metafile/PDF

Overview

Use this dialogue form to export your design as an enhanced metafile (standard metafiles are no longer supported). If you don't check the Output to File option, the metafile will be placed on the clipboard.

Options

Scope

Select which part(s) of the design you wish to export from the given options. Note that not all of the options may be available at any one time.

  • Marked Area - Export the marked area as set by the Set Area command on the File menu. This option is only enabled where there a marked area and there is no maximised graph.
  • Current Graph - Export the currently maximised graph. This option is only enabled where a graph has been maximised. To maximise a graph either select the graph title from the bottom of the Graph menu or click left once on the graph's title bar.
  • Current Sheet - Export the currently displayed sheet. This option is only enabled where there is no maximised graph.
  • All Sheets - Export all sheets, including root sheets and hierarchical sub-sheets. This option is only enabled where there is no maximised graph.

Options

Use these checkboxes to configure output options for the metafile.

  • Colour Output? - Specify either a colour output or a monochrome output.
  • Erase Background? - If checked, this option causes ISIS to draw a rectangle in the current 'paper' colour before drawing anything else in the metafile.
  • Launch Acrobat? - Launch a copy of Adobe Acrobat Reader with the current output loaded.

Rotation

The Virtual Graphics Device subsystem can produce output with the x dimension either vertical or horizontal on your peripheral. This lets you use the length of your peripheral to best effect. For example, with a wide carriage 9 pin printer it is possible to print an A2 sheet at 1:1 scaling though this will take a considerable amount of time.

Output to File?

Use these options if you want to export to a file.


Export DXF/EPS

Overview

This dialogue allows you to export the current schematic as a DXF/EPS file for import into other software.

Options

Filename

Click to specify a path and filename for the file to be exported.

Scope

Select which part(s) of the design you wish to export from the given options. Note that not all of the options may be available at any one time.

  • Marked Area - Export the marked area as set by the Set Area command on the File menu. This option is only enabled where there a marked area and there is no maximised graph.
  • Current Graph - Export the currently maximised graph. This option is only enabled where a graph has been maximised. To maximise a graph either select the graph title from the bottom of the Graph menu or click left once on the graph's title bar.
  • Current Sheet - Export the currently displayed sheet. This option is only enabled where there is no maximised graph.
  • All Sheets - Export all sheets, including root sheets and hierarchical sub-sheets. This option is only enabled where there is no maximised graph.

Scale

You can scale the output from 1:1 down to 1:4 so that, for example, a drawing entered on a nominally A2 sheet can be rendered on an A4 laser printer at 300 dpi. Obviously, the hard copy device must have sufficient resolution if legibility is to be maintained. There is no support for printing a large drawing across multiple A4 or other small pages.

Rotation

The Virtual Graphics Device subsystem can produce output with the x dimension either vertical or horizontal on your peripheral. This lets you use the length of your peripheral to best effect. For example, with a wide carriage 9 pin printer it is possible to print an A2 sheet at 1:1 scaling though this will take a considerable amount of time.

Reflection

Specify whether you wish normal (i.e. as seen on screen) or mirrored output.


Export Vector

Overview

This dialogue allows you to export the current schematic as a Vector file for import into other software.

Options

Filename

Browse through your computer to determine where to save the Vector file.

Device

  • HPGL - Export in Hewlett Packard Graphics Language (HPGL) standard format. This assumes a top left origin.
  • HPGL (CTO) - Export in Hewlett Packard Graphics Language (HPGL) CTO format. This assumes a centre origin.
  • HI-80 - Export in HI-80 format. This format is compatible with most Epson Plotters.
  • DPML - Export in DPML format. This format is compatible with the Houston plotter series.

Scope

Select which part(s) of the design you wish to export from the given options. Note that not all of the options may be available at any one time.

  • Marked Area - Export the marked area as set by the Set Area command on the File menu. This option is only enabled where there a marked area and there is no maximised graph.
  • Current Graph - Export the currently maximised graph. This option is only enabled where a graph has been maximised. To maximise a graph either select the graph title from the bottom of the Graph menu or click left once on the graph's title bar.
  • Current Sheet - Export the currently displayed sheet. This option is only enabled where there is no maximised graph.
  • All Sheets - Export all sheets, including root sheets and hierarchical sub-sheets. This option is only enabled where there is no maximised graph.

Scale

You can scale the output from 1:1 down to 1:4 so that, for example, a drawing entered on a nominally A2 sheet can be rendered on an A4 laser printer at 300 dpi. Obviously, the hard copy device must have sufficient resolution if legibility is to be maintained. There is no support for printing a large drawing across multiple A4 or other small pages.

Rotation

The Virtual Graphics Device subsystem can produce output with the x dimension either vertical or horizontal on your peripheral. This lets you use the length of your peripheral to best effect. For example, with a wide carriage 9 pin printer it is possible to print an A2 sheet at 1:1 scaling though this will take a considerable amount of time.

Reflection

Specify whether you wish normal (i.e. as seen on screen) or mirrored output.


Print Design

Overview

This dialogue allows you to configure the scale and range of the schematic for printing.

Options

Printer & Output Device

This allows you to specify and configure the printer output device for the current print job. Note that selecting a different print device here will not change the default printer for ISIS. You can specify the default printer for use with ISIS via the Printer Setup option on the File Menu.

  • Printer - Use this button to configure the printer device for the current print job.
  • Filename - Click to specify a path and filename for the file to be exported.

Options

Use these options to specify colour output or to use the Labcenter Plotter Driver. Note that the plotter driver button is only enabled if you have specified a plotter device (via the printer button on the left).

  • Print in Colour? - Check this box to specify colour output. Note that some printers do not support this mode.
  • Labcenter Plotter Driver? - If this option is checked then ISIS only relies on the plotter driver’s ability to draw a line on the plotter with ISIS linearising arcs, circles, etc. and rendering text in a vector font. If this option is not checked then ISIS treats the plotter driver just like any other driver and expects it to sensibly handle all Windows GDI calls. This option is only enabled when a plotter is selected as the output device.

What to Print

The options in this groupbox allow you to configure which areas of the design you wish to print. Note that the print preview is disabled when printing all sheets.

  • Marked Area - Export the marked area as set by the Set Area command on the File Menu. This option is only enabled where there a marked area and there is no maximised graph.
  • Current Graph - Export the currently maximised graph. This option is only enabled where a graph has been maximised. To maximise a graph either select the graph title from the bottom of the Graph menu or click left once on the graph's title bar.
  • Current Sheet - Export the currently displayed sheet. This option is only enabled where there is no maximised graph.
  • All Sheets - Export all sheets, including root sheets and hierarchical sub-sheets. This option is only enabled where there is no maximised graph. Note that no print preview is available with this option and the sheets will position with origin at the centre of the printable area. For more control over sheet position select the ‘Current sheet’ option and print for every sheet individually.

Copies

Specify the number of copies you want for the current print job. Note that if your printer does not support multiple copies this field will be disabled.

Scale

These options allow you to specify the appropriate scaling factor for your output area. The print preview will display the output area at the current scaling. Note that the Scale to Fit option will, by default, only shrink a large design down to fit the paper size. To enlarge a small design to fit you must first uncheck the Only Shrink to Fit option.

Only Shrink to Fit? - This checkbox is only enabled when the ‘Scale to Fit’ option is selected. When checked the output area will, if necessary, shrink to fit within the printable area. It will not however, expand a smaller area to the bounds of the printable area. When unchecked designs can be both shrunk and expanded to the printable area.

Page Orientation

These options specify whether the document should be printed with its top along the short side of the paper (Portrait) or along the long side of the paper (Landscape). The print preview will automatically update to provide a visual representation of the specified orientation.

Compensation Factors

The compensation parameters scale the absolute co-ordinates of the graphic leaving the relative size(s) unaffected. For example, if you have a line of length 10 units drawn at co-ordinates (5, 5) and you set the x-compensation = 0.6 and the y-compensation = 0.5, then the line would actually be outputed at co-ordinates (3, 2). The length (10 units) remains unaffected. The purpose of these parameters is therefore to allow dimensionally critical designs to be of sufficient accuracy.

Print to File?

Specify whether or not you want to save the print job to disk.

Advanced Options

These options allow you to override the information that your printer supplies to ISIS and should only be used when the information supplied is incorrect. We advise you to use these options with caution – for example, enabling colour options on a printer which does not support colour output is pointless and will achieve nothing.


Block Rotate/Reflect

Overview

This dialogue form allows you to rotate highlighted items by a specific angle and mirror the highlighted items in the x or y axes.

Options

Angle

Choose the angle at which you wish the selected items to be rotated by.

Mirror X

Check this box if you wish the selected items to be mirrored in the x axis

Mirror Y

Check this box if you wish the selected items to be mirrored in the y axis


Edit Box/Circle/Path Graphics

Overview

This dialogue allows you to make local changes to one or more graphics styles on the schematic. Global changes (for future designs) should be made via the Template menu.

Options

Global Style

Specify the global graphics style on which to base the appearance of the wire. Individual aspects of the wire’s appearance can be adjusted by unchecking the Follow Global checkboxes.

Lock controls to global style's current settings?

When checked this will disable any controls on the dialogue whose settings are meaningless as a result of the Global Style Settings.

Line Attributes

  • Line Style - Specify a local change to the Line Style. This is enabled only when the appropriate Follow Global? Checkbox is unchecked and any changes made are specific to the current wire.
  • Width - Specify a local change to the Line Width. This is enabled only when the appropriate Follow Global? Checkbox is unchecked and any changes made are specific to the current wire.
  • Colour - Specify a local change to the Line Colour. This is enabled only when the appropriate Follow Global? Checkbox is unchecked and any changes made are specific to the current wire.
  • Follow Global? - When checked the Line Style/Width/Colour will follow the global style as set in the Template Menu.

Sample

This displays a sample of the graphic reflecting any changes you have effected through the options given.

Fill Attributes

  • Fill Style - Specify which type of fill style you wish to use.
  • Fg Colour - Specify the colour of the graphic.
  • Use Bk. Colour For particular graphic types only, this option allows you to use a background colour.
  • Bk. Colour - If enabled, this option allows you to choose which background colour to use.
  • Follow Global? - These checkboxes determine whether the graphic(s) being edited should use the default style properties (as defined via the Template Menu) or should be overriden for the current graphics.


Current Probe

Overview

This dialogue allows you to configure current probe objects that are connected to wires on the schematic.

Options

Name

Enter the name of the probe here. Once you have manually changed the name of a probe, ISIS will never replace it, even if you move the probe to a new net. If you want a probe to revert to automatic naming, clear its name to the blank string and then click OK.

Record to File

When checked the output data will be recorded to a partition data file.

Filename

Specify the filename and path for the output data, and which details you want to be visible on the schematic.


Edit Line/Beizer Graphics

Edit Line/Bezier Graphics

Overview

This dialogue allows you to make local changes to one or more graphics styles on the schematic. Global changes (for future designs) should be made via the Template menu.

Options

Global Style

Specify the global graphics style on which to base the appearance of the wire. Individual aspects of the wire’s appearance can be adjusted by unchecking the Follow Global checkboxes.

  • Lock controls to global style's current settings? - When checked this will disable any controls on the dialogue whose settings are meaningless as a result of the Global Style Settings.

Line Attributes

  • Line Style - Specify a local change to the Line Style. This is enabled only when the appropriate Follow Global? Checkbox is unchecked and any changes made are specific to the current wire.
  • Width - Specify a local change to the Line Width. This is enabled only when the appropriate Follow Global? Checkbox is unchecked and any changes made are specific to the current wire.
  • Colour - Specify a local change to the Line Colour. This is enabled only when the appropriate Follow Global? Checkbox is unchecked and any changes made are specific to the current wire.
  • Follow Global? - When checked the Line Style/Width/Colour will follow the global style as set in the Template Menu.

Sample

This displays a sample of the graphic reflecting any changes you have effected through the options given.

Fill Attributes (Bezier Graphics Only)

  • Fill Style - Specify which type of fill style you wish to use.
  • Fg Colour - Specify the colour of the graphic.
  • Use Bk. Colour For particular graphic types only, this option allows you to use a background colour.
  • Bk. Colour - If enabled, this option allows you to choose which background colour to use.
  • Follow Global? - These checkboxes determine whether the graphic(s) being edited should use the default style properties (as defined via the Template Menu) or should be overriden for the current graphics.


Edit Pin

Overview

This dialogue allows configuration of all pin properties.

Options

Pin Name

Specify the pin name. If the device uses a pinout, this must match the pin name that appears in it.

Default Pin Number

Specify the pin number. If the device uses a pinout, or if the pin is a bus pin, this field should be left blank.

Draw Body?

If checked, the pin stem will be drawn along with the name and number as defined by the Draw name and Draw number checkboxes. If not checked then the pin is deemed hidden and will not be drawn at all.

Draw Name?

If checked (along with the Draw body checkbox), the pin name will be drawn at the position defined in the pin's symbol by the Pinname marker.

Draw Number?

If checked (along with the Draw body checkbox), the pin number will be drawn at the position defined in the pin's symbol by the Pinnum marker.

Rotate Pin Name?

This option, when checked, will rotate the pin name. This can be convenient where space is at a premium in some components.

Rotate Pin Number?

This option, when checked, will rotate the pin number as displayed on the schematic.

Electrical Type

Specify the electrical type of the pin. This is used by the electrical rules checker, and also by the PROSPICE simulation software.


Edit Subcircuit

Overview

This dialogue allows you to provide basic information about the sub-circuit.

Options

Name

The object name for the sub-circuit. If a flattened netlist is produced, this is taken as the sheet name for the child sheet. If the hierarchy is not flattened, then this field is used as the part name for the 'component' represented by the sub-circuit. This field must be different for each sub-circuit on a given sheet.

Circuit

The name of the child circuit to attach. This will be assigned automatically if you zoom into a sub-circuit for which this field is blank. On the other hand, if you want to attach several sub-circuits to the same child-circuit, you should enter the circuit name in this field. For example, if you are designing a stereo amplifier and want two sub-circuits named LEFT and RIGHT to use the same circuit for an amplifier channel, you might edit each one to have the circuit AMP.

Properties

Sub-circuits carry a property list in the same way that ordinary components do. When the design is flattened, these properties become sheet property definitions which may be used in parameterized expressions on the child sheet. It thus becomes possible to have different instances of a given circuit use different component values.


Edit Tape Recorder

Name

Specify the name of the tape. You can change the name of a tape by typing in a new name into the name field. Once you have manually changed the name of a tape, ISIS will never replace it, even if you move the tape to a new net. Should you wish to revert back to automatic naming clear the name field and then click OK.

Properties

Include any additional properties or modify existing properties here. Text in curly brackets { } will be hidden. The contents of this text block will be dependant on the type of generator used.

Mode

Specify whether the tape operates automatically, records to a named file, or plays a named file.

Filename

Specify the data file used for the Play and Record modes.


Edit Text

Overview

This dialogue allows you to configure a single line text entry. Note that this is different from a script block which is a multi-line text entry on the schematic. All changes to styles made here are local to the current text line; global changes should be made via the Template Menu.

Options

String

Enter a text string here.

Justification

These checkboxes allow you to define the required justification for the text.

Graphic's Style

  • Global Style - Specify which global Graphics style you want the text to be formatted in. Previews are shown in the Sample window.
  • Line Width - The width of line used to draw text when drawn in a vector font face. This field is disabled when either a TrueType™ font face is selected (for which a line width is meaningless) or where the Follow Global? checkbox is checked (which indicates the line width is to taken from the global style selected in the Global Style selector).
  • Colour - Specify a local ( object-specific ) colour. This is only enabled when the Follow Global? checkbox is unchecked.
  • Follow Global? - If checked, the associated style attribute is initialised from the global style indicated in the Global Style selector. Unchecking the Follow Global? checkbox enables the dialogue control for the associated style attribute allowing you to specify a local (object-specific) value for that attribute.

Font Attributes

  • Font Face - Specify the name of the font face the text is to be displayed in. The drop down list lists all the TrueType™ fonts available on the machine as well as two special fonts: Default Font and Vector Font.
  • Height - Specify the height of the text. You can use whatever standard units you like, such at th for thou (thousandths of an inch) or mm for millimetres.
  • Width - Specify the width of a character in the text. This field is only enabled for text to be drawn in the internal Vector Font (either explicitly or by selecting the Default Font where the default font has been set to be the Vector Font.)
  • Bold? - Select Bold Text.
  • Italic? - Select Italic Text.
  • Underline? - Select Underlined Text.
  • Strikeout? - Select text with a strikeout.

Sample

Displays a sample of text drawn with the current style settings.


Voltage Probe

Overview

Voltage probes can be used to capture voltage data on a wire and display on a graph or to halt the simulation when a particular voltage condition is reached (hardware breakpoint). To record data on a graph you must apply the voltage probe to the wire of interest and then seperately add it to the graph.

Options

Probe Name

Enter the name of the probe here. Once you have manually changed the name of a probe, ISIS will never replace it, even if you move the probe to a new net. If you want a probe to revert to automatic naming, clear its name to the blank string and then click OK.

Resistive Loading

  • Load to Ground? - Specify whether you want to define a resistance to ground from the voltage probe. Use this where the probe is connected to a point which does not have a DC path to ground.
  • Load - Enter a value for the resistance from the probe to the ground net, and specify which, if any, properties of the probe you want to be visible on the schematic.

Waveform Recording

  • Record to File? - When checked the output data will be recorded to a partition data file. If you do not specifiy a path, the file will be stored in the RESULTS directory.
  • Filename - Specify the filename and path for the output data, and which details you want to be visible on the schematic.

Real Time Breakpoint

  • Trigger Value - Specify the value at which you wish to halt the simulation. If digital, this amounts to 0 for logic low and 1 for logic high whilst in the analogue domain you simply enter the desired voltage.
  • Arm at Time - It is often useful to disable the condition until a particular point in time (e.g. after initialisation logic). The arm time represents the time at which the breakpoint becomes active.

Isolate After?

When checked a voltage probe placed in the middle of a wire acts to 'break' the wire to which it is connected, isolating the circuitry to which the probe connects from the circuitry after it.


Generator Properties

Overview

This dialogue allows configuration of all generator properties. The dialogue form is dynamic and will show/hide properties according to the type of generator selected.

Options

Generator Name

Specify a name for the generator. Once you have manually changed the name of a generator, ISIS will never replace it, even if you move the generator to a new net. If you want a generator to revert to automatic naming, clear its name to the blank string and then click OK.

Analogue Types

DC

This is used to generate a constant DC voltage or current Level.

Sine

This is used to produce continuous sinusoidal waves at a fixed frequency.

The output level is specified as a peak amplitude (VA) with optional DC offset (VO). The amplitude may also be specified in term of RMS or peak-peak values.

The frequency of oscillation can be given in Hz (FREQ), or as a period (PER), or in terms of the number of cycles over the entire graph.

A phase shift can be specified in either degrees (PHASE) or as a time delay (TD). In the latter case, oscillation does not start until the specified time.

Exponential decay of the waveform after the start of oscillations is specified by the damping factor, THETA.

Mathematically, the output is given by:

for t >= TD. For t < TD the output is simply the offset voltage, VO.

Pulse

This is used to produce a variety of repetitive input signals for analogue analysis. Square, saw-tooth and triangular waveforms can be produced, as well as single short pulses. Note that the rise and fall times cannot be zero and so a truly square wave is not allowed. This is because instantaneous changes in general are not allowed in PROSPICE. The operation of the pulse generator is best described by the following diagram:

where

§. PER - The period of the waveform. If none is specified, then FREQ is used instead.FREQ The frequency of the waveform. This defaults to one period for a transient analysis.

§. V1 - The low-level value of the output.

§. V2 - The high-level of the output.

§. PW - The time for which the output is at V2 in each cycle. This does not include TR and TF.

§. TR - The rise time - time taken between LOW and HIGH in each cycle. This defaults to 1ns.

§. TF - The fall time - time taken between HIGH and LOW in each cycle. This defaults to TR.

§. TD - The delay time. The output of the generator starts at V1, and will remain at this level for TD seconds.

Pwlin

This is used to produce analogue signals which are too complicated for a pulse generator, or to reproduce a measured waveform. The output waveform is described using pairs of values for time and output magnitude. The output of the generator at intermediate times is linearly interpolated between the given times.

If you have tabular data, you may find it easier to use manual edit mode. In this case, each data point is specified by a property of the form V(t). The following example shows how this works.

V(0)=0

V(2n)=0

V(3n)=1

V(5n)=1

V(6n)=0

If you have a large amount of data, you may find it easier to use a FILE generator instead.

File

This is used to drive a circuit from an analogue signal that is specified by a series of time points and data values contained in an ASCII file. The ASCII file should be formatted with one time/voltage pair on each line seperated by white space (spaces or tabs , not commas ). The time values must be in ascending order and all values must be simple floating point numbers ( no suffixes allowed ).

Example

The following example data file produces three cycles of a saw-tooth waveform with rise time 0.9ms, fall time 0.1ms and amplitude 1V.

0 0

9E-4 1

1E-3 0

1.9E-3 1

2E-3 0

2.9E-3 1

3E-3 0

Audio

This is used to drive a circuit from a Windows WAV file. In conjunction with Audio Graphs they make it possible to hear the results of processing a sound signal through a simulated circuit.

Exponent

This produces the waveform as an RC circuit under charging and discharging conditions. . The parameters are best described by the diagram below.

where the parameters are

§. V1 - The low-level value of the output.

§. V2 - The high-level of the output.

§. TD1 - The start time of the rise curve.

§. TAU1 - The time constant of the rise curve. This is the time for the voltage to reach approximately 0.63 of its full potential.

§. TD2 - The start time of the fall curve. Note that TD2 is measured from zero.

§. TAU1 - The time constant of the fall curve.

Mathematically, the waveform is defined in three sections:

0 to TD1

TD1 to TD2

TD2 to TSTOP

SFFM

This produces a waveform that represents the result of frequency modulating one sine-wave with another. Mathematically, this is represented as:

where the parameters are

§. VO - The DC offset voltage.

§. VA - The carrier amplitude.

§. FC - The carrier frequency.

§. FS - The signal frequency.

§. MDI - The modulation index.

Random

This enables the injection of random noise into the circuit. The noise can never be rigorously white or pink because the sample rate is limited. But if the sample rate is around 10x the frequencies you're interested in it's a pretty good approximation.

Filter Output: When this option is selected an LPF is engaged, making the noise approximately pink, rather than white. Also a more continuous waveform.

Random Seed: If this checkbox is off, each generator gets it's own seed so they are all different but repeatable between simulation runs.

The Mayday sample design under graph based simulation shows how the random generator can be used.

EasyHDL

EasyHDL is a scriptable generator type based loosely on the BASIC programming language but adds additional features specific for its application in specifying test vectors. It is discussed in full in the topic on Scriptable Generators in the main simulation help file and you'll find a series of examples under the 'Generator Scripts' category in the samples browser.

Digital Types

  • Single Edge - a single transition from low to high or high to low.
  • Single Pulse - a pair of transitions in opposite directions which together form a positive or negative pulse waveform. You can specify either the times of each edge (start time and stop time) or the start time and the pulse width.
  • Clock - a continuous pulse train of even mark-space ratio. You can specify the starting value and the time of the first edge as well as the period or frequency. The period specifies the time for a whole cycle, not the width of a single mark or space.
  • Pattern - This is the most flexible and can, in fact, generate any of the other types. For larger pulse trains consider using the pattern generator instrument which can be scripted.
  • Easy HDL - Use the EasyHDL programming language to specify a signal chain for injection. See the programming reference manual in the VSM Help file for more information.

Checkboxes

  • Current Source? - Specify a current source. This is not applicable to digital generators.
  • Isolate Before? - Specify whether or not a generator placed in the middle of a wire acts to 'break' the wire to which it is connected, isolating the net to which the generator points from the net behind it. The check box has no affect on a generator connected directly to a net by a single wire.
  • Manual Edits? - Enables manual editing of all the properties. Use this to enter parameterized expressions for generator properties. Recommended for advanced users only.
  • Hide Properties? - Hides the textual representations of the properties.

DC Properties

  • Voltage - Specify the constant output level. This can be either a Voltage (default) or a current (select the 'Current Source?' radio button).

Sine Properties

  • Offset - Specify the DC offset for the sine wave.
  • Amplitude - Specify the amplitude as a half-wave value
  • Peak - Specify the amplitude as a peak to peak value.
  • RMS - Specify the amplitude as a RMS (Root Mean Squared ) value.
  • Frequency - Specify the frequency of oscillation in Hz.
  • Period - Express the frequency of oscillation as a period in seconds.
  • Cycles/Graph - Express the frequency of oscillation in terms of the number of cycles over the entire graph.
  • Time Delay - Express the phase shift as a time delay in seconds. Oscillation does not start until the specified time.
  • Phase - Specify a phase shift in degrees.
  • Damping Factor - Specify the rate of exponential decay of the waveform after the start of oscillation.

Pulse Properties

  • Initial (Low) Voltage - Specify the low level value of the output
  • Pulsed (High) Voltage - Specify the high-level value of the output
  • Start - Specify the start time for the waveform
  • Rise Time - Specify the time taken between LOW and HIGH in each cycle. This is not permitted to be zero and so a truly square wave is not possible.
  • Fall Time - Specify the time taken between HIGH and LOW in each cycle. This is not allowed to be zero and so a truly square wave is not possible. This defaults to the value for Rise Time.
  • Pulse Width (Secs) - Specify the time for which the output is HIGH in each cycle. This does not include Rise Time and Fall Time. This value can be zero if a triangle type waveform is required.
  • Pulse Width (%) - Specify the time for which the output is HIGH as a percentage of the period. This does not include Rise Time and Fall Time.
  • Frequency - Specify the frequency of the waveform in Hz.
  • Period - Specify the period of the waveform in seconds.
  • Cycles/Graph - Specify how many waveform cycles you want in the graph

Pwlin Properties

  • Time/Voltages - Drag and Drop Data Points on the Graph Editor. There must always be a point at time zero, although it' y-value an be changed.
  • X Min Scaling - Specify the minimum value for the x-axis.
  • X Max Scaling - Specify the maximum value for the x-axis.
  • Y Min Scaling - Specify the minimum value for the y-axis.
  • Y Max Scaling - Specify the maximum value for the y-axis.
  • Minimum rise/fall time - Specify the minimum rise/fall time. Should you attempt to create a vertical edge the Graph Editor will separate the two data points by this value.

File Properties

  • Data File - Enter the name of the ASCII data file. The file should be in the same directory as the design file unless a full path is specified. There is no default extension for the file.

Audio Properties

  • WAV Audio File - Selects the filename of the audio file.The filename is assumed to have a default extension of WAV, and should be located in the same directory as the ISIS design file (DSN extension) unless a full path is specified
  • Amplitude - Specify amplitude as a half-wave value.
  • Peak - Specify amplitude as a peak-to-peak value.
  • Offset - Specifies the DC offset. If this is set to zero the output voltage will oscillate about zero.
  • Channel - For stereo WAV files this specifies which channel is played, or whether to treat the data as mono.

Exponent Properties

  • Initial (Low) Voltage - Specify the low-level value of the output.
  • Pulsed (High) Voltage - Specify the high-level value of the output.
  • Rise Start time - Specify the start time of the rise curve in seconds.
  • Fall Start time - Specify the start time of the fall curve in seconds. Note that this time is measured from zero.
  • Rise time constant - Specify the time constant for the rise curve. This is the time for the voltage to reach approximately 0.63 of it's full potential.
  • Fall time constant - Specify the time constant of the fall curve.

SFFM Properties

  • Offset - Specify the DC offset of the waveform.
  • Amplitude - Specify the carrier amplitude.
  • Carrier Frequency - Specify the carrier frequency in Hz.
  • Modulation Index - Specify the modulation index for the wave.
  • Signal Frequency - Specify the signal frequency in Hz.

Easy HDL Properties

  • Assigned Script - Specify the script to be executed by the generator. Normally this is the local script (<LOCAL>) but it is possible to have other script blocks on the schematic.
  • Local Script - Type the script you wish to execute (assuming assigned script is set to <LOCAL>) - refer to VSM help for the programming reference manual and some practical examples.
  • Debug this Generator? - Select this option if you wish to single step debug the script during simulation. This will present a source window when the simulation is paused allowing you to debug in the normal way.

Steady State Properties

Specify a State from those listed. The states are organised in a centred array decreasing in strength from Power Rail High To Floating and from Power Rail Low to Floating.

Single Edge Properties

  • Positive (Low-to-High) Edge - Specify a positive edge transition.
  • Negative (High-to-Low) Edge - Specify a negative edge transition.
  • Edge At - Specify the time in seconds at which the edge is to begin.

Single Pulse Properties

  • Pulse Polarity - Select the required polarity of the pulse.
  • Start Time - Enter the time in seconds at which you want the pulse to start.
  • Pulse Width - Specify the ovarall pulse width in seconds.
  • Stop Time - Specify the time in seconds at which you want the pulse to stop.

Clock Properties

  • Clock Type - Select the required polarity of clock phase.
  • First Edge At - Specifies the time in seconds at which the first clock edge occurs. Prior to this time the generator stays in its initial state as specified by the clock type.
  • Frequency - Specifies the clock frequency in Hz.
  • Period - Specify the clock period in seconds. The period specifies the time for a whole cycle, not the width of a single mark or space.

Pattern Properties

  • Initial State - This specifies the value at time zero. It is also the value used when finding the operating point in a mixed mode circuit.
  • First Edge At - Specifies the time in seconds when the pattern output starts. The output will remain at the initial state value until this time is reached.
  • Equal Mark/Space Timing? - Indicates whether or not each step of the pattern will take the same time or have a different time for high and low values.
  • Pulse Width - If each step takes the same time (specified by checking the Equal Mark/Space Timing? checkbox ) this determines the pulse width. If there are different times specified for high and low values this determines the time for logic '1' values.
  • 'Space' time - When there are different times for high and low values (specified by unchecking the Equal Mark/Space Timing? checkbox) this value determines the time for logic ' 0 ' values.
  • Continuous Sequence of Pulses - Specifies that the output will run continuously until the end of the simulation, repeating the pattern as many times as are necessary.
  • Determine from Pattern Length - Specifies that the output will run until the end of the pattern. This option can only be selected when a specific pulse train is entered.
  • Specific Number of Edges - Specifies that the pattern is only to run for a specific number of edges.
  • Standard High-Low Pulse Train - This indicates an alternating high-low-high-low sequence.
  • Specific Pulse Train - Specifies that a specified pattern string is to be enabled. Enables the edit box below and permits the option of running the output until the end of the pattern.


Edit Wire Label

Overview

This dialogue allows you to specify a wire label. Common uses for wire labels include naming e a bus tap, naming a net and applying a net class to the net (CLASS=xxx). The latter is particularly useful when laying out the PCB as you can apply design rules and trace/via styles on a net class basis.

Options

String

Specify the script text. This field can be manipulated using the standard windows shortcut keys for cutting copying and pasting.

Auto-sync?

When checked this will ensure that all wire labels on the net carry the same text at all times.

Rotate

Specify whether the text is oriented horizontally or vertically.

Justify

Selects whether the text is left, centre or right justified, and whether it its origin is at the top or bottom.


Edit Wire Label Style

Options

Global Style

Select a Global Style from the drop down list. Local changes (i.e. changes persistent only in the existing design ) can be made to the selected Global Style by unchecking the appropriate Follow Global? Checkbox.

Fontface

You can change the type of font used for this particulat script by unchecking the Follow Global? Checkbox and selecting a font face from the drop down list. A preview of your selection will become visible in the Sample viewscreen.

Height

You can change the height of the specified font by unchecking the corresponding Follow Global? checkbox and entering the required value. All changes will be local to the current label.

Width

Where appropriate the font width can be changed by unchecking the corresponding Follow Global? chackbox adnd entering the required value. This option is not available for TrueType™ Fonts.

Effects

When the appropriate Follow Global checkflag is unchecked local changes can be made to the font style by checking or unchecking this option.

Colour

Change the colour of the script text to one of the alternative colours shown. This option is only available when the corresponding Follow Global? checkflag is unchecked,

Sample

Displays a visual representation of the text style currently specified.


Add Trace

Overview

This dialogue allows you to add one or more traces to a graph and to use multiple traces to form a trace expression (e.g. Power) which can then be plotted on the graph.

Options

Name

Enter the name of the trace to be added to the graph.

Probe P1

Select a probe or generator from the list box to be assigned to the selected trace probe. The Selected Probe name (P1 through P4) will appear in the Expression field if it is not already present.

Probe P2 - P4

Select a probe or generator from the list box to be assigned to the selected trace probe. The Selected Probe name (P1 through P4) will appear in the Expression field if it is not already present. This is only enabled if a trace expression is permitted.

Expression

Enter the trace expression in the Expression field. Within the expression, the selected probes should be represented by the names P1, P2, P3 and P4 which correspond to the probes selected alongside the P1, P2, P3 and P4 buttons respectively. If the trace type selected does not support a trace expression the contents of the Expression field will be ignored.

Trace Type

Select the type of trace you wish to add to the graph by checking the appropriate button. Only those trace types applicable to the graph are enabled.

Axis

Select the y-axis to which the new trace is to be added. Only those axes applicable to the graph and trace type selected are enabled.


Batch Mode Conformance Analysis

Overview

This dialogue form enables you to automatically run a set of designs which contain conformance graphs. Each design is simulated and the conformance results analysed and presented in a textual report at the end of the process.

For more information on conformance testing and conformance graphs please refer to the VSM Help under Analysis Types.

Options

Root Path

Specify the root directory where the designs containing the conformance graphs are stored.

Recurse Subdirectories?

Run the batch processing through not only the specified directory above but also through any subdirectories inside the root directory.

Stop on Error?

Stop the batch processing if a conformance error is detected.

Log Detailed File Information ?

This option enables detailed reporting of conformance results and provides more information on completion than the standard output.


Graph Colour Configuration

Overview

This dialogue form allows you to customise the graph to be colours of your choice.

Options

General Appearance

Use these options for general configuration. Each option has its own context sensitive help topic.

  • Graph Outline - Specify the colour used for borders and dividing lines on the graph.
  • Background - Specify the background colour used to fill the main part of the graph.
  • Graph Title - Specify the background colour used to fill the title bar.
  • Graph Text - Specify the colour used for text used to label and mark the graph axes. Trace labels always appear in the same colour as the trace.
  • Tagged/Highlight - Specify the colour used to highlight the graph or individual trace when it is tagged.

Analogue Traces

Specify the colour(s) by which you want to identify the various analogue traces.

Digital Traces

Specify the colour(s) by which you want to identify the Digital Traces on the graph.


Edit AC Sweep Graph

Overview

This type of analysis creates a family of frequency response curves for a different values of a swept variable.

The main use for this graph type is in seeing how a particular component value affects the frequency response of your circuit.

Options

Graph Title

Specify the title that appears along the top of the graph. By default, this is set to the type of analysis determined by the graph's type.

Reference

Specify a generator to use as the source of the test signal.

Start Frequency

Specify the frequency the simulation will start at. This must be greater than 0, and less than the stop frequency.

Stop Frequency

Specify the frequency the simulation will cease at.

Interval

Specify whether the number of steps is per decade, per octave or is linearly spaced across the whole plot.

No. Steps/Interval

Specify the number of steps per the selected interval. For the linear interval this is the number of points plotted across the whole x-axis.

Sweep Var

Specify the name of the variable that is to be swept. This defaults to X, but any variable name may be used, including control properties like TEMP.

Start Value

Specify the initial value of the swept variable. This may be a negative value.

Stop Value

Specify the final value of the swept variable. This may be negative, but must be greater than the start value, as negative going sweeps are not allowed.

Nom Value

Specify the value for the sweep variable to use when computing the operating point.

No. Steps

Specify the number of steps that PROSPICE will take in incrementing the swept variable.

User Defined Properties

The Properties free-format text field allows you to define Simulation Control Properties that will be fed to the simulator engine when the graph is simulated. Recommended only for advanced users. You can also use this field to define values that appear in component property expressions. This technique is particularly useful if you wish to create several graphs showing the effect of changing one or more component values.

Options

  • Y-scale in dBs? - If checked, the left y- axis displays the magnitude in dBs.
  • Always Simulate? - When checked this forces a graph to perform a simulation regardless of whether or not the partition or partitions on which the simulation depends has changed.
  • Log Netlist(s) - When checked this causes the simulation netlist generated by ISIS and fed to the simulator engines to be placed in the graph's simulation log.
  • SPICE Options - Pressing this button activates a dialogue form that enables you to adjust global simulator options that are common to all types of analysis.
  • Set Y-scales - This option allows you to manually configure the ranges for the Y-axes of the graph. Note that you must have performed an initial simulation before manually setting or locking the Y-Axis of the graph.


Edit Audio Analysis Graph

Overview

PROTEUS VSM incorporates a number of features that enable you to hear the output from your circuits (providing you have a sound card, of course!). The major component of this is the Audio graph. This is essentially the same as an Analogue graph except that after simulation, a Windows WAV file is generated from the time domain data and played through your sound card.

The WAV files can also be exported for use in other applications.

Options

Graph Title

Specify the title that appears along the top of the graph. By default, this is set to the type of analysis determined by the graph's type.

Start Time

Specify the start of the time period that will be used to generate the WAV file.

Stop Time

Specify the end of the time period that will be played. Bear in mind that asking PROSPICE to generate several seconds of audio containing several thousand cycles of a waveform will take a considerable amount of time.

Play Mode

Specify a play mode from one of the following options:

  • MONO - Generates a WAV file from the aggregate of all the traces on the graph.
  • STEREO - Generates a stereo WAV file routing the left hand traces to the left channel and the right hand traces to the right channel.
  • INPUT - Generates a mono WAV file from the aggregate of the left hand traces. The right hand traces are merely displayed.
  • OUTPUT - Generates a mono WAV file from the aggregate of the right hand traces. The left hand traces are merely displayed.

Loop Time

To avoid the need for PROSPICE to simulate hundreds or thousands of cycles of a waveform, it is possible to generate a WAV file of several seconds in length by repeating one cycle many times. The Loop Time setting determines the desired length of the WAV file, and the interval from Start Time to Stop Time will be copied as many times as are needed to achieve this.

Sample Bits

Specify the number of bits per sample for the WAV file. 8 bit gives about 48dB dynamic range and 16 bit gives 96dB.

Sample Rate

Specify the number of samples per second for the WAV file. Remember that the maximum frequency that can be played back is half the sample rate. Also, at present there are no fancy pre-filtering algorithms implemented and so aliasing effects will be heard if the sample rate is too low.

Lock Timestep?

This option locks PROSPICE’s internal timestep to the desired sample rate. This can result in much quicker (albeit slightly less accurate) simulations and reduced partition file sizes - useful if you are processing several seconds of audio as file sizes can otherwise quite easily exceed 10Mb.

User Defined Properties

The Properties free-format text field allows you to define Simulation Control Properties that will be fed to the simulator engine when the graph is simulated. Recommended only for advanced users. You can also use this field to define values that appear in component property expressions. This technique is particularly useful if you wish to create several graphs showing the effect of changing one or more component values.

Options

  • Initial DC Solution - Specify that at time = 0 all capacitors, inductors etc. are at steady states. If this is unchecked then when the simulation starts all inductors will be defluxed and all capacitors will be discharged.
  • Always Simulate - When checked this forces a graph to perform a simulation regardless of whether or not the partition or partitions on which the simulation depends has changed.
  • Log Netlist(s) - When checked this causes the simulation netlist generated by ISIS and fed to the simulator engines to be placed in the graph's simulation log.
  • SPICE Options - Pressing this button activates a dialogue form that enables you to adjust global simulator options that are common to all types of analysis.
  • Set Y-scales - This option allows you to manually configure the ranges for the Y-axes of the graph. Note that you must have performed an initial simulation before manually setting or locking the Y-Axis of the graph.

Audio

Play Audio - This option allows you to play stored audio data through your computers sound card.

Export as WAV file - This option allows you to export the currently graphed data as a WAV file. You can then optionally import this into another design using the audio generator.


Edit DC Sweep Graph

Overview

With a DC Sweep analysis you can see how changing a circuit will affect its operation. This is achieved using Property Expression Evaluation in the PROSPICE simulator engine. The sweep graph defines a variable that can be swept in even steps over a user-defined range. The sweep variable can appear in any property within the circuit, such as a resistor value, a transistor gain or even the circuit temperature.

A DC Sweep curve shows the steady state voltage (or current) levels of the probed points around the circuit, as the swept variable is increased. It can be used to plot the DC transfer characteristic of a circuit by assigning the swept variable to a generator value, as well as plotting the effect of changing component values on the operating point of the circuit.

Options

Graph Title

Specify the title that appears along the top of the graph. By default, this is set to the type of analysis determined by the graph's type.

Sweep Variable

Specify the name of the variable that is to be swept. This defaults to X, but any variable name may be used, including control properties like TEMP.

Start Value

Specify the initial value of the swept variable. This may be a negative value.

Stop Value

Specify the final value of the swept variable. This may be negative, but must be greater than the start value, as negative going sweeps are not allowed.

Nominal Value

Specify the value for the sweep variable to use when computing the operating point.

No. Steps

Specify the number of steps PROSPICE will take in incrementing the swept variable.

Left Axis Label

Specify the left y-axis label.

Right Axis Label

Specify the right y-axis label.

User Defined Properties

The Properties free-format text field allows you to define Simulation Control Properties that will be fed to the simulator engine when the graph is simulated. Recommended only for advanced users. You can also use this field to define values that appear in component property expressions. This technique is particularly useful if you wish to create several graphs showing the effect of changing one or more component values.

Options

  • Always Simulate? - When checked this forces a graph to perform a simulation regardless of whether or not the partition or partitions on which the simulation depends has changed.
  • Log Netlist(s)? - When checked this causes the simulation netlist generated by ISIS and fed to the simulator engines to be placed in the graph's simulation log.
  • SPICE Options - Pressing this button activates a dialogue form that enables you to adjust global simulator options that are common to all types of analysis.
  • Set Y-scales - This option allows you to manually configure the ranges for the Y-axes of the graph. Note that you must have performed an initial simulation before manually setting or locking the Y-Axis of the graph.


Edit Distortion Graph

Overview

Distortion analysis determines the level of distortion harmonics produced by the circuit under test. These can be either the 2nd and 3rd harmonics of a single fundamental or the intermodulation products of two test signals.

Distortion is created by non-linearities in a circuit’s transfer function - a circuit comprising linear components only (resistors, capacitors, inductors, linear controlled sources) will not produce any distortion. SPICE distortion analysis models distortion for diodes, bipolar transistors, JFETs and MOSFETs.

Options

Graph Title

Specify the title that appears along the top of the graph. By default, this is set to the type of analysis determined by the graph's type.

Reference

Specify a generator to use as the source of the test signal.

IM ratio

Specify the value for F2/F1 in intermodulation analysis. If this value is zero then harmonic distortion analysis is performed. When choosing a value for F2/F1 you should generally specify a value that is an irrational number, or at least a fraction with as large as possible a denominator. Note that F2/F1 must be less than unity. i.e. F2/F1 < 1.

Start Frequency

Specify the minimum test frequency for F1

Stop Frequency

Specify the maximum test frequency for F1.

Interval

Specify whether the number of steps is per decade, per octave or is linearly spaced across the whole plot.

No. Steps/Interval

Specify the number of steps per the selected interval. For the linear interval this is the number of points plotted across the whole x-axis.

User Defined Properties

The Properties free-format text field allows you to define Simulation Control Properties that will be fed to the simulator engine when the graph is simulated. Recommended only for advanced users. You can also use this field to define values that appear in component property expressions. This technique is particularly useful if you wish to create several graphs showing the effect of changing one or more component values.

Options

  • Y-scale in dBs - If checked, the left y-axis will display the magnitude of harmonics in dBs relative to an IV fundamental.
  • Always Simulate - When checked this forces a graph to perform a simulation regardless of whether or not the partition or partitions on which the simulation depends has changed.
  • Log Netlist(s) - When checked this causes the simulation netlist generated by ISIS and fed to the simulator engines to be placed in the graph's simulation log.
  • SPICE Options - Pressing this button activates a dialogue form that enables you to adjust global simulator options that are common to all types of analysis.
  • Set Y-scales - This option allows you to manually configure the ranges for the Y-axes of the graph. Note that you must have performed an initial simulation before manually setting or locking the Y-Axis of the graph.


Edit Fourier Analysis Graph

Overview

Fourier Analysis is the process of transforming time domain data into to the frequency domain and the result is similar to that obtained by connecting up a spectrum analyser instead of an oscilloscope. It is especially useful in analysing the harmonic content of signals, perhaps to look for particular types of distortion but has many other uses also.

Options

Graph Title

Specify the title that appears along the top of the graph. By default, this is set to the type of analysis determined by the graph's type.

Start Time

Specify the start of the time period that will be analysed.

Stop time

Specify the end of the time period that will be analysed. If the input signal is periodic, you should ensure that the interval defined by the start and stop times is exactly one or more cycles.

Max Frequency

Specify the highest frequency that will be displayed. (half the sampling rate).

Resolution

Specify the interval between the frequency points that will be analysed. This is analogous to the spacing of the bands on a graphic equaliser. The lower the number, the more bands and the slower the calculations. If the input signal is periodic, you should choose a resolution that corresponds with the fundamental frequency, or a sub-multiple of it. Sub-multiples which are powers of 2 (e.g. ½, ¼, etc) work best.

Window

Specify a window type to apply to the time data. Use the windowing options if you appear to be getting spurious peaks in the frequency data.

Left Axis Label

Specify the left y-axis label.

Right Axis Label

Specify the right axis label.

User Defined Properties

The Properties free-format text field allows you to define Simulation Control Properties that will be fed to the simulator engine when the graph is simulated. Recommended only for advanced users. You can also use this field to define values that appear in component property expressions. This technique is particularly useful if you wish to create several graphs showing the effect of changing one or more component values.

Options

  • Y-scale in dBs - If checked, the left y-axis displays the magnitude in dBs.
  • Initial DC Solution - Specify that at time = 0 all capacitors, inductors etc. are at steady states. If this is unchecked then when the simulation starts all inductors will be defluxed and all capacitors will be discharged.
  • Always Simulate? - When checked this forces a graph to perform a simulation regardless of whether or not the partition or partitions on which the simulation depends has changed.
  • Log Netlist(s)? - When checked this causes the simulation netlist generated by ISIS and fed to the simulator engines to be placed in the graph's simulation log.
  • SPICE Options - Pressing this button activates a dialogue form that enables you to adjust global simulator options that are common to all types of analysis.
  • Set Y-Scales - This option allows you to manually configure the ranges for the Y-axes of the graph. Note that you must have performed an initial simulation before manually setting or locking the Y-Axis of the graph.


Edit Frequency Graph

Overview

With Frequency Analysis you can see how the circuit behaves at different frequencies. Only one frequency is considered at a time, so the plots are not like those seen on a spectrum analyser, where all frequencies are considered together. Instead, the simulation is similar in effect to connecting a frequency generator to the input, and looking at the output with an AC voltmeter. As well as the magnitude, however, the phase of the probed signal can also be seen.

Frequency analysis produces frequency response or Bode plots. It is useful in checking that filters are behaving as expected, or that amplifier stages will work correctly across the required frequency range.

Frequency graphs can also be used to plot small signal input and output impedance against frequency.

Options

Graph Title

Specify the title that appears along the top of the graph. By default, this is set to the type of analysis determined by the graph's type.

Reference

Specify the generator used as the input source.

Start Frequency

Specify the frequency at which the simulation will start. This must be greater than zero and less than the stop frequency.

Stop Frequency

Specify the frequency at which the simulation is to stop.

Interval

Specify whether the number of steps is per decade, per octave or is linearly spaced across the whole plot.

No. Steps/Interval

Specify the number of steps per the selected interval. For the linear interval this is the number of points plotted across the whole x-axis.

User Defined Properties

The Properties free-format text field allows you to define Simulation Control Properties that will be fed to the simulator engine when the graph is simulated. Recommended only for advanced users. You can also use this field to define values that appear in component property expressions. This technique is particularly useful if you wish to create several graphs showing the effect of changing one or more component values.

Options

  • Y-scale in dBs - If checked the left y-axis will display the magnitude in dBs.
  • Always Simulate - When checked this forces a graph to perform a simulation regardless of whether or not the partition or partitions on which the simulation depends has changed.
  • Log Netlist(s) - When checked this causes the simulation netlist generated by ISIS and fed to the simulator engine to be placed in the graph's simulation log.
  • SPICE Options - Pressing this button activates a dialogue form that enables you to adjust global simulator options that are common to all types of analysis.
  • Set Y-scales - This option allows you to manually configure the ranges for the Y-axes of the graph. Note that you must have performed an initial simulation before manually setting or locking the Y-Axis of the graph.


Edit Graph DSIM

Simulation Options - DSIM

Options

Random Initialization Values

  • Fully Random Values - Specifies that the initialization values for each model in the design with a scaleable timing value will be completely random both on the initial simulation and through repeat simulations.
  • Pseudo-Random values based on seed - Specifies that the random numbers generated are dependant on a seed value. This, in effect, means that while all capable models receive random values ( which are dependant on the value of the seed that you specify ) they will receive those same values on repeat simulations. This is particularly useful for isolating errors in the simulation.

Propagation Delay Scaling

  • Scale all values by constant amount - When this option is checked all propogation delays for models in DSIM will be scaled by the amount specified. For example, a high to low edge propogation delay of 10ns will actually take 20ns if this setting is selected and a value of 2 is specified.
  • Pseudo-random scaling based on seed - When this option is checked propagation delays are randomized within the bounds specified according to seed. The fact that the randomization is seeded ensures that the ordering is constant and so subsequent simulation runs will produce the same ‘random’ values as the initial simulation.
  • Fully Random Scaling - Selects an option from those given to indicate how you would like DSIM to handle propagation delay in the models on the design. See the context sensitive help on each edit field for more information. The Upper and Lower Scaling Limits fields specify the limits for random propogation delays and ensure that random delays have sensible boundaries.


Edit Graph Iteration

Simulation Options - Iteration

Integration Method

Specifies an integration method (can be either Gear or Trapezoidal).

Trapezoidal Integration is provided mainly for backward compatibility with previous versions of SPICE since Gear integration generally gives more accurate results for a given number of time-steps.

In Gear integration, higher orders than 2 are possible; this involves SPICE using more of the past history of a time-point in predicting what happens at the next time-point.

Maximum Integration Order

Specifies the maximum level of integration for a particular integration method. This is limited to an order of 2 for the Trapezoidal Method but higher orders are permitted for the Gear Method.

Number of Source Steps

Specifies the number of steps you want in SPICE’s Source Stepping mode. This is an approach utilied by SPICE when it fails to find convergence at the operating point. All power supplies in the circuit are started at zero and are ramped up to their proper values in a number of steps as determined by this parameter.

Number of GMIN Steps

Specifies the number of steps you want in SPICE’s GMIN Stepping mode. This is an approach utilized by SPICE when it fails to find convergence at the operating point. The GMIN parameter is increasingly reduced until convergence occurs, and then ramped back to its proper value. The number of attempts is determined by this parameter.

DC Iteration Limit

Specifies the maximum number of iterations that will be tried at the operating point.

DC transfer curve iteration limit

Specifies the maximum number of iterations that will be tried at a step in a Transfer Curve Analysis.

Upper Transient Iteration Limit

Specifies the maximum number of iterations that will be tried at a time point in a Transient Analysis.

Go directly to GMIN stepping?

Specifies whether or not you want SPICE to directly adopt the GMIN Stepping mode. SPICE uses this mode when it fails to find convergence at the operating point.

Try compaction for LTRA lines?

Specifies whether or not you want LTRA compaction performed on the simulation. This applies only for circuits incorporating lossy transmission lines (LOSSYLINE model). The idea is that near identical values in the data pipeline get discarded so that this data points are processed.

Allow bypass on unchanging elements?

Specifies whether or not you want to bypass unchanging elements in the simulation. This is a general optimization that saves SPICE from re-computing the values of semiconductor devices whose node voltages have not changed since the last evaluation.


Edit Graph MOSFET

Simulation Options - MOSFET

Options

MOS drain diffusion area

Specifies the default drain diffusion area for MOSFET models.

This is intended to be used in IC modelling where it is useful to specify the model parameters in terms of physical dimensions.

MOS source diffusion area

Specifies the default source diffusion area for MOSFET models.

This is intended to be used in IC modelling where it is useful to specify the model parameters in terms of physical dimensions.

MOS Channel Length

Specifies the default channel length for MOSFET models.

This is intended to be used in IC modelling where it is useful to specify the model parameters in terms of physical dimensions.

MOS Channel Width

Specifies the default channel Width for MOSFET models.

This is intended to be used in IC modelling where it is useful to specify the model parameters in terms of physical dimensions.

Use older MOS3 Model?

Activates 'bug emulation' for certain MOSFET models which were developed for earlier release of SPICE 3.

Use SPICE2 MOSFET Limiting?

Actives 'old style' Kappa limiting for MOSFET models that were developed for SPICE 2.


Edit Graph Tolerances

Simulation Options - Tolerances

Options

Absolute Current Error Tolerance

Specifies the absolute current error tolerance of the program. This is the amount by which successive current values must match before convergence is achieved.

Absolute Voltage Error Tolerance

Specifies the absolute voltage error tolerance of the program. This is the amount by which successive voltage values must match before convergence is achieved.

Charge Error Tolerance

Specifies the charge error tolerance for the program. This is the amount by which successive charge values must match before convergence is achieved.

Relative Error Tolerance

Specifies the relative error tolerance for the program. This is the threshold of relative change in current, voltage or charge values that must be attained for convergence.

Minimum acceptable pivot value

Specifies the absolute minimum value for a matrix entry to be accepted as a pivot in solving the circuit equations.

Minimum acceptable ratio of pivot

Specifies the relative ratio between the largest column entry and an acceptable pivot value in solving the circuit equations.

Minimum Conductance

Specifies the minimum conductance allowed by the program. This value defines the leakage of reverse biased semiconductor junctions and other theoretical points of infinite impedance. Reducing this value may help achieve convergence for circuits that fail to simulate - although this may be at the expense of simulation accuracy. Values greater than 1E-9 will give very dubious results.

Minimum Transient Conductance

This is a Labcenter specific convergence optimisation which provides a dynamic way of increasing GMIN to improve convergence during transient analysis.

Shunt Resistance

This is the resistance to ground from all nodes in the circuit.


Edit Graph Temperature

Simulation Options - Temperature

Options

Operating Temperature

Specifies the operating temperature. This is the actual temperature of the circuit.

Parameter measurement temperature

Specifies the parameter measurement temperature. This is the value at which temperature dependent device parameters are taken to have been measured.


Edit Graph Transient

Options

Number of Steps

Specifies the minimum number of steps in the simulation, or - to be precise - the maximum timestep as a fraction of the overall analysis run time. Use this property to force PROSPICE to produce a more detailed analysis if the results are suffering from jitter, or if the simulation appears to be skipping over rapid switching activity.

You can also specify the maximum allowed timestep directly by entering TMAX as a graph property.

E.g. TMAX=1u

Any TMAX property will override NUMSTEPS

Truncation Error over-estimation factor

Specifies the transient error tolerance. This parameter is an estimate of the factor by which SPICE overestimates the actual truncation error. If you have results that appear overly spiky, or suffer from overshoots you should try a lower value here. However, entering a low value will result in SPICE having to perform more simulation timesteps.

Mixed Mode Timing tolerance

Specifies the accuracy with which the analogue and digital sides of a mixed mode simulation are synchronized. This parameter affects the operation of the ADC and DAC interface objects. For totally accurate simulation of DAC rise and fall waveforms TTOL must be set smaller than the rise and fall times, but for most purposes these waveforms are irrelevant and setting a larger TTOL makes for substantially faster simulations.

Minimum Analogue Timestep

Specifies the minimum allowed timestep for the SPICE simulation. If at any point during the simulation, the timestep is reduced below this value as a result of convergence errors, the simulation will fail with the "Timestep too small" error. The default value is adequate for most purposes.


Edit Noise Graph

Overview

The SPICE simulator engine can model the thermal noise generated in resistors and semiconductor devices. The individual contributions of noise are summed together at a voltage probe in the circuit for a range of frequencies. The noise voltage, normalised with respect to the square root of the noise bandwidth, can then be plotted against frequency. Traces on a noise graph always have units of V/ÖHz.

Two types of noise figure are computed - Output Noise and Equivalent Input Noise. The computation of the latter enables comparison of the noise with the input signal, or input noise, since it represents the level of noise at the input that would be required to create the actually noise at the output taking into account the circuit gain at a particular frequency.

Placing a probe on the left axis displays output noise, whilst equivalent input noise can be displayed by dragging the probe onto the right axis.

Noise analysis tends to produce extremely small values (of the order of nanovolts). For this reason, there is the option to display them in dBs. The 0dB reference is 1V/ÖHz.

Options

Title

Specify the title that appears along the top of the graph. By default, this is set to the type of analysis determined by the graph's type.

Reference

The generator used as the input source – this defines the point for which Equivalent Input Noise is computed.

Start Frequency

The noise bandwidth frequency at which the simulation will start.

Stop Frequency

The noise bandwidth frequency at which the simulation will end.

Interval

Specify whether the number of steps is per decade, per octave or is linearly spaced across the whole plot.

No. Steps/Interval

Specify the number of steps per the selected interval. For the linear interval this is the number of points plotted across the whole x-axis.

User Defined Properties

The Properties free-format text field allows you to define Simulation Control Properties that will be fed to the simulator engine when the graph is simulated. Recommended only for advanced users. You can also use this field to define values that appear in component property expressions. This technique is particularly useful if you wish to create several graphs showing the effect of changing one or more component values.

Options

  • Y-scale in dBs - If checked the left y-axis will display the magnitude in dBs.
  • Log total contributions - If checked, the total noise contribution (summed from all spot frequencies) from each component in the design is recorded in the simulation log.
  • Log Spectral Contributions - If checked, the noise contribution from each component at each spot frequency is recorded in the simulation log. This can generate a very large amount of data.
  • Always Simulate - When checked this forces a graph to perform a simulation regardless of whether or not the partition or partitions on which the simulation depends has changed.
  • Log Netlist(s) - When checked this causes the simulation netlist generated by ISIS and fed to the simulator engines to be placed in the graph's simulation log.
  • SPICE Options - Pressing this button activates a dialogue form that enables you to adjust global simulator options that are common to all types of analysis.
  • Set Y-Scales - This option allows you to manually configure the ranges for the Y-axes of the graph. Note that you must have performed an initial simulation before manually setting or locking the Y-Axis of the graph.


Edit Transient/Conformance Graph

Overview

This graph type represents what you might expect to see on an oscilloscope. The x-axis shows the advance of time, whilst the y-axis displays voltage or current. We often refer to this type of analysis as Transient Analysis because it takes place in the time domain.

Transient analysis is perhaps the most commonly used form of analysis. Everything that you would measure with an oscilloscope on a real prototype can be measured on an analogue graph. It can be used to check that the circuit operates in the expected manner, to take quick measurements of gain, to assess visually the way in which a signal is distorted, to measure the current flowing from the supply or through individual components, and so on.

Options

Graph Title

Specify the title that appears along the top of the graph. By default, this is set to the type of analysis determined by the graph's type.

Start Time

Specify the nominal time from which simulation results will be displayed.

Stop Time

Specify the time the simulation is to cease at. Times such as 100u will be correctly interpreted by ISIS as 100ms. The right end of the graph time axis is set by this field.

Left Axis Label

Specify the frequency at which the simulation is to stop.

Right Axis Label

Specify the right y-axis label.

Options

  • Initial DC Solution - Specify that at time = 0 all capacitors, inductors etc. are at steady states. If this is unchecked then when the simulation starts all inductors will be defluxed and all capacitors will be discharged.
  • Always Simulate - This check box forces a graph to perform a simulation regardless of whether or not the partition or partitions on which the simulation depends have changed.
  • Log Netlist(s) - This check box causes the simulation netlist generated by ISIS and fed to the simulator engines to be placed in the graph's simulation log.
  • Spice Options - Pressing this button activates a dialogue form that enables you to adjust global simulator options that are common to all types of analysis.
  • Set Y-scales - This option allows you to manually configure the ranges for the Y-axes of the graph. Note that you must have performed an initial simulation before manually setting or locking the Y-Axis of the graph.

User Defined Properties

The Properties free-format text field allows you to define Simulation Control Properties that will be fed to the simulator engine when the graph is simulated. Recommended only for advanced users. You can also use this field to define values that appear in component property expressions. This technique is particularly useful if you wish to create several graphs showing the effect of changing one or more component values.

Verification

Use these options to either store a known good set of results or to clear the stored results. Subsequent to storing a set of results any future simulation on this graph will be analysed for conformance against these results (according to the control trace edges).


Edit Transfer Function Graph

Overview

This graph type is specifically designed for producing characteristic curve families for semiconductor devices, although it occasionally finds other applications. Each curve consists of a plot of operating point voltage or current against the value of a nominated input generator which is swept from one DC value to another. An additional generator may also be stepped to produce a set of curves.

Options

Graph Title

Specify the title that appears along the top of the graph. By default, this is set to the type of analysis determined by the graph's type.

Source 1

Specify the name of the first generator to sweep.

  • Start Value - Specify the initial value for the first generator.
  • Stop Value - Specify the final value for the first generator.
  • No. Steps - Specify the number of steps PROSPICE will take in incrementing the first generator. This translates into the number of points on a curve.

Source 2

Specify the name of the second generator to sweep.

  • Start Value - Specify the initial value for the second generator.
  • Stop Value - Specify the final value for the second generator.
  • No. Steps - Specify the number of steps PROSPICE will take in incrementing the second generator. This will determine the number of curves in the simulation.

Left Axis

Specify the left axis label.

Right Axis

Specify the right axis label.

User Defined Properties

The Properties free-format text field allows you to define Simulation Control Properties that will be fed to the simulator engine when the graph is simulated. Recommended only for advanced users. You can also use this field to define values that appear in component property expressions. This technique is particularly useful if you wish to create several graphs showing the effect of changing one or more component values.

Options

  • Always Simulate? - When checked this forces a graph to perform a simulation regardless of whether or not the partition or partitions on which the simulation depends has changed.
  • Log Netlists? - When checked this causes the simulation netlist generated by ISIS and fed to the simulator engine to be placed in the graph's simulation log.
  • SPICE options - Pressing this button activates a dialogue form that enables you to adjust global simulator options that are common to all types of analysis.
  • Set Y-scales - This option allows you to manually configure the ranges for the Y-axes of the graph. Note that you must have performed an initial simulation before manually setting or locking the Y-Axis of the graph.


Set Animation Options

Overview

This dialogue allows you to configure various simulation parameters for use in interactive/animated simulation.

Options

Simulation Speed

Use these options to configure simulation speed. Each option has its own context sensitive help associated with it.

  • Frames per second - Specify how many animation frames are shown every second. The range for this option is 1 to 50. The lower the value the slower the animation will run. The higher the value the faster the animation will run. On Windows 95/98 there is no benefit in setting it higher than 20.
  • Timestep per frame - Specify by how much the simulation times advances for each frame. It follows that if you change the frame rate, you must also change the timestep per frame if you wish to maintain real time simulation. Alternatively, you can set a smaller timestep per frame if you wish to slow down the rate of progress of the simulation. This value represents the desired timestep which will only be achieved if there is sufficient CPU power for the speed of operation and complexity of the circuit.
  • Single Step Time - This is used in conjunction with the STEP button and determines the time advanced for each single step. In logic circuits it is often useful to set this to half of the clock period so that the effect of each clock transition can be observed.
  • Max SPICE Timestep - This setting clamps the simulation to a maximum timestep. The higher this value the faster the simulation at the expense of accuracy.
  • Step Animation Rate - This is the rate at which the automatic single step debugging will progress. At default value 4, the system will step over four instructions per second when automated stepping is enabled.

Animation Options

Use these options to configure general animation options. for interactive simulation. Each option has its own context sensitive help associated with it.

  • Show Voltage and Current on Probes? - When checked this option will enable a small live readout of voltage / current beside a probe on the schematic during animation where the readout is determined by the type of probe used on the schematic.
  • Show Logic state of pins? - If checked, then coloured blobs are drawn next to the pins of all logic devices in order to indicate their logic state. This option imposes an extra but modest computational burden on the simulator.
  • Show wire voltage by colour? - If checked, then the voltage of analog nets is displayed by colouring the wires. The scaling for this is determined by the value given in the Maximum Voltage field, above.
  • Show wire current with arrows? - If checked, then current flow within wires on analog nets is displayed using small arrows. An arrow is drawn for any current flow greater or equal to the value given in the Current Threshold field, above. This option can impose a major computational burden on the simulator, because each wire is replaced by a 1mÙ resistor, thus substantially increasing the number of components and circuit nodes. In digital simulation, the presence of the resistors causes a doubling of the number of events to be processed.
  • SPICE options - This button launches the SPICE simulation options dialogue, allowing advanced users to further configure simulation tolerances etc.

Voltage/Current Ranges

Use these options to configure voltage and current ranges for interactive simulation. Each option has its own context sensitive help associated with it.

  • Maximum Voltage - Specify the scaling for the active wire colours. You would normally set it to the highest voltage occurring in your circuit.
  • Current Threshold - Specify the minimum value of current flow within a wire for which an arrow will be displayed. Occasionally it may be useful (for educational clarity) to increase this value so that the circuit behavior will appear idealized, not withstanding the use of real world models. For example, you may wish to have an op-amp appear to draw no input current when in fact a given SPICE model may draw a few microamps from its inputs.


Set Y-Axis Scaling

Overview

This dialogue allows you to specify a Y-Axis scaling for the current graph once a data set has been stored on the graph.

Options

Left Axis

The options within this groupbox allow you to manually specify the Y-Axis range for the left hand Y-Axis. Note that these options are only enabled for applicable graph types and after the graph has already been simulated.

Right Axis

The options within this groupbox allow you to manually specify the Y-Axis range for the right hand Y-Axis. Note that these options are only enabled for applicable graph types, where the right hand Y-axis has traces on it, and after the graph has already been simulated.


Graph Size Configuration

Overview

This dialogue form allows you what size you would like the graph to be printed out as from A4 to A0 paper sizes, or you can create your own custom size using the User field.


bsdl_import

Overview

This topic outlines the basic procedure for importing a BSDL file into Proteus.

More detailed information and guidance can be found via the HELP button at the bottom of the dialogue form or in the Library Facilities chapter of the reference manual.

Basic Procedure

  • Check whether the pins in the pin grid need re-ordering or re-naming. They will appear on the schematic in the same order as they appear in the pin grid.
  • Decide whether you want your power pins and/or NC pins to be visible or hidden. If hidden, power pins will connect automatically to the net whereas if visible you will need to tie them to a power terminal with the correct net name. Similarly, if you make the NC pins visible you need to place and connect NC terminals to each pin. This is discussed more in the help topic in the reference manual.
  • Check whether you need to split the part into several elements and add component separators in appropriate places. If you are using visible power and NC pins it's useful to split them off into their own elements.
  • Check whether blank line separators would help with clarity (for example, on either side of a bus) and add where appropriate.
  • Specify the direction of pin placement.
  • Continue to part naming, packaging, etc in the usual way.


Autoplace Library

Overview

This dialogue form allows you to select the library from which you wish the components to be autoplaced.

Options

Show Properties

Causes all properties of the components to be made visible so that you can more easily inspect them.


Compile Placed Components to Device Library

Overview

This dialogue form allows you to specify which Device Library you want to store the component in.

Options

Process all sheets in the design?

When checked all sheets containing parts of the selected component will be compiled to the specified library.

Hide Component Properties?

When checked the component properties will be hidden.

Hide Pin Numbers?

When checked the component pin numbers will be hidden.


Component Properties & Definitions

Default Property Definitions

Overview

This screen allows you to specify additional properties for the component. All properties added here can then be configured to be output in the bill of materials report (System Menu - Set BOM Scripts) or may be relevant to a simulation model if you have created your own model for a component.

You can directly create, manage and remove properties in the Bill of Materials module within a grid view.

See Also:

BOM Reference Manual - Properties

BOM Reference Manual - Examples

Options

Left Pane

This combo-box displays the names of the property definitions. The property definitions on the right pertain to the highlighted property.

  • New - Specify a new property. Holding down this button will give you a list of existing default property definitions from which you can select and modify as required.
  • Delete - Delete an existing property.

Property Definition

  • Name - Specify the name of the property. This can be typed in or selected from a list of property definitions.
  • Description - Document the meaning of the property in full English. This is especially useful for model parameters. If the field is left blank, the property name will be used as a description.
  • Type - Select a data type from the list given. Integer and floating point types enable range limitation fields on the dialogue form.
  • Initial Directory - Enter the initial directory for the File Dialog to open.
  • File Description - Enter a description of the file type that is to be opened.
  • Extension - Enter the file extension for the type of file that you wish to open.
  • Type - Specify how the property is to be displayed and edited.

§. Normal - The property is displayed in its own field on the Edit Component dialogue and can be edited in the normal way.

§. Read only - The property is displayed in it’s own field in the Edit Component dialogue but cannot be edited.

§. Advanced - The property appears in the list of advanced properties on the Edit Component dialogue. To edit it, the user must select the property using the Advanced Properties combobox, and then edit the value in the associated data fields. This option is useful for simulator primitives or models that have large numbers of relatively obscure properties.

§. Hidden - The property does not normally appear on the Edit Component dialogue and can only be edited by selecting the Edit All Properties as Text option.

Property Defaults

  • Default Value - Specify a default value for the property. All instances of the component placed on the schematic will be initialised with this property value.
  • Visibility - Specify which parts of the property definition you want displayed when a component is placed.

Use Default Property Definitions when editing Components?

When checked Proteus will use the default property definitions when they do not exist in a component part. When you define a new property via System Menu -Set property definitions dialogue you are creating a default property definition. Let's assume you did this for Minimum Order Quantity (MoQ) and you define to be a integer greater than 100.

Next you edit a component and type MOQ=150. If this checkbox is selected you will see that when you re-enter the dialogue form the entered string is automatically formatted and part of the Edit Component dialogue form.

We recommend that you leave this option selected unless you are certain that you understand the consequences of removing it.


Device Datasheet & Help File

Overview

This screen allows you to associate a datasheet and a help file with the component. When configured a data and help button will appear on the edit component dialogue form.

Options

Datasheet

Use these options to link a manufacturers datasheet to the library part. You can specify a path to an HTTP or FTP site. Each field has its own context sensitive help associated with it.

  • Filename - Specify the filename of a manufacturer's datasheet for the component. If none of the other fields are filled in, the data sheet is assumed to be available from the Labcenter download site. Otherwise, you can fill in the other fields to specify an alternative location for the file. The extension (usually PDF) is required, and the filename may be case sensitive for some download sites. If you specify a filename in this field, then ISIS will add a Data button to the Edit Component dialogue form.
  • Download Server - Specify the HTTP or FTP site on which the datasheet file may be found. E.g. http://downloads.labcenter.co.uk or ftp://ftp.microchip.com If you leave this field blank, the datasheet will have to be manually downloaded and put in the datasheets directory within the installation directory.
  • Download Path - Specify the path (directory) in which the datasheet is located on the HTTP or FTP server. This field may be case sensitive for some download sites.
  • Download User ID - Specify the user id for the HTTP or FTP server login. Leave this field blank where authorization is not required.
  • Download Password - Specify the password for the HTTP or FTP server login. Leave this field blank where authorization is not required.

Help Topic

Use these options to link in a help project to your library part. These options tend to be used where you have a simulation model associated with the part and want to describe tolerances, properties and functionality for that model in the form of some help documentation. Each field has its own context sensitive help associated with it.

  • Help File - Specify the name of a Windows Help file which contains information about this component. This is provided mainly as a means for providing usage information about simulator models. If you specify a filename in this field, then ISIS will add a Help button to the Edit Component dialogue form. This facility is intended for use in documenting simulator models.
  • Context Number - Specify the help context ID containing information about the component. You should cross-reference this number to a help topic ID using the MAP section of the Windows Help project file.


Device Properties

Options

General Properties

Use these fields to specify the basic device information. Each field has it’s own context sensitive help associated with it.

  • Device Name - Specify the name for the new device.
  • Reference Prefix - Specify the Default prefix for newly placed components. If you blank out the prefix, then placed parts will initially have empty reference fields and their value and properties will be hidden. The reference prefix is also used to group like items together in the Bill of Materials report.
  • External Module - Specify the name of an external module file to attach to the component when it is placed. This allows you to define components which represent re-useable circuit elements. You can create an external module file by checking the External Mod File checkbox within the Edit Sheet Properties command. For an ordinary physical component you should leave this field blank.

Active Component Properties

If your library part has an associated Active Component interface then use these options to link in the Active Component Model. This will only be the case if you are either editing one of our Active Components (for example,the keypad model), or have created your own VSM model . If you are simply creating a library part for use within the Schematic Capture package or for linking to ARES PCB design then you can safely leave these options in there default states. Each option contains it’s own context sensitive help topic.

  • Symbol Name Stem - Specify the stem of the name for the model. The symbol names will consist of the name stem an underscore and an appended number.
  • No. of States - Specify the number of states for the model. In the standard case this is the number of symbols created for the model. However if Bitwise States? is checked then a separate symbol is required for both the on and off states and so the number of symbols required will be double the number of states.
  • Bitwise States? - Specify whether a symbol is required for both on and off states (Bitwise States ) or not. A bitwise active component has symbols names of the form STEM_N_0 and STEM_N_1 for each element of the component.
  • Link to DLL? - Specify whether or not the component model is to be linked to a VSM Model DLL.


Indexing and Library Section

Overview

The final stage of creating a device is to specify which library you wish to store the part in and to provide categories and search (index) terms to make it easy to pick the part into designs. Note that you should never store your own parts in to Labcenter libraries as these libraries are overwritten on installation of a new version (to enable library updates).

Options

Device Category

Specify which category you wish the device to be indexed under. If no appropriate category is available you can add one of your own via the New button on the right. Indexing your parts makes them far easier to find when browsing and rationalizes the libraries into logical groups.

Device Subcategory

Specify which subcategory you wish the device to be indexed under. If no appropriate category is available you can add one of your own via the New button on the right. Alternatively, if no subcategory is appropriate for your part you can select ‘None’ from the combo list. Indexing your parts makes them far easier to find when browsing and rationalizes the libraries into logical groups.

Device Manufacturer

Specify which manufacturer you wish the device to be indexed under. If no appropriate category is available you can add one of your own via the New button on the right. Alternatively, if no subcategory is appropriate for your part you can select ‘None’ from the combo list.

Stock/Order Code

You can optionally specify a stock code for the part for use in the Bill of Materials report.

Device Description

This field is used to enter the description for the library part you are creating. You can search by description when browsing for library parts and the description string is displayed in the results listview. Care should be taken therefore to enter a description using terminology that you would use to easily search for the part.

Advanced Mode - When selected this checkbox will place the dialogue in advanced mode. This allows you to, for example, enter a comma separated list of categories if you want your part to be listed in more than one category. However, due to the free format nature of the advanced mode, we recommend that this is only used by experienced users.

Device Notes

This field can be used for entering any additional information about the library part being created. For example, we may use this field to enter helpful model information for simulatable. If a component has notes added to it, they are then viewable via the ‘View Notes’ button on the Edit Component dialogue form (this button is dynamic and so does not appear for components with no notes).

Save Device to Library

This viewer displays a list of all read-write libraries contained in your library path(s). To select a library to place your part in, left click to highlight that library in the viewer. If the library into which you want to place the part does not appear in the list check the following :

That the library is writeable – only read-write libraries will appear in this list.

That the library is in a directory specified in your library path (see System – Set Paths). If you need to move a library you will have to close and restart ISIS for the library to be reloaded.


Packaging

Overview

This screen displays a list of existing packages for the device you are making. If you are creating a device for the first time this area will be empty . If you intend to netlist this device to ARES you should create a package for the device via the Add/Edit button directly below this field.

Options

Add/Edit

This command launches the Visual Packaging Tool allowing you to add packages to the device.


Make Symbol

Overview

This dialogue allows you to create your own graphics symbols for use in ISIS.

Options

Symbol Name

Enter the name by which the symbol is to be known.

Library

Select the library in which the symbol is to be stored.

Type

Select the appropriate symbol type from the options given.


Pick Devices/Symbol

Overview

This dialogue presents a search and selection system for bringing library parts into the current schematic.

Options

Keywords

Search for library part(s) by keyword. This method is ideal if you want one (or more) components of a specific type. Examples of possible searches include, ‘

NAND Gate’, ‘Line Driver’, ‘res 2k2’, ‘cap 22n’, ‘zener 4.7’ etc. Search results can then be refined by using the Category, Subcategory and Manufacturer fields below.

Alternatively, you can use keywords to refine a search in which you have already specified categories. For example, if you select the Diodes category and the Zener subcategory you could then refine the search by entering ‘4.7’ in the keywords field.

Keywords are matched in the following ways

  • Textual comparison - Each keyword is matched against the part name and part description on a ‘contains string’ basis, unless the Whole Word matching option is checked.
  • Part Name Digit matching - A keyword containing only digits will be matched against part names using just digits. This means that ‘8051’ will find ‘80C51’, and ‘1684’ will find ‘PIC16F84’.
  • Part Name Wildcards - A search for 74*373, 74??373, *373, 74LS373, will all yield the 74LS373 in the results.
  • Value matching - A keyword which will evaluate to a number will be compared numerically with any values in the part descriptions. So 1500 will match 1k5, and 220n will match 0.22u, for example.
  • Note that you can use the TAB key to move from the keywords field to the list of the results, the UP/DOWN arrow keys will navigate through the results, and the ENTER key will select the currently highlighted result into the schematic and exit the form.
  • Match Whole Words? - This option enforces a full word match on the description field. For example, a search for ‘OR Gate’ may yield a result for an ‘Open Collector AND Gate’ (the ‘or’ being contained within the word collector) but a whole word only search will eliminate such matches from the results list.
  • Show only parts with models? - This option is relevant if you are performing a simulation and wish to restrict search results to those with a simulation model.

Category

This field displays a list of categories according to the following rules:

  • If a keyword search has been entered then the category list will contain all categories containing results from the search. You can then select a category to refine your search.
  • If no keywords have been entered the category list displays all available categories. Selecting a category in this case will display all results for that category. Typically you would use this mode (together with the subcategory listbox) for non-specific browsing.

The Unspecified category contains all library parts for which no indexing information has been provided. For example, if you have created your own library parts and they have not been indexed they can be found by selecting this category.

Subcategory

This field displays a list of subcategories pertaining to the currently selected category. This works in one of two ways :

  • If you have entered a keyword search then the listbox will display all subcategories for the currently selected category where the subcategory contains results matching the textual search term entered.
  • If no keywords are entered the listbox will display all available sub-categories under the currently selected category.

In either case if no category is currently selected then the subcategory listbox will be empty.

Manufacturer

This field displays a list of manufacturers for the currently selected category and subcategory. The contents of this listbox are based on the following rules :

  • If a keyword search has been entered only those manufacturers containing results from the textual search and the currently selected category will be displayed.
  • If no keywords have been entered then all available manufacturers for the specified category will be displayed

Note that we have only provided manufacturer information for parts where it was deemed appropriate, usually as a result of an entire library originating from a single manufacturer.

Results

This is the main display window for search results. The names and textual description of parts matching the search criteria are displayed here - additional information can be added or removed from the display by clicking right to display a context menu.

To select a part(s) into your just design double-click on the part(s) within the results list.

The results can be ordered by column information by clicking on the column names at the top of the list view.

Schematic Preview

These fields display previews of the currently selected schematic part and its footprint. For parts packaged with more than one footprint the footprint preview can be changed via the footprint name selector at the bottom of the dialogue.

These previews will be blank until a part is selected within the results list.

PCB Preview

These fields display previews of the currently selected schematic part and its footprint. For parts packaged with more than one footprint the footprint preview can be changed via the footprint name selector at the bottom of the dialogue.

These previews will be blank until a part is selected within the results list.

Drop Down List

Where a schematic part has been packaged with multiple footprints this drop down list allows you to preview all the packages associated with the selected ISIS component. The package preview above displays the footprint for the currently selected package.


Package Device

Overview

This dialogue allows you to specify one or more packages to associate with the component. You can also specify hidden power pins and identify NC pins whilst the footprint preview gives you visual confirmation when all the pins on the schematic part are mapped onto the pads of the footprint.

Options

Packages

Lists all available packages. To change from one existing package to another click on the down arrow to the right of this field and select the desired package. If the package you want is not in this combo box you will have to create it via the add button located directly below this field.

  • Default Package? - By checking this box, you specify that the package currently selected in the packages combo box is to be used as the default package for this device. This in turn means that without intervention from yourself the component will use this package in future designs.
  • Add - Use this button to add a package to the component. Should the Use ARES Libraries checkbox be selected a package viewer will launch from which you can browse to the package that you want to add. If you are not using the ARES Libraries (for example,.if you are drawing the schematic to be exported to another PCB design package), then clicking this button will launch a dialog box where you can enter the name of the package you wish to associate with the library part. Note that in this case no validation of the package is possible.
  • Rename - This button allows you to rename the packaging currently specified in the packages combo box. Should the Use ARES Libraries checkbox be selected a package viewer will launch from which you can browse to the package with the name that you want to us. If you are not using the ARES Libraries (for example,.if you are drawing the schematic to be exported to another PCB design package), then clicking this button will launch a dialog box where you can manually rename the package you wish to associate with the library part. Note that in this case no validation of the package is possible.
  • Delete - This option allows you to delete the package currently selected in the packages combo box.
  • Order - This option allows you to re-order the existing packages to your preference and is disabled if you have only one package specified for the device currently being packaged.

No. of Gate

This field determines the number of pin-number columns that appear in the pin grid. For a multi-element heterogeneous part, it should represent the total number of elements. For most common devices (e.g. resistor, capacitor etc.) this field can be left in its default state (single element).

Gates can be swapped on the PCB Layout?

Selecting this checkbox will flag to ARES that the gate elements can be swapped.

Pin Selection Window

This is the engine of the Visual Packaging tool and where you assign pins on the schematic part to pads on the PCB footprint. Some points of note are listed below :

  • If you have a package preview on the right hand pane and you assign a pin number, the corresponding pad on the package will highlight in white. This means that when you have completely packaged the device all pads in the preview pane should be white
  • Again with the package preview you can set the focus in an elements pin field ( as if to type in the pin number) and then left click the mouse on the pad in the preview pane. This will assign the pin with the designation of the pad you have clicked on and move the focus to the next pin in the list. This can be a very fast and convenient way to manually package devices.
  • A number of options are available to you via the context menu (right click to access). These are mainly advanced features of the packaging tool but, properly used, can make large or multiple packages far simpler. See the help documentation for more details.

NC Pins

When packaging a large device, it may be useful to 'prove' that all the pins have been accounted for by verifying that all the pins are highlighted in the Package View. Since some pins may be specified as non-connected, it is useful to be able to record that they have been accounted for. This can be achieved by entering their numbers in the NC Pins field. Use commas to separate the pin numbers.

Add Pin - This option allows you to create a hidden pin that is specific to a given package, and is implicitly common to all its elements.

Remove Pin - This option allows you to remove a hidden pin that is specific to a given package,and as such has been created via the packaging tool.

Swappable Pins

The swappable pins section allows you to define groups of pins that are electrically interchangeable. For example, the two inputs A and B of a 7400 quad NAND gate are electrically identical can could be swapped on the PCB for convenience of wiring. You can add a swap-group to the list by highlighting the pins in the pin grid (hold the ctrl key down and click left on the pin names), and then clicking the Add button.

  • Add - This option allows you to add a group of swappable pins. Proceed by highlighting the pins in the pin grid (hold the CTRL key down and left click on each pin in turn), and then click this button to assign the highlighted pins as a swappable group.
  • Remove - This option allows you to remove a previously specified group of swappable pins. Simply highlight the group in the pinswap selector to the left and click on this control to remove the pins.
  • Replace - This option allows you to replace a previously specified group of swappable pins. Highlight the pins in the pin grid that you want to add (holding the CTRL key down to highlight multiple pins) and then use this button to replace the group currently selected in the pinswap selector with the group you have just specified.

Use ARES Libraries

This option, selected by default, allows both package viewing and package verification. You should only disable this checkbox if you are creating the schematic for netlist to a different PCB design package.

Assign Package(s)

Commit any changes in the dialogue options and exit.


Keyboard Mapping

Overview

This dialogue allows you to assign all commands in ARES to keyboard shortcuts of your choice.

Please note that the documentation refers to keyboard shortcuts in their default assignation.

Options

Command Groups

Use this selector to filter the command sets according to which command(s) you want to assign a keyboard shortcut for. All mappable commands are logically sorted into groups and each group is selectable from this combobox.

Available Commands

This view will list all commands available for mapping within the command set specified by the selector above. To specify a command for mapping left click once on the appropriate command (to highlight the command) and then click the mouse in the keyboard assignation box below.

Key Sequence for Selected Command

Specify the keyboard shortcut for the command highlighted in the above viewer. This field is disabled if no command is highlighted. More information on keyboard shortcuts can be found here.

  • Assign - Confirm that the specified keyboard shortcut is to be assigned to the highlighted command.
  • Unassign - This command will unbind the currently assigned keyboard shortcut (as displayed in the text to the right of the highlighted command) from the highlighted command.


Library Manager

Overview

This tool is used to manage your own user libraries, enabling you to create libraries and copy footprints between different libraries. It is important that you do not copy your own parts into the Labcenter system libraries as they will be overwritten on installation of a new version (to enable library updates). System libraries are read only by default to prevent this from happening.

Options

Source and Destination Libraries

The Source or Primary Library and the Destination or Secondary Library are the libraries used as the source and destination of objects in operations such as Copy, Delete, etc., and as the library for operations such as Pack Library, Delete Library, etc.

The Source or Primary Library is the library that last received the input focus; clicking on one of the two library list boxes causes that list box to become the Source (Primary) Library and the other list box to become the Destination (Secondary) Library. The text at the top of the list box indicates which list box is which, and the large black arrow between the two gives the sense of direction to the Copy and Move commands.

The library list boxes allow for multiple-selection of items: clicking the left mouse button on an item to select it, clicking on a selected item un-selects it.

The text at the top of a library list box indicates whether the specified library is read-only. Read-only libraries can only be used as a Source or Primary Library - you can still select a read-only library as a Destination (Secondary) Library, but the buttons that affect the library (e.g. Copy) will not be enabled. The text at the bottom of a library list box indicates the number of items in the library and the number of remaining entries in the library index.

Order

This button will launch a separate dialogue box which will allow you to specify the ordering of the available libraries.

Select All

This button is used to select all of the objects in the source library for copying moving or deleting.

Unselect All

This button is used to clear any objects that may have previously been highlighted for copying moving or deleting.

Copy Items

The Copy Items button copies the selected objects from the Source Library to the Destination Library. A percentage indicator on the right of the window indicates progress. The copy process stops once all the selected objects have been copied or when the destination library becomes full.

You can only copy objects to a writable (i.e. non read-only) Destination Library that is different to the Source Library

Move Items

The Move Items button moves the selected objects from the Source Library to the Destination Library. A percentage indicator on the right of the window indicates progress. The move operation is done in two stages: an object is first copied to the destination library and then it is deleted from the source library. The process stops once all the selected objects have been moved or when the destination library becomes full. Objects are only deleted from the source library after being successfully copied to the destination library - so if the destination library becomes full, those objects not yet moved are left in the source library.

You can only move objects from a writable (i.e. non read-only) Source Library to a writable Destination Library that is different to the Source Library.

Delete Items

The Delete Items button deletes all the selected objects in the Source Library. Note that deleted items cannot be recovered. You can only delete objects from a writable (i.e. non read-only) library.

Rename Item

The Rename Item button allows you to change the name of the last selected item in the Source Library. You can only rename objects in a writable (i.e. non read-only) library.

Information

Provides information about the current library and highlighted object, including date at which the object was last modified.

Dump Library

The Dump Library button displays a form containing the library information as well as the headers and properties for any selected library objects.

ADI Library

ASCII Data Import allows you to assign given properties to particular objects according to whether their existing properties match certain test conditions. In ISIS III ADI can be applied directly to libraries as well as design files. Selecting ADI Library asks for the name of an ADI file to apply to the selected components in the source library.

Backup Libraries

Create a backup copy of the source library.

Create Library

The Create Library button allows you to create a new library. You are prompted to enter the maximum number of objects the new library will be able to hold. These values cannot be changed after the library has been created and there is no (reasonable) limit to the values you enter. The new library is initialized empty and writable (that is, with its MS-DOS or network read-only file attribute not set).

Delete Library

The Delete Library button allows you to delete the current Source Library from disk. Note that you cannot undelete a deleted library! You can only delete a writable (i.e. non read-only) library.

Pack Library

The Pack Library button packs the current Source (Primary) Library. The existing library is renamed to a .BAK file. You can only pack a writable (i.e. non read-only) library.

File Attribute

Change the read/write status of the current library.


Position Printer Output Numerically

Overview

This dialogue form allows you to more accurately specify how you would like the output to be presented when printed by using numerical values.

Options

Top, Left, Right, Bottom

The textboxes allow you to numerically specify left, right, top and bottom margins. Note that if, for example, you enter a left margin, the right margin will be adjusted automatically according to the current paper size settings.

Buttons

The buttons will auto-position the output area at a preset position relative to the paper size (e.g. top left, bottom right, etc..).More information on printer output is provided within both the ISIS and ARES online documentation.

Metric Units?

Uncheck the metric checkbox to display all settings and values in imperial units. When checked all values are displayed in metric units.


Add/Remove Source Code Files

Overview

This dialogue is relevant to microprocessor simulation only and provides a user interface to specifying the source file(s) and compiler tools for creating the binary file on which the processor will run.

Note that it is perfectly possible to work inside your own IDE/Compiler environment and to then simply edit the processor component on the schematic and specify the file to be simulated directly.

Options

Target Processor

Specify the target processor on the schematic - since it is possible to simulate multi-core designs in Proteus you must identify the target for each source file.

Code Generation Tool

Use these options to specify or change the code generation tool to be used with the given source file. New Code Generation Tools can be specified from the Define Code Generation Tools command on the Source Menu.

Flags - Specify any arguments to be appended to the command line when applying the Code Generation Tool to the given Source File. These flags are applied just to the compilation of this source file.

Source Code Filename

Use these options to select or change a source code file

  • Change - Substitute the highlighted source file for a different source file.
  • New - Add a source file to the design.
  • Remove - Remove a source file from the design.


Add/Remove Code Generation Tools

Overview

This dialogue is relevant to microprocessor simulation and allows you to configure command line interfaces to your compiler/assembler such that Proteus can invoke them and build your projects.

Note that it is perfectly possible to work inside your own IDE/Compiler environment and to then simply edit the processor component on the schematic and specify the file to be simulated directly.

Options

Code Generation Tool

Use these options to specify or change the Code Generation Tool to be used for files in the current design.

  • Tool - Select a Code Generation Tool from the list. You can add to the list using the New Button at the bottom of the form.
  • Browse - Search your computer to find an appropriate Code Generation Tool. Both executable (EXE) and batch (BAT) files can be selected.
  • Path - Search your computer to find an appropriate Code Generation Tool. Both executable (EXE) and batch (BAT) files can be selected.

Make Rules

Use these options to specify specific Make Rules for the Code Generation tool currently listed above.

  • Source Extn - Specify the file extension for the Source file. For example, with an Assembler as the Code Generation Tool, the Source extension would normally be "ASM".
  • Obj Extn - Specify the file extension for the Object file. For example, with an Assembler as the Code Generation Tool, the object extension would normally be "HEX".
  • Always Build - When checked the project will always be compiled before the start of a simulation.
  • Command Line - Specify the arguments used on the command line to apply the Code Generation Tool to a source file. Substitute ‘%1’ for the source file and ‘%2’ for the object file.

Debug Data Extraction

Use these options to specify a Debug data Extraction (DDX) tool for the given tool. This is only necessary if you are using a supported assembler and should not be used if you are using a high level language tool.

  • List File Extn - Specify the extension of the list file generated from the Code Generation Tool. For example, with an assembler as the Code Generation Tool, the list file extension is normally "LST".
  • Browse - Browse for the location of the debug data extraction tool on your computer.

Other

  • Disable Automatic Build Rules - This option disables any automatic building selections that you have made and applies globally to all tools configured in this dialogue.
  • New - Specify a new Code Generation Tool.
  • Remove - Remove a Code Generation Tool.


Source Code Editor Configuration

Overview

This dialogue allows you to specify an editor for working with source files. Used in conjunction with the other dialogues on this menu you can write and compile your code using the Proteus environment.

Note that it is perfectly possible to work inside your own IDE/Compiler environment and to then simply edit the processor component on the schematic and specify the file to be simulated directly.

Options

Executable

Search your computer for an appropriate Source Code Editor.

DDE Interface

Use these options to specify a DDE interface for a text editor of your choice. Each option has its own context sensitive help topic.

  • Service Name - Specify the service name of the Source code Editor.
  • Open Command - Enter the command used by the Source Code Editor to open a file. Substitute ‘%1’ for the source file.
  • Save Command - Enter the command used by the Source Code Editor to save a file.


Set BOM Scripts

Overview

The Bill of Materials output is the primary report generated from the Proteus schematic module and details the parts used in the design. You can add arbitrary information to the BIll of Materials report by adding properties to components on the design and then adding the property name as a field in the Bill of Materials report. This dialogue form allows you to control which information (properties) are displayed in the output and also provides various formatting options.

The report itself is then generated from the output options at the top of the BOM module.

Bill of Materials Tutorial Movie (YouTube Channel)

Options

Scripts

Specify the Bill of Materials script that you want to use for your BOM Output. By default, three scripts are provided which you can customise as required. You can also create your own scripts tailored to your own requirements.

  • New - Create a new Bill of Materials script.
  • Rename - Rename the currently selected Bill of Materials script.
  • Delete - Delete the Bill of Materials script currently selected in the combo box to the left of this button (this operation cannot be undone). Note that you cannot delete the last script - ISIS requires that there is always at least one bill of materials script.

Bill of Materials Output Format

Specify the format of the Bill of Materials output. The following formats are available:

  • PDF Output - Formats your outputs as a PDF File. This is the most common format and enables presentation features such as colouring and company logos to be included.
  • ASCII Text - This plain text output is readable by notepad and any other common text editing application.
  • CSV (Compact) - This format is directly loadable into Microsoft Excel spreadsheet . Groups of components where all the specified columns are the same are grouped together.
  • CSV (Full) - This format is directly loadable into Microsoft Excel spreadsheet . Each part is output independantly regardless of similarities in the columns.

Categories

Displays a list of current catagories for the Bill of Materials. These catagories delineate the Bill of Materials, grouping the components in logical groups.

  • Add - Add a category to the current Bill of Materials Template.
  • Delete - Remove the currently selected category from the current Bill of Materials Template. This button is only enabled when a category is highlighted in the selector above the button.
  • Edit - Edit the category currently selected in the catagories selector. This button is only enabled when a category is highlighted in the selector above the button.
  • Order - Use this button to specify the order of the catagories currently in the selector.

Fields (Columns)

This selector displays the fields (or columns) to be used for each component in the Bill of Materials.

  • Add - Add a field (a column) to the selected Bill of Materials template. You can use this to add custom fields or simply to include information already provided by the components default properties.
  • Delete - Remove the currently selected field from the Bill of Materials. This button is only enabled when a field is highlighted in the selector above.
  • Edit - Edit the currently selected field. This button is only enabled when a field is highlighted in the selector above.
  • Order - Specify the order of the fields currently in the column selector.

Import/Export

These options provide mechanisms for copying, pasting, saving and loading BOM scripts and are intended to allow custom BOM scripts to be shared across machines.


Add BOM Category

Overview

In order to group similar parts together in the Bill of Materials output the system applies categories according to the reference prefix of the component. For example, all resistors have reference prefix 'R' and all capacitors have reference prefix 'C'. The reference prefix is set on the first tab of the Make Device dialogue form and you can therefore create additional categories of components if you choose.

This dialogue form allows you to add an additional category of components to the Bill of Materials output and optionally to specify several reference prefixes to associate with this category.

Options

Category Heading

Specify the heading you want for the category. This text should describe the type of components listed in the category.

Reference(s) to Match

Specify the reference prefixes you want to include this category. Each component on the schematic has a reference prefix (R for resistors, C for Capacitors etc.) which allows you to easily group types of component within a category.

Mark this category as the miscellaneous category?

Each template should have a miscellaneous category into which all component with a reference prefix not previously allocated can be placed. For example, if you create two catagories, one for capacitors (reference prefix C) and one for resistors (reference prefix R) then any component with a reference prefix other than C or R will be placed in the miscellaneous category.

Output separate References for each component?

When checked all references will be output individually. This means, for example, if you have 15 10k resistors you will get 15 rows, one for each resistor. When unchecked, you will get a single row indexed as R1-R15.


Add BOM Field

Overview

Each component has a base set of properties associated with it and users can add additional properties if required ( through the Make Device dialogue form, the property assignment tool or ASCII data import commands). In the Bill of Materials output each column or field is associated with a property and the value of the property for a given component populates that column in the resulting output. For example, you may wish to add properties for COST or RoHS to your components so that the bill of materials contains this information.

This dialogue allows you to add properties as fields in the report and provides configuration options for formatting and validation.

Options

Component Property Name

Specify the property to associate with the field being created/edited. The ‘list’ button allows you choose from a list of all the properties currently on the schematic.

Title for Column Heading

Specify the title for the column. This should be a textual description of the values which will be placed in the columns.

Property Validation

This combo box allows you to specify a degree of validation for the component property name specified above. This can help prevent errors or unintentional omissions in your final Bill of Materials.

Column Width

For ASCII output this value specify the number of characters that can be in the column. The column in clipped at the width of the column as specified by this value and any extra characters/text will be lost.

Prefix

This field allows you to add a prefix to the values for this field.(for example, a currency designator for monetary fields).

Suffix

This field allows you to add a suffix to the values for this field.(for example, a unit specification).

Apply Prefix/Suffix to blank (empty) values?

This checkbox determines whether the chosen prefix/suffix is applied to empty fields and is only enabled if you have values entered for either the prefix or the suffix.

Default Field Value

This field allows you to specify a default value where no value is present for the specified property within the component.

Output Sub-Totals/Totals For this Field

This checkbox enables the subtotalling (per category) and totalling of column values. Particularly useful for monetary values.


Set Display Options

Overview

This dialogue form allows customization of the display options within ISIS allowing you to change animation and graphics mode settings.

Options

Graphics Mode

Check the different box depending on which graphics mode you wish your computer to use, some graphics cards will support Open GL in hardware.

Auto-Pan Animation

This provides control over the smooth panning of the board.

  • Panning Distance - Setting the distance moved.
  • Number of Steps - The smoothness of the scroll (the more steps the smoother the scroll).
  • Pan Time - The speed according to personal preference.

Highlight Animation

The highlight animation options control what happens when the mouse is placed over an object

  • Attack Rate - The speed at which items highlight when the mouse is placed over the object.
  • Release Rate - The speed at which an object highlight will disappear.

Multi-Sampling

Allows to change the anti-aliasing of text on the display providing your graphics card supports the options.


System Information

Overview

This information details your registration details and the expiry of your Update Subscription Contract. You should contact Labcenter Electronics if your subscription has expired as you will not be able to install versions of the software newer than the expiration of your USC.


Set Environment

Overview

This dialogue enables configuration of several application environment preferences.

Options

Autosave Time

Specify the time delay between automatic saves of the current design.

Number of Undo Levels

Specify the number of undo levels you want to keep. Obviously the more undo levels the more memory ISIS requires in order to store each stage.

Tooltip Delay

Specify the time the mouse must be held over an icon before the tooltip message for that icon appears.

Number of Filenames on File Menu

Specify the number of filenames that you want in the Most Recently Used list on the File Menu.

Auto Synchronise/Save with ARES?

Specify whether or not you want the ISIS to automatically back-annotate from ARES whenever it is brought to the foreground. If this option is selected, the ARES file will automatically be saved whenever ISIS is brought to the foreground.

Save/Load ISIS state in Design files?

Specify whether or not you want the general editing state of ISIS to be saved with the design file. For example, when checked this will store the mode you are in and the current sheet and will start up in that mode and on that sheet when next you load the design.


Set Paths

Overview

This dialogue form allows easier navigation through folders while saving and loading layouts, keeping track of libraries and creating paths to the directory where CADCAM files will be placed.

Options

Initial Folder for Designs

Provides options for the default behaviour of the File-Open directory. Options are to always use My Documents, to default to the last opened directory or to always open in a specified directory.

Library Locale

These option dictate whether component symbols are European or American standard. You will need to close and restart Proteus to reload the libraries before any changes here will take effect. These options affect parts selected into the design but do not adjust instances of a part that have already been placed on the schematic.

Template Folders

The templates path is used to specify the location or locations of your design templates and Bill of Materials templates. By default this is located within the Proteus directory of your installation but you can move this directory to a location of your choice. You can also add additional templates directories if for example, you want to have user design templates and company design templates in different directories.

Library Folders

Set the path(s) to the directory holding your library files. Proteus uses the library path(s) to locate all the schematic parts that have been created for use in Proteus. The libraries supplied with the software are located by default inside the Proteus directory of your installation but you can move them and/or add additional paths (on the network for example) as required.

Project Clips (Snippets) Folder

Set or change the path for the storage and retrieval of Project Clips. These are sections of schematic and optionally associated layout that you want to re-use in future designs (e.g. power supply, USB connector circuit).

See Also:

Project Clips.

Datasheet Folder

Specify the path to locally stored datasheets on components. This is only relevant should you choose to specify / associate component parts with datasheets. If you do this you can set datasheet name and download locations when making devices in the Libraries via the Make Device wizard.

Maximum Undo Levels

Set a value between 1 and 200 for the number of undo operations held in memory at any given time. The larger the number the more impact on computer memory and for most purposes the default of 20 is more than enough.

Maximum Backups

Proteus operates a system of incremental backups on save. These are saved into the specified Backups folder and work in a cyclical fashion. For example, when set to 10 the 11th save would overwrite the 1st backup so that the last 10 save operations were preserved in the Backups folder.

This can be any number between 1 and 100.

Autosave Interval

An autosave is not the same as a backup (which happens on a manual save). Autosave takes place while you are working and produces a temporary snapshot at regular intervals specified by this field.

This snapshot is then verified in the background by a second, silent copy of Proteus to ensure that it is not corrupted and that it can be loaded. After that it is placed into the Backups directory as an autosaved file.

Since autosaved files are verified they protect against a creeping error such as data corruption which could result in a normal backup being unloadable.

You can set the autosave interval from every 3 mins to every 60 mins. Bear in mind with large boards that it may take a second or so to save.

Autosave cannot take place while a modal dialogue is open but will be scheduled and will then complete as soon as the dialogue form is closed.

Backup Folder

This is the location into which the file backups and autosave file will be processed. By default it is in the Project directory of your current project, although you can move it to another directory (e.g. a synched dropbox folder) by entering a suitable path and folder name.

Toolbar Icon Size

Allows the provision of different sized icons, letting you choose the most appropriate for your monitor resolution.

Simulation Model and Module Folders

Set the path(s) to the models directory (by default this is located inside the Proteus directory of your installation). Proteus looks inside the models directory before a simulation to find all the simulation models necessary for simulating the current schematic. While typically there would be no need to specify multiple paths here you can add additional models directories if need be (for example, if you have created some simulation models of your own and wish to keep them in a separate place from ours).

Path to Folder for Simulation Results

Set the path to the Results directory. (by default this is located inside the Proteus directory of your installation). The results path is used to store the results of graph based simulations, must be specified and there can be only be one results path.

Limit maximum disk space used for simulation results to

Specify the amount of space (in Kbytes) that you wish to allocate your Results directory. ISIS deletes results files on a last recently used basis to restrict the amount of accumulated results data to this value.


Edit Design Defaults

Overview

This dialogue allows you to configure default styles and colours for the work environment in ISIS and for interactive simulation. If you want to persist these changes for future designs you need to use the Save as Template command on the File Menu when you have finished configuration.

Options

Colours

Use these options to specify global colour preferences for various objects on the schematic. Each option has its own context sensitive help topic.

  • Paper Colour - This is the colour used as the ‘background’ colour of the ISIS editing and overview windows.
  • Grid Colour - Specify the colour of the grid dots in the main editing window.
  • Work Area Box Colour - Specify the colour of the box drawn in the overview window which shows the part of the schematic currently in the editing window.
  • World Box Colour - Specify the colour of the box drawn in both the editing and the overview windows that shows the maximum sheet extents.
  • Highlight Colour - Specify the colour used for tagged objects.
  • Drag Colour - Specify the colour used when entering objects such as wires, graphics, subcircuits, etc. as well as when an object is dragged.

Animation

Use these options to specify colours for various animation conditions. Each option has its own context sensitive help topic.

  • Positive Colour - Specify the colour of a wire at a positive potential. This colour is blended with the ground colour for potentials between zero and the maximum wire animation voltage value.
  • Ground Colour - Specify the colour of a wire at ground potential.
  • Negative Colour - Specify the colour of a wire at a negative potential. This colour is blended with the ground colour for potentials between zero and the minus the maximum wire animation voltage value.
  • Logic '1' Colour - Specify the colour of a wire when at a logic ‘1’ state.
  • Logic '0' Colour - Specify the colour of a wire when at a logic ‘0’ state.
  • Logic '?' Colour - Specify the colour of a wire when at an undefined or floating state.

Hidden Objects

Use these options to configure defaults for hidden objects. Each option has its own context sensitive help topic.

  • Show Hidden Text? - Specify whether or not any hidden properties should be displayed on the schematic.
  • Show Hidden Pins? - Specify whether or not to display any hidden power pins on the schematic.
  • 'Hidden' Colour - Specify the colour in which you want hidden objects to appear if made visible.

Font Face for Default Font

The TrueType™ font face name that is used wherever the Default Font is selected as the font face for text styles or 2D graphics text.

Render Master Sheet?

When checked the contents of the master sheet will be rendered on all sheets in the design. Unchecking this option will mean that the contents of the master sheet will not be drawn on any sheet on the schematic.


Set Graphics Styles

Overview

This dialogue is the main configuration tool for the appearance of the objects on the schematic. Select the object type you wish to edit and then set the attributes as desired. When you are finished you need to use the Save as Template command on the File Menu if you wish to persist the settings for future designs (all new designs are derived from a template).

Options

Style

Specify the name of the current global style being edited. When a new style is selected, the previous style is automatically updated with any changes made to its attributes.

  • New - Click to create a new global style. The new style is initialised with settings taken from the controls on the dialogue form when it is created so the new button also effects a ‘copy’ operation. Note that you cannot create a new style with the same name as an existing style.
  • Rename - Click to rename the current global style. You cannot rename any of the predefined (system) styles – when one of these styles is selected the Rename button is disabled. You cannot rename a style to the same name as an existing style.
  • Delete - Click to delete the currently selected global style. You cannot delete any of the predefined (system) styles - when one of these styles is selected the Delete button is disabled. Selecting this button causes a confirmation to be displayed after which the style is deleted. A deleted style cannot be recovered using the Undo button. Once a style is deleted, any local styles in the design using the style as their parent style are updated to use the most appropriate system style as their parent.
  • Undo - Click to undo any edits to the currently selected Global Style. Note that Rename and Delete operations cannot be undone using this button.
  • Import - Click to import a global graphics style.
  • Close - Click to close the dialogue form and commits any changes made to the currently selected style.

Line Attributes

  • Line Style - Specify the line style used for drawing lines, arcs and the outside boundaries of boxes, circles, paths, etc. The (none) option allows you to draw filled graphics with no bounding lines.
  • Width - Specify the line thickness for solid line styles. A width cannot be specified for dot/dash style lines as these can only be drawn with a single pixel width. You can specify a value of zero which forces ISIS to draw the line as a single device pixel regardless of any device resolution and/or scaling applicable at the time the line is drawn.
  • Colour - Specify the line colour.

Fill Attributes

  • Fill Style - Specify the type of fill to be applied to any closed area within the graphic object. The None option indicates the object is not to be filled (i.e. it is transparent), the Solid fill indicates the object is to be completely filled whilst the other fill styles indicate the object is to be given a hatched fill.
  • FG Colour - Specify an FG Colour.This option is only applicable for a solid or hatch fill; where no fill is specified this control is disabled. The foreground colour is the colour used for the solid fill or for the hatch lines in a hatched fill.
  • Use Bk. Colour? - This option is only applicable for a hatched fill; where none or a solid fill is specified this control is disabled. Deselecting this checkbox indicates that the 'gaps' between the lines of a hatched fill are to be transparent. Selecting this checkbox indicates that the 'gaps' are to be (solid) filled in a additional, background colour.
  • Bk. Colour - Specify a background colour. This option is only applicable for a hatched fill and where the Use Bk. Colour? Checkbox is selected (checked). Where none or a solid fill is specified this control is disabled, or where a hatched fill is specified and the Use Bk. Colour? checkbox is not selected (unchecked) this control is disabled. The background colour is the colour used to fill in between the lines of a hatched fill.

Sample

The sample window shows a (scaled) 1" x 1" box drawn in the current line and fill attributes.


Set Graphics Text

Overview

This dialogue allows you to specify the font and font attributes for 2D graphics text placed on the schematic. If you want to persist these changes for future designs you need to use the Save as Template command on the File Menu when you have finished configuration.

Options

Font Face

Set the initial font face for the 2D Graphics text. This is the initial or default font but can be altered using the Edit 2D Graphics Dialogue form.

Text Justification

These checkboxes allow you to define the required justification for the text.

Effects

Use these options to configure default effects for the text.

Character Sizes

  • Height - Specify the initial height for 2D Graphics Text. This will become the default height but can be altered as required using the Edit 2D Graphics Dialogue form.
  • Width - Specify the initial width for 2D Graphics Text. This will become the default width but can be altered as required using the Edit 2D Graphics Dialogue form.


Configure Junction Dots

Overview

This dialogue allows you to specify the style and size of junction dots placed on the schematic. If you want to persist these changes for future designs you need to use the Save as Template command on the File Menu when you have finished configuration.

Options

Size

Specify the global size of wire junction dots.

Shape

Use these options to globally specify the shape of wire junction dots. Note that to change graphical appearance of wire junction dots you need to edit the WIRE DOT graphics style with the Set Graphics Styles command on the same menu.


Set Text Styles

Overview

This dialogue form allows you to edit different styles for your text enabling you to change the font face, size, colours and add effects while allowing you to see a sample of the style.

Options

Style

Specify the name of the current global style being edited. When a new style is selected, the previous style is automatically updated with any changes made to its attributes.

  • New - Click to create a new global style. The new style is initialised with settings taken from the controls on the dialogue form when it is created so the new button also effects a ‘copy’ operation. Note that you cannot create a new style with the same name as an existing style.
  • Rename - Click to rename the current global style. You cannot rename any of the predefined (system) styles – when one of these styles is selected the Rename button is disabled. You cannot rename a style to the same name as an existing style.
  • Delete - Click to delete the currently selected global style. You cannot delete any of the predefined (system) styles - when one of these styles is selected the Delete button is disabled. Selecting this button causes a confirmation to be displayed after which the style is deleted. A deleted style cannot be recovered using the Undo button. Once a style is deleted, any local styles in the design using the style as their parent style are updated to use the most appropriate system style as their parent.
  • Undo - Click to undo any edits to the currently selected Global Style. Note that Rename and Delete operations cannot be undone using this button.
  • Close - Click to close the dialogue form and commits any changes made to the currently selected style.

Font Face

Specify the name of the font face the text is to be displayed in. The drop down list lists all the TrueType™ fonts available on the machine as well as two special fonts: Default Font and Vector Font.

The Default Font causes the text to be displayed in the design-global default font as set on the Set Design Defaults dialogue form. If you use Default Font on all your styles then you can globally control the font face used in the design via the Set Design Defaults command on the Template menu.

The Vector Font causes the text to be displayed in an internal proprietary vector font which is particularly suited for plotters and other vector output.

Height

Specify the height of the text. You can use whatever standard units you like, such at th for thou (thousandths of an inch) or mm for millimetres.

Width

Specify the width of a character in the text. This field is only enabled for text to be drawn in the internal Vector Font (either explicitly or by selecting the Default Font where the default font has been set to be the Vector Font).Units can be specified as for the Height field.

Colour

Specify which colour the text is to be drawn in.

Effects

Use these options to configure default effects for the text.

Sample

The sample box displays a sample of text drawn with the current style settings. Note that text drawn in the 'paper' colour or where the Visible check box is not checked, no text will be visible.


Global Annotator

Overview

This dialogue allows you to re-annotate all or part of the schematic with an initial annotation reference.

Options

Scope

Determine the scope of the annotation according to these options.

  • Whole Design - Specify annotation over the entire design.
  • Current Branch - Specify annotation from the current level of the sheet hierarchy downwards. Will include any sub-circuits derived from the current sheet.
  • Current Sheet - Specify annotation over the current sheet only.

Mode

Determine the mode of the annotation according to these options.

  • Total - Will re-annotate all parts in the selected scope.
  • Incremental - Will re-annotate only parts that do not have an annotation.

Initial Count

Specify the initial value for the annotator. For example, if you set this to be 7 then the relevant components will be annotated with suffix’s 7,8,9,10,etc.

Note:

You can also perform global or total annotation of the schematic based on the physical (geometric) layout of the board in the ARES layout module as follows:

  • If live netlisting is off (Tools menu in ARES) then turn it on.

  • Launch Automatic Annotator from the Tools Menu in ARES and specify starting point and direction.
  • The schematic annotation will update automatically after the layout annotation completes.


Netlist Compiler

Overview

This dialogue allows you to manually compile a netlist for the current schematic. If you are working with the ARES Layout software you should use the automatic netlisting method (Netlist to ARES command on the Tools Menu. Typically you would use this dialogue if you have designed the schematic in ISIS but are laying out the PCB in a different PCB package.

Do note that it is almost certain that the name of PCB footprints will be different in a foreign PCB package to that given in the ARES Layout software. This means that you will need to manually match the PCB footprint names on import to the PCB software if you are working in this way.

Options

Output

Specify whether you want to output the netlist to a file or to the netlist viewer.

Mode

Specify the type of netlist that you wish to generate. A logical netlist contains pin names whereas a physical netlist contains pin numbers. A more subtle effect is that in a physical netlist, the elements of multi-element parts such as the 7400 will be grouped (appearing, for example, as U1) whereas in a logical netlist they are kept separate (appearing, for example, as U1:A, U1:B, U1:C, U1:D). A logical netlist will generally be used for simulation whilst a physical netlist is best suited to PCB design. Transfer mode is used in specialist applications of ISIS only.

Scope

Specify the scope for the netlist. The default scope is the whole design. Current scope restricts the netlist generator to just the current sheet. This is generally used when you wish to extract the netlist from a child sheet - perhaps a daughter card which is to be represented as a layout in ARES, but which is part of a larger design that needs to be simulated whole. It is also possible to create a 'virtual test jig' by having a parent sheet which contains circuitry to simulate the components on the child sheet.

Depth

Specify the depth of the netlist. The default mode is to flatten the design. In this case objects with sub-sheets will be replaced by their implementation. If the netlist is not flattened then this replacement will not occur and objects with sub-sheets will appear as-is in the partslist and netlist. The most common reason for not flatting a design is if some components have attached child sheets representing their simulator models, but you wish to produce a purely physical netlist for PCB design. Note that sheets specified as non-physical will not be flattened for PCB design, irrespective of this setting.

Format

Specify the desired netlist format. Context Sensitive help is available on each option.

  • SDF - Specify the SDF netlist format. SDF (Schematic Description Format) is the native Labcenter format - used by PROSPICE, ARES and any future Labcenter EDA products. Also very easy to read in and process to other forms. Contains all textual/connectivity information contained in the DSN file. Use Physical mode for ARES.
  • Eedesigner - Specify the EE Designer III netlist format. The user property PACKAGE is used for the package name. Use in Physical mode.
  • Multiwire/ Eag - Specify the Multiwire netlist format. Also used by EAGLE PCB design.File format does not contain packaging data. Use in Physical mode.
  • Spice - Specify the SPICE netlist format, also ideal for P-Spice. The ground net will be node 0, unnamed nets start at 1000; numeric net will be fed straight through. The file SPICE.LXB can be re-named to SPICE.LIB to obtain a set of SPICE compatible models. Use in Logical mode. Do not use this format for creating PROSPICE models – use the normal MDF output from the Model Compiler – it is far more flexible.
  • Tango - Specify the Tango netlist format, also used by Protel and others. A good general purpose format. Use in Physical mode.
  • Vutrax - Specify the VUTRAX netlist format.
  • Boardmarker - Netlist format for Tsien Boardmaker II. The user property PACKAGE is used for the package name. Use in Physical mode.
  • Futurenet - Netlist format used by Dash design tools. Also popular for general purpose netlist transfer. Use Physical mode for Pin List, Logical mode for Net List.
  • Racal - Specify the RACAL netlist format. Used by RedBoard, CADSTAR etc. Two files are created with CPT and NET extensions. The user property PACKAGE is used for the package name. Use Physical mode.
  • Spice - Age - Specify the SPICE-AGE netlist format for Those Engineers analogue simulator .The file SPICEAGE.LXB can be re-named to SPICEAGE.LIB to obtain a set of SPICE-AGE compatible models.


Property Assignment Tool

Overview

This tool provides a generic and semi-automatic way of assigning properties to one or more objects on the schematic. You can use this tool for everything from labelling bus taps to changing the footprints for a group of resistors.

We recommend that for changing component properties you use the Design Explorer which more easily allows for mass editing with a spreadsheet like interface to the schematic.

See Also:

Design Explorer

Options

String

Specify the property assignment, or property keyword on which the selected action will be performed for each object.

Count

Specify the initial value for the counter. The counter is incremented on each application of the PAT. The current value of the counter may be included in the string by entering a hash ('#') character.

Increment

Specify by what amount you wish to increment on each use of the Property Assignment Tool.

Action

Specify the action you wish to perform.

  • Assign - The String field should contain a property assignment of the form: keyword=value and this property will be assigned to the selected objects. If you want to assign values that run in a sequence, such as D0, D1, D2 etc. then use the hash ('#') character in the value and set the initial count as required. Both user and system properties may be assigned; assigning system properties may cause graphical changes to your drawing.
  • Remove - The String field should contain a property keyword only and this property will be removed from the selected objects. Only user properties can be removed.
  • Rename - The String field should contain both a property assignment of the form: current_keyword=new_keyword. The name to the left of the assignment is the existing property name you wish to rename; the name to the right is the new name you wish to rename it to. Only user properties can be renamed.
  • Show - The String field should contain a property keyword only and this property will be made visible for the selected objects. All user properties and system properties can be shown.
  • Hide - The String field should contain a property keyword only and this property will be made invisible for the selected objects. All user properties and system properties can be hidden.
  • Resize - The String field should contain an assignment such as REF=20,16 and the given property will be assigned a new height and width for the selected objects. Only textual system properties may be resized. Note that changing a labels text size implicitly sets the Height and Width attributes of the labels text style to be local and that, thereafter, changes to the global text style for the label will not be reflected in these labels.

Apply To

Specify in what way you wish to apply the selected action to the design.

  • On Click - The diagram editor is put into Main Mode, with the Instant Edit icon selected. Each object on which you click left has the selected action performed upon it. When you select a different icon, the PAT is cancelled. This mode is the only way to apply the PAT to wires, in order to assign wire labels. ISIS cannot perform PAT assignments on tagged wires because there would be no way for it to know where to put the wire labels.
  • Local Tagged - The selected action is performed on all tagged objects on the current sheet only. You can select the tagged objects either individually, or with the Search & Tag commands.
  • Global Tagged - The selected action is performed on all tagged objects across the entire design. You can select the tagged objects either individually, or with the Search & Tag commands. ISIS is capable of remembering different tag states for different instances of an object in a hierarchical design, should this be an issue. However, the user property blocks are shared between instances so you cannot change a user property in just one instance.
  • All Objects - The selected action is performed on all the objects in the design.

Help

Provides a basic list of properties that can be manipulated for each object type.


Search and Tag

Overview

This dialogue form gives you a fast and efficient method of searching for and highlighting components on the design. The search can also be expanded or refined with the AND and OR commands.

Design Explorer provides a more traditional search and filter interface for applying property changes to components.

See Also:

Design Explorer Search

Options

Property

Specify the Keyword of the property you wish to test. You can test both system and user properties.

String

Specify the string you wish to test against the property value.

Search Mode

Specify the type of search you want to perform. If items already exist in the results list box you can either refine or add to the results to help you find the object you are searching for.

Matching Mode

Specify how you want the string to be tested against the property.

Listbox

The listbox displays the results of a given search. Double clicking on an item in this list box will zoom in to the object in question, tag all the items in the listbox and exit the dialogue. If the object is not the one you were looking for simply re-invoke the dialogue. The results box is populated with all tagged objects on load so you will find the results of your previous search available to you (provided you have not deselected the tagged items).

Search across whole design?

Specify whether you want the search applied to the entire design (checked) or just to the current sheet.

Case sensitive search?

This option allows you to restrict your result set to matches where the characters are in the same case (capitals or lowercase) as those typed in the search term.


Display Toolbars

Overview

This dialogue form provides you with a quick and simple way to choose which groups of icons you would like to appear on the main toolbar at the top of the screen.


PLOTTER OUTPUT

Windows support for pen plotters is, unfortunately, very poor. Although drivers are supplied for HPGL and other plotters, the implementation of these drivers is very sketchy. Better drivers may be available for particular plotters, but we have not relied on this in designing the plotter support within ISIS for Windows. Instead, we rely on the Windows plotter driver only to draw straight lines and then ISIS itself does the rest.

Plotter output is generated as for bitmap printer output using the Print command on the File menu. Where a plotter is selected as the output device, the Labcenter Plotter Driver option is enabled on the Print Design dialogue form. If this option is checked then ISIS only relies on the plotter driver’s ability to draw a line on the plotter with ISIS linearising arcs, circles, etc. and rendering text in a vector font. If this option is not checked then ISIS treats the plotter driver just like any other driver and expects it to sensibly handle all Windows GDI (Graphics Device Interface) calls, including translation of functions the plotter itself doesn’t support (for example, Bezier curves).

The plotter drivers are able to generate a multi-coloured plot - to enable colour plots check the box at the top right of the print dialogue form.

Note that this option is dynamically enabled if your plotter driver presents itself as being capable of colour plotting but can be overridden via the advanced options button if Windows is reporting the plotter as being unable to handle colour plots.


DIFFERENTIAL PAIR SETUP

Introduction

While much of the differential pair work is specific to the layout there are two tasks required on the schematic, namely to identify the differential pair pins and then to name the diff pair itself. Both of these are done with the diff pair configurator tool which is launched from the right click context menu on one of the two diff pair wires.

Once everything is placed and wired on the schematic the workflow is summarized below.

  1. Name the diff pair class.
  2. Find the start component.
  3. Find the end component.
  4. Select the start component pins.
  5. Select the end component pins (if not done automatically)
  6. Manage the pass through components (if not done automatically)
  7. Save and exit when the configurator dialogue shows a complete signal path.

Important : Use terminals and terminal names, not junction dots and wire labels.

The full process, along with some worked examples can be found in the layout module help as linked below.

See Also:

Differential Pair Setup - Layout Manual.