Home

I2C MEMORY MODEL

Introduction

The I2C Memory Model is a generic Proteus VSM model designed to model the timing and functionality of I2C memory devices from a wide range of manufacturers.

A library of pre-configured memory devices from manufacturers such as Microchip Technologies™ , ST Microelectronics™ and Fairchild™ is supplied with Proteus VSM.

Contents

  • Modelling A New Device.

  • Model Properties.

  • Schematic Device Pin Names.

  • Memory and Page Sizes.

  • Device Selection.

  • Memory Block Selection.

  • Hardware Write Protection.

  • Software Write Protection.

  • PRE Pin Support.

  • Memory Timing.

  • Log, Warning And Error Messages.

This help file last modified on 05th March 2010.


DEVICE SELECTION

Overview

Many memory devices support external hardware selection by way of one or more device select pins. This allows several devices to be connected in parallel to the I2C bus. A device only responds to a command byte when the state of one or more bits in the lower nibble of the command byte matches the states of its device select pins.

The memory model models this functionality as follows:

  • The schematic device must have pins named as A0, E0, or E for the first (lowest) address select pin, A1 or E1 for the second address select pin (if any) and A2 or E2 for the third address select pin (if any).

  • In determining the value on the address select pins the model ignores any pin not found so that a device with two address select pins labelled E1 and E2, for example, yields an address where E1 sets/clears bit zero and E2 sets/clears bit one. Thus, for example, if both E1 and E2 were active then the device address would be determined as ‘3’.

  • The model obtains the device address select value from the command byte by first shifting the command byte to the left and then applying a bit mask. The number of places the command byte should be shifted by is specified by the DVCADDRSHIFT property. The mask value to be applied is specified by the DVCADDRMASK property.

  • The model only responds (and generates an acknowledge bit) to command bytes where the two values are the same.

The following illustration shows the format of a typical command byte. The command byte’s bits 2 and 3 form the device address select:

As an example, if the command byte were 0b10100100 (0xA4) then the device selected would be device number 1.


HARDWARE WRITE PROTECTION

The I2C memory model supports an external write protect pin. To use this functionality the model must be configured as follows:

  • The schematic device must have a pin named WP or $WC$. This is the write protect pin and is by default active high (that is, when the pin is high the memory is write protected and when the pin is low, the memory is read/write). This behaviour can be changed using the INVERT property (see Proteus VSM documentation).

  • The WPLOW and WPHIGH properties should be set to define the first and last byte of memory protected when the write protect pin is active. The default values for each property will cause the entire memory to be protected.

    For example, if WPLOW is 0x0080 and WPHIGH is 0x00FF then bytes 0x0080 to 0x00FF are protected; addresses 0x0000-0x007F and addresses 0x0100 and above are read/write.


LogWarnErrorMsgs

LOG/WARN/ERROR MESSAGES

Introduction

The I2C memory model outputs a number of messages that are either log, warning or error messages.

For an interactive simulation log messages only appear in the model's private log window (accessible from the Debug menu in ISIS). However, the USESIMLOG property may be used to have the model place log messages in the main Proteus VSM simulation as well if this is useful. For a graph-based (non-interactive) simulation log messages are always placed in the Proteus VSM simulation log. Log messages appear as follows:

<time> [<state>]: <message>

The <time> indicates the current simulation time in seconds, the <state> indicates the current internal state of the model (see the section below) and the <message> is the message text.

Warning messages appear in both the log window and the Proteus simulation log as follows:

<time> [<state>]: *WARNING* <message>

The meaning of <time>, <state> and <message> are the same as for a log message.

Error messages always appear in the Proteus simulation log and will cause the simulation to be cancelled.

Internal Model State

The memory model is constructed as a state machine with the model moving from one state to another according to pin transitions and data received. All log and warning messages indicate the current internal state of the model as follows:

STOPPED

The model is currently idle and awaiting a start condition.

RX_CMD

The model is ready to receive or is receiving a command word.

RX_ADDR(1)

The model is ready to receive or is receiving the first address word.

RX_ADDR(2)

The model is ready to receive or is receiving the second address word. This state only occurs where the DATAWIDTH property is greater than eight.

RX_DATA

The model is ready to receive or is receiving a data word.

TX_DATA

The model is ready to transmit or is transmitting a data word.

TX_END

The model is about to release the SDA pin after transmitting a data word.

START_ACK

The model is ready and waiting to transmit an acknowledge bit.

END_ACK

The model is transmitting an acknowledge bit and is waiting to end the acknowledge.

TEST_ACK

The model has transmitted a data byte is testing or waiting to test whether the master is acknowledging the transmitted word.

EXP_STOP

A model expects a stop condition in the next 'bit time'.

STOPPING

A current operation has been aborted and the model is waiting for a stop condition.

If the model is currently performing an internal erase/write operation then the state is followed by an asterisk ('*').

Log Messages

The following is a complete list of all log messages generated by the model, listed alphabetically. A log message will only be output if the appropriate LOG_xxx property (indicated) is defined Yes.

Address byte received: <HEX> (<BINARY>). Complete address is <HEX> (<VALUE>).

An address byte has been received. The message shows the byte received as well as the accumulated address word for multi-byte (extended) addressing.

Enabled by LOG_ADDRS property.

Command is not for this device (command address is <ADDR>, device address is <ADDR>).

A command word has been received but is not for this particular device. The message shows the device address as decoded from the command byte as well as the device address as currently selected by the address select pins.

Enabled by LOG_CMDS property.

Command received: <CMD> (<CMD>). Device=<DVC>, Block=<BLK>, Address=<ADDR> RD/WR=<RW>.

A command word has been received. The message shows the break down of the command word as determined by the model. Note that for fields not being implemented for the device (e.g. the device doesn’t support block selection) the values will be zero.

Enabled by LOG_CMDS property.

Data received: <DATA> (<DATA>).

A data word has been received. The message shows the word both as a hexadecimal and binary value of the data word.

Enabled by LOG_DATA property.

Data transmitted: <DATA> (<DATA>).

The model has completed transmission of a word of data. The message shows the word both as a hexadecimal and binary value of the data byte.

Enabled by LOG_DATA property.

End of acknowledge. New state is [<STATE>].

The model has reached the end of an acknowledge bit and is releasing (tri-stating) the SDA pin (if the model is about to transmit a zero data bit it leaves the SDA pin driven low). The next internal state of the model is shown and may be useful for debugging.

Enabled by LOG_ACKS property.

Internal write cycle started.

An internal erase/write cycle has commenced. The model will not generate acknowledge bits to commands until the cycle has been completed.

Enabled by LOG_OTHER property.

Internal write in progress - command word will not be acknowledged.

A command word has been received but will not be acknowledged because an internal erase/write cycle is in progress.

Enabled by LOG_CMDS property.

Negative clock edge ignored.

A negative clock edge has been detected on the SCK pin when one wasn’t expected and has been ignored by the model. The message indicates that there may be some erroneous bus behaviour.

Enabled by LOG_EDGES property.

Next address is <ADDR>; next data is <DATA> (<DATA>).

The model has completed the read of a data word and incremented the address pointer to the address indicated. If the master acknowledges the data byte and doesn't generate a stop condition then a sequential read operation is assumed and the model will transmit the data indicated from this address.

Enabled by LOG_DATA property.

PRE pin active, memory <FROM>-<TO> is not write protected (Bit <ADDR><2> is set).

The PRE pin has become active but the memory is not protected as bit 2 in the last memory location is not clear. The message indicates the memory range that would normally be protected

Enabled by LOG_OTHER property.

Positive clock edge ignored.

A positive clock edge has been detected on the SCK pin when one wasn’t expected and has been ignored by the model. The message indicates that there may be some erroneous bus behaviour.

Enabled by LOG_EDGES property.

Repeated start condition (<N>) detected.

A repeated start condition has been detected. The number of repeated start conditions so far found is indicated by <N>.

Enabled by LOG_DATA property.

Set SDA for bit <bit> of data word <data> (<bit value>).

The model is driving the SDA pin in order to transmit a data bit. The bit position is indicated by <bit>, data word is indicated by <data> and the current state of the particular bit by <bit value>.

Enabled by LOG_DATA property.

Software Write Protect (SWP) command when SWP command already received isn't acknowledged.

Once a Software Write Protect command word is received and the memory is write protected, any subsequent Software Write Protect commands are not acknowledged. This allows the master to determine if the memory is write protected via a SWP command.

Enabled by LOG_SWP property.

Software Write Protect (SWP) register written. All memory is now write-protected.

The Software Write Protect register has been successfully written and is active.

Enabled by LOG_SWP property.

Start condition detected.

A start condition has been detected

Enabled by LOG_STARTSTOP property.

Start of acknowledge - driving SDA low.

The model is generating the start of an acknowledge bit and is driving the SDA pin low.

Enabled by LOG_ACKS property.

Stop condition detected.

A stop condition has been detected.

Enabled by LOG_STARTSTOP property.

Test of acknowledge after a read: <ACK_STATE>.

The model has completed transmitting a data word to the master and has tested the SDA pin to see if the master has acknowledged the data word. The <ACK_STATE> indicates whether an acknowledge was detected or not.

Enabled by LOG_ACKS property.

Unknown command value (<CMD>) received - command is ignored.

A command word has been received (indicated by <CMD>) which is not recognized as either a memory read/write command or a Software Write Protect (SWP) command. The command word is ignored.

Enabled by LOG_CMDS property.

Writing <N> words of data to memory at address <FROM>-<TO>.

An internal erase/write cycle has started at the end of a page write operation and the model is writing data to memory. The number of words and the memory addresses being written are indicated.

Enabled by LOG_OTHER property.

Writing data <DATA> (<DATA>) to memory at address <ADDR>.

An internal erase/write cycle has started at the end of a word write operation and the model is writing a single data word to memory. The data word and the memory address being written are indicated.

Enabled by LOG_OTHER property.

Warning Messages

The following is a complete list of all warning messages generated by the model, listed alphabetically. A warning message will only be output if the appropriate WARN_xxx property (indicated) is defined Yes.

$WC$ hold time violated. Stop was at <t1>, hold time is <t2>, min. hold time is <t3>.

See WP hold time violated error message.

$WC$ setup time violated. $WC$ changed at <t1>, setup time is <t2>, min. setup time is <t3>.

  • See WP setup time violated error message.

Address (<ADDR>) received is outside of memory (<MEMSIZE> bytes). Address will be wrapped.

An address word is been received that is outside of the memory. The address received is indicated by <ADDR> and the configured memory size by <MEMSIZE>.

Enabled by the WARN_ADDRS property.

Bus free time violated. Last stop was at <t1>, bus has been free <t2>, minumum is <t3>.

A start condition has been detected and the delay between the start condition and the previous stop condition is less than the minimum specified by the TD_BUSFREE property.

The time of the last stop condition is indicated by <t1>, the time the bus has been free is indicated by <t2> and the minimum time as specified by the TD_BUSFREE property is indicated by <t3>.

Enabled by the WARN_TIMING property.

Change of PRE pin during a command is ambiguous.

As manufactures' data sheets to not state the timing of changes on the PRE pin the model assumes that changes to the PRE pin will only occur before or after any command sequence. Any change in the state of the pin during a command sequence will result in this warning.

Note that the model samples the PRE pin at the start of a write operation (i.e. when the stop condition is detected) so whilst this warning is issued for a change in the pin's state mid-way through a command sequence, the state of the pin at the time of the write operation is still honoured.

Enabled by the WARN_OTHER property.

Change of $WC$ (to <STATE>) during a command is ambiguous.

See Change of WP to error message.

Change of WP (to <STATE>) during a command is ambiguous.

As manufactures' data sheets to not state the timing of changes on the write protect pin (WP or $WC$) the model assumes that changes on this pin will only occur before or after any command sequence. Any change in the state of the pin during a command sequence will result in this warning.

Note that the model samples the WP/$WC$ pin at the start of a write operation (i.e. when the stop condition is detected) so whilst this warning is issued for a change in the pin's state mid-way through a command sequence, the state of the pin at the time of the write operation is still honoured.

Enabled by the WARN_OTHER property.

Internal write buffer overflowed: buffer size is <BS> words but <N> words received.

A page write operation has written more words to the memory than the device's page size allows and the address pointer will have wrapped around such that words specified at the start of the write operation are overwritten by words specified at the end of the operation. The page buffer size of the device, as set by the WPAGESIZE property, is indicated by <BS>; the number of words received as part of the page write operation is indicated by <N>.

Enabled by the WARN_OTHER property.

PRE hold time violated. Stop was at <t1>, hold time is <t2>, min. hold time is <t3>.

A change has been detected on the PRE pin and the delay between the change and a previous stop condition that initiated an erase/write cycle is less than the minimum specified by the TD_PRE_HOLD property.

The time of the stop condition that initiated the erase/write cycle is indicated by <t1>, the delay between the pin change and the stop condition is indicated by <t2> and the minimum hold time as specified by the TD_PRE_HOLD property is indicated by <t3>.

Enabled by the WARN_TIMING property.

PRE pin active but last memory byte (0xXX at 0xXXXX) has low order bits set.

One or more unused bits in the last memory byte are set when the PRE pin is active.

For devices with a PRE pin the last memory byte contains the address mask (for the protected memory base address) in the upper bits and has bit 2 (mask value 0b00000100) as an enable bit. The documentation states that all remaining low order bits should be zero even though they are not used.

Enabled by the WARN_OTHER property.

Read command received but address pointer not initialised. Address zero will be read.

A current-address read command has been received as the first command since the memory powered up. Since no write operation has occurred to initialise the address pointer the model defaults to address zero.

Enabled by the WARN_OTHER property.

Data setup time violated. Last change on SDA was at <t1>, setup time is <t2>, min. setup time is <t3>.

A positive clock edge has been detected on SCK that clocks a data bit in to memory but the delay between it and a previous change on SDA is less than that specified by the TD_DATA_SETUP property.

The time of the last change on the SDA property is indicated by <t1> and the delay between it and the clock edge is indicated by <t2> and the minimum as specified by the TD_DATA_SETUP property is indicated by <t3>.

Enabled by the WARN_TIMING property.

Start hold time violated. Start was at <t1>, hold time is <t2>, min. hold time is <t3>.

A negative edge has been detected after a start condition and the delay between the two is less than the minimum specified by the TD_START_HOLD property.

The time of the last start condition is indicated by <t1>, the delay between the negative edge and the start condition is indicated by <t2> and the minimum as specified by the TD_START_HOLD property is indicated by <t3>.

Enabled by the WARN_TIMING property.

Start setup time violated. Clock positive edge was at <t1>, setup time is <t2>, minimum is <t3>

A start condition has been detected but the delay between it and the previous low-to-high transition of the SCK pin is less than the minimum specified by the TD_START_SETUP property.

The time of the last positive edge on the SCK pin is indicated by <t1>, the delay between it and the start condition is indicated by <t2> and the minimum as specified by the TD_START_SETUP property is indicated by <t3>.

Enabled by the WARN_TIMING property.

Stop condition was expected but negative clock edge has been detected.

The model expected a stop condition but none was found.

For example, on a device that only supports single byte writes, the master should generate stop condition immediately after the memory has acknowledged the data byte. If the SCK pin goes low before the stop condition is detected then this implies the master is trying to clock more data in to the memory (i.e. perform a page write).

After this warning the model waits until the stop condition is detected without issuing further warnings.

Enabled by the WARN_OTHER property.

Stop detected part way through receiving data byte. Write operation aborted.

A stop condition has been received part way through the reception of a command, address or data word. The model aborts the current operation and returns to waiting for a start condition. In particular, if the current operation was a page write operation and the stop condition occurs after several bytes have been successfully received then no bytes are written.

Enabled by the WARN_OTHER property.

Stop setup time violated. Clock positive edge was at <t1>, setup time is <t2>, minimum is <t3>.

A stop condition has been detected but the delay between it and the previous low-to-high transition of the SCK pin is less than the minimum specified by the TD_STOP_SETUP property.

The time of the last positive edge on the SCK pin is indicated by <t1>, the delay between it and the stop condition is indicated by <t2> and the minimum as specified by the TD_STOP_SETUP property is indicated by <t3>.

Enabled by the WARN_TIMING property.

Stop condition whilst memory is transmitting data is unreliable.

A stop condition has been detected whilst data is was being read from the memory. However the creation of stop condition is only possible when the data on the SDA pin is a ‘1’ (i.e. the SDA pin is tristate) and hence the creation of the stop condition is dependent on the data being read and therefore unreliable.

A stop condition requires a low-to-high transition of the SDA pin whilst the SCK pin is high. When a master is reading from the memory device it generates the clock edges to clock data from the memory and the memory drives the SDA pin with the appropriate data. The memory changes the state of the SDA pin whilst the SCK clock is low and holds it steady whilst the SCK clock is high. Because the SDA pin is open collector (i.e. is driven strong low or float) it is possible, when the SDA pin is being driven and held as a float (for a ‘1’ data bit) that the master itself pull SDA low and then high again so generating a stop condition. The master cannot do this when the SDA pin is being driven low (for a ‘0’ data bit) as it is not possible for the master to pull the SDA pin high (a contention arises).

Enabled by the WARN_OTHER property.

WP hold time violated. Stop was at <t1>, hold time is <t2>, min. hold time is <t3>.

The hardware write protect pin (WP or $WC$) has changed after an erase/write cycle has started and the delay between the change and the stop condition that initiated the erase/write cycle is less than the minimum specified by the TD_WP_HOLD property.

The time of the stop condition that initiated the erase/write cycle is indicated by <t1>, the delay between the pin change and the stop condition is indicated by <t2> and the minimum hold time as specified by the TD_WP_HOLD property is indicated by <t3>.

Enabled by the WARN_TIMING property.

WP setup time violated. WP changed at <t1>, setup time is <t2>, min. setup time is <t3>.

A stop condition has been detected that initiates an erase/write cycle but the delay between it and a previous change of the hardware write protect pin (WP or $WC$) is less than the minimum specified by the TD_WP_SETUP property.

after an erase/write cycle has started and the delay between the change and the stop condition that initiated the erase/write cycle is less than the minimum specified by the TD_WP_HOLD.

The time of the stop condition that initiated the erase/write cycle is indicated by <t1>, the delay between the pin change and the stop condition is indicated by <t2> and the minimum hold time as specified by the TD_WP_SETUP property is indicated by <t3>.

Enabled by the WARN_TIMING property.

Write to addresses <FROM>-<TO> not allowed - software write protect has been set.

An attempt has been made to write data to several addresses (as indicated) after a Software Write Protect (SWP) command has been received. Once a SWP command has been received by the model, software write protection is enabled and all memory is write protected. The write operation is ignored.

Enabled by the WARN_OTHER property.

Write to address <ADDR> not allowed - software write protect has been set.

An attempt has been made to write data to an address (indicated) after a Software Write Protect (SWP) command has been received. Once a SWP command has been received by the model, software write protection is enabled and all memory is write protected. The write operation is ignored.

Enabled by the WARN_OTHER property.

Write to addresses <FROM>-<TO> not allowed - PRE pin is active and enabled.

An attempt has been made to write data to one or more addresses currently protected by the PRE pin protection mechanism. The message indicates the addresses that an attempt are being written.

Enabled by the WARN_OTHER property.

Write to address <ADDR> not allowed - PRE pin is active and enabled.

An attempt has been made to write data an address (indicated) that is currently protected by the PRE pin protection mechanism.

Enabled by the WARN_OTHER property.

Write to addresses <FROM>-<TO> not allowed - pin <PIN> is <STATE>.

An attempt has been made to write data to one or more addresses currently protected by the named hardware write protection pin (WP or $WC$) being active/inactive. The message indicates the addresses that are being written, , the pin name and its state.

Enabled by the WARN_OTHER property.

Write to address <ADDR> not allowed - pin <PIN> is <STATE>.

An attempt has been made to write data to an address currently protected by the named hardware write protection pin (WP or $WC$) being active/inactive. The message indicates the address that are being written, the pin name and its state.

Enabled by the WARN_OTHER property.

Write to SWP register disabled because <PIN> pin is <state>.

A write operation to the Software Write Protect (SWP) register has been attempted but hasn’t occurred because the hardware write protect pin (WP or $WC$) is active or inactive. Writes to the SWP register are not possible when the device hardware protected.

Enabled by the WARN_OTHER property.


MEMORY PAGE SIZES

The overall size of the memory is specified in bytes via the MEMSIZE property. If you want the memory to be persistent you need to use the MODDATA property as documented in the VSM help.

The model supports both single byte and paged memory write modes with the maximum length of a writable page being specified by the WPAGESIZE property. For devices that do not support a paged write mode the WPAGESIZE should be set to 1.

For any paged write, an attempt to write bytes beyond the write page boundary results in the address pointer wrapping around to the start of the page. For example, for a memory with an eight byte page, if a paged write is made to address 12 (half way through the first page) then only four bytes may be written (addresses 12,13,14 and 15). An attempt to write a fifth byte (to address 16) results in the internal address pointer wrapping around to address 8 and the fifth byte being written to this location.

The model supports the notion of a paged memory reads for sequential read operations with the maximum length of a readable page being specified by the RPAGESIZE property. For any sequential read, an attempt to read bytes beyond the read page boundary results in the address pointer wrapping around to the start of the page. Most devices are able to read their entire memories and for these devices the RPAGESIZE property should be left undefined so that it defaults to the value of the MEMSIZE property.

The MEMSIZE property.

The WPAGESIZE property.

The RPAGESIZE property.


MEMORY BLOCK SELECTION

Introduction

The original I2C specification only allows for memory devices of up to 256 bytes (2k bits) of memory. To support this the specification uses a single address byte transmitted after the command word to select the memory address.

Many memory devices have more than 256 bytes of memory and such devices invariably use one of two methods to allow the memory to be addressed:

  1. Generally, if the amount of memory on the device is between 256 and 2k bytes (2k bits and 16k bits) then the device may use one or more of the lower bits of the command word as extra address bits. These lower command bits thus form a ‘block selector’ selecting between two or more blocks of memory, each block being 256 bytes.

    As the lower order bits of the command are normally used for selecting between different memory devices on the I2C bus (see the Device Selection section) it follows utilising these bits as a block selector is done at the expense of being able to have several memory devices on the I2C bus.
  2. Generally, if the amount of memory is greater than 2k bytes (16k bits) then an ‘extended addressing’ system is adopted whereby the device expects two address bytes after the command word: the most significant byte of the address followed by the least significant byte.

Although most memory devices adopt one or the other approach the I2C memory model models both methods simultaneously as follows:

  1. The low order bits of any address are always taken from the address byte or bytes received from the master after the command word.

    The number of bytes the model expects to receive is determined by the value assigned to the ADDRWIDTH property. If the value is less than or equal to eight then the model expects a single address byte after the command word; if value is greater than eight then the model assumes the device supports extended addressing and expects two address bytes with the most significant byte being transmitted first and the least significant byte transmitted last.

    Regardless of whether the address word is formed by a one or two bytes, the resulting address word is always masked by the number of bits specified in the ADDRWIDTH property to ensure high order bits are zero.

  2. The model obtains the block address select value from the command byte by first shifting the command byte to the left and then applying a bit mask. The number of places the command byte should be shifted by is specified by the BLKADDRSHIFT property. The mask value to be applied is specified by the BLKADDRMASK property.

    If the model doesn’t support block selection then the BLKADDRMASK property should be set to zero (its default).

  3. The model forms a final address word by placing the block address formed in stage (2) in to the high order bits of the masked address word formed in stage (1).

The following illustration shows the format of typical command and address bytes for a typical 1k-bit memory device. The command byte’s bits 1 and 2 form the block select and provide the upper two bits of any address:

As an example, if the command byte received by the model was 0b10100100 (0xA4) and the address byte received was 0x55 this would yield a final byte address of 0x255.

The following illustration shows how a 12-bit address word might be formed using for a device that uses extended addressing. The example is a little contrived since, as has already been mentioned, most devices that support extended addressing would get their entire address word from the two address bytes that follow the command word and not from a mixture of the address bytes and the command word.

Note that it is important that the ADDRWIDTH property be correctly specified in order for the model to:

  1. correctly mask the address word formed from the received address bytes. Most memory devices that support extended (two byte) addresses ignore unused bits in second address byte.

  2. Correctly position any block selection bits in the most significant bits of the address word.


MEMORY TIMING

The model uses a small number of properties to determine the timing of the signals it generates:

  • TD_CLK_SDO

  • TD_CLK_ENDDATA

  • TD_CLK_ACK

  • TD_CLK_UNACK

Most manufacturers' data sheets only quote a minimum and a maximum time for the SCK-to-SDA. In such circumstances you can consider the TD_CLK_SDO property as the ‘data output setup time’ and the other three properties as the ‘data output hold time’

In order to model the worst case scenario, set the TD_CLK_SDO property to the maximum SCK-to-SDA delay given in the datasheet and set the other three properties to the minimum SCK-to-SDA delay given. The model then drives data on to the SDO pin at the latest time allowed and removes it at the earliest time allowed.

The model is also able to verify that signals generated by the master meet minimum timings via configuration of the following properties :

  • TD_CLK_HIGH

  • TD_CLK_LOW

  • TD_RSTART_SETUP

  • TD_START_SETUP

  • TD_START_HOLD

  • TD_DATA_SETUP

  • TD_STOP_SETUP

  • TD_WP_SETUP

  • TD_WP_HOLD

  • TD_PRE_SETUP

  • TD_PRE_HOLD

  • TD_BUSFREE

Any of these may be set to zero (the default if they are not defined) if they are not applicable to the device being modelled or if verification is not required.

Finally, the model uses two properties to determine the timing of its internal write cycle:

  • TD_WRITE

  • BYTETIMING

In general the TD_WRITE property is the maximum value quoted on the data sheet and the BYTETIMING property will be 'No' as the timing for most devices is the same whether it is writing a single word or a page of words. If the device is one of the older devices that use a FIFO buffer to hold write data then the BYTETIMING property may need to be 'Yes' in order that the write time is per word.

Timing Diagram.

Complete Properties Reference.


MODEL PROPERTIES

Property Index

The following is a complete list of all properties supported by the model. Properties have been grouped according to their function and as a result some properties are listed more than once:

Memory Size and General Configuration

  • MEMSIZE

  • WPAGESIZE

  • RPAGESIZE

  • RDWRCMD

  • CMDWIDTH

  • ADDRWIDTH

  • DATAWIDTH

  • BYTETIMING

  • INCRADDR

  • APWAA

  • ALWAYS_ACK_DATA

Device and Block Selection

  • DVCADDRSHIFT

  • DVCADDRMASK

  • BLKADDRSHIFT

  • BLKADDRMASK

External Write Protection Support

  • WPLOW

  • WPHIGH

  • TD_WP_HOLD

  • TD_WP_SETUP

Software Write Protection Support

  • SWPCMD

  • SWPLOW

  • SWPHIGH

PRE Pin Support

  • PREADDRMASK

  • PREBASE

  • PREBLOCKSIZE

  • TD_PRE_HOLD

  • TD_PRE_SETUP

Log Messages

  • LOG_STARTSTOP

  • LOG_CMDS

  • LOG_ADDRS

  • LOG_DATA

  • LOG_ACKS

  • LOG_EDGES

  • LOG_SWP

  • LOG_OTHER

  • USESIMLOG

Warning Messages

  • WARN_CMDS

  • WARN_ADDRS

  • WARN_TIMING

  • WARN_OTHER

  • USESIMLOG

Model Timing And Verification Of External Signal Timing

  • BYTETIMING

  • TD_BUSFREE

  • TD_CLK_HIGH

  • TD_CLK_LOW

  • TD_CLK_SDO

  • TD_CLK_ACK

  • TD_CLK_ENDDATA

  • TD_CLK_UNACK

  • TD_DATA_SETUP

  • TD_PRE_HOLD

  • TD_PRE_SETUP

  • TD_RSTART_SETUP

  • TD_START_HOLD

  • TD_START_SETUP

  • TD_STOP_SETUP

  • TD_WP_HOLD

  • TD_WP_SETUP

  • TD_WRITE

Model Property Descriptions

The following is an itemized listing of the model properties and includes the units, default value and a brief description of each property.

MEMSIZE

Units | : | Integer.
Default Value | : | None.

This property specifies the size of the memory device in bytes. This property must be specified.

WPAGESIZE

Units | : | Integer.
Default Value | : | None.

This property specifies the maximum number of bytes that can be written to the memory as part of a page write operation. The value must be a positive integer. For devices that do not support a page write mode the property should be defined as one.

Most memory devices organize their internal memory as a table of rows of bytes. For example, a 2k bit (256 byte) device may be organized as 32 rows of 8 bytes. The devices then support a page write mode in which a number of bytes, up to the width of a row, can be written to the device sequentially and then a single erase/write cycle is executed to write all the bytes simultaneously.

RPAGESIZE

Units | : | Integer.
Default Value | : | The value of the MEMSIZE Property.

This property specifies the maximum number of bytes that can be read from the memory as part of a sequential read operation.

Some devices internal architectures mean that the memory is organized in blocks and that sequential read operations cannot traverse a block boundary but instead wrap around to reading the bytes at the start of the block. This property defines, in effect, the size of the internal block for sequential read operations. The default value (the size of the memory) implies there is no limit.

INCADDR

Units | : | Boolean
Default Value | : | Yes.

This property defines whether or not the internal address pointer should be incremented after a single or page write operation. For most devices the default value is correct.

APWAA

Units | : | Integer.
Default Value | : | 0

This property defines an adjustment value for the address pointer when a page write operation is aborted (by a stop condition part way through a byte) and is added to the address pointer increment.

When a paged write operation is aborted most memory devices increment the address pointer by the number of bytes that have been received even though no bytes are written to memory. Some devices (most notably those from ST Microelectronics) increment the address pointer by the number of bytes received minus one. For such a device this property would need to be defined as 1.

ALWAYS_ACK_DATA

Units | : | Boolean
Default Value | : | No.

This property defines whether or not the model acknowledges the write of a data byte when the memory being written is write-protected because one of the software or hardware protection mechanisms are active.

When write-protected, most manufacturers devices will acknowledge a command and address byte but not the data byte. Notably, devices from Arizona Microchip will also acknowledge the data byte even though the byte cannot (and isnt) written. For these latter devices this property needs to be defined Yes.

WPLOW

Units | : | Integer.
Default Value | : | 0

This property defines the lowest memory address protected when the write protection pin (named WP or $WC$) is active.

For most devices the write protect pin protects the entire memory so the default value of zero will be correct. Some devices however may only have half their memory protected (so allowing then to be both RAM and ROM) in which case this property may need to be defined.

For example, for a 256 byte device that only protects its upper 128 bytes (memory 0x80-0xFF), this property would be defined as 128.

WPHIGH

Units | : | Integer.
Default Value | : | The value of the MEMSIZE Property minus one.

This property defines the highest memory address protected when the write protection pin (named WP or $WC$) is active.

For most devices the write protect pin protects the entire memory so the default value of zero will be correct. Some devices however may only have half their memory protected (so allowing then to be both RAM and ROM) in which case this property may need to be defined.

For example, for a 256 byte device that only protects its lower 128 bytes (memory 0x00-0x7F), this property would be defined as 0x7F.

RDWRCMD

Units | : | Integer.
Default Value | : | 0x0A

This property specifies the value of the upper nibble of the command byte for a read/write command. The I2C standard for memory devices indicates that a command byte should always be 0b1010xxxx and hence the default value for this property is 0x0A.

SWPCMD

Units | : | Integer.
Default Value | : | 0x00

This property specifies the value of the upper nibble of the command byte for a Software Write Proptect (SWP) command. If the device doesnt support a SWP command this property should be set to zero (the default).

See the section on Software Write Protection for more information.

SWPLOW

Units | : | Integer.
Default Value | : | 0

This property defines the lowest memory address protected once the Software Write Protect (SWP) register has been written.

For most devices the SWP register protects the entire memory so the default value of zero will be correct. Some devices however may only have half their memory protected (so allowing then to be both RAM and ROM) in which case this property may need to be defined.

See the section on Software Write Protection for more information.

SWPHIGH

Units | : | Integer.
Default Value | : | The value of the MEMSIZE Property minus one.

This property defines the highest memory address protected once the Software Write Protect (SWP) register has been written.

For most devices the SWP register protects the entire memory so the default will be correct. Some devices however may only have half their memory protected (so allowing then to be both RAM and ROM) in which case this property may need to be defined.

See the section on Software Write Protection for more information.

DVCADDRSHIFT

Units | : | Integer.
Default Value | : | 0x01

Specifies the number of bit positions the command byte should be shifted to the left so as to place the least significant bit of the device address at bit zero.

The model obtains the device address from a command byte by first shifting the command word DVCADDRSHIFT bits to the left and then applying the DVCADDRMASK value.

See the section on Device Selection for more information.

DVCADDRMASK

Units | : | Integer.
Default Value | : | 0x07.

Specifies the binary mask to be applied to the command byte after it has been shifted by the DVCADDRSHIFT value to obtain the device address.

The model obtains the device address from a command byte by first shifting the command word DVCADDRSHIFT bits to the left and then applying the DVCADDRMASK value.

For devices that do not support external device selection this value should be set to zero.

See the section on Device Selection for more information.

BLKADDRSHIFT

Units | : | Integer.
Default Value | : | 0x01.

Specifies the number of bit positions the command byte should be shifted to the left so as to place the least significant bit of the a block address at bit zero.

The model obtains the block address from a command byte by first shifting the command word BLKADDRSHIFT bits to the left and then applying the BLKADDRMASK value.

For devices that do not support memory blocks this value should be set to zero.

See the section on Memory Block Selection for more information.

BLKADDRMASK

Units | : | Integer.
Default Value | : | 0x00.

Specifies the number of bit positions the command byte should be shifted to the left so as to place the least significant bit of any block address at bit zero.

The model obtains the block address from a command byte by first shifting the command word BLKADDRSHIFT bits to the left and then applying the BLKADDRMASK value.

For devices that do not support memory blocks this value should be set to zero.

See the section on Memory Block Selection for more information.

CMDWIDTH

Units | : | Integer.
Default Value | : | 8

Specifies the number of bits in a command word. The default value is correct for all I2C memories and there should be no reason to change it.

ADDRWIDTH

Units | : | Integer.
Default Value | : | 8

Specifies the number of valid bits in an address word.

After receiving the command word the model expects one or two address bytes. If the ADDRWIDTH property is greater than eight then a two byte address is expected (the most significant byte first, least significant byte second); otherwise only a single address byte is expected.

The received address word is masked by the number of bits specified in the ADDRWIDTH property before any block selection bits are placed in the upper bits.

For most standard I2C memories which use all of the address byte (plus one or more block select bits in the command word), the default value is correct. However, newer memories that use an extended address of two bytes the property should be assigned a value equal to the number of valid bits in the address. For example, the ST24E16 memory is a 16k-bit (2k byte) memory that uses and 11-bit address and for this device the ADDRWIDTH property would be set to 11.

See the section on Memory Block Selection for more information.

DATAWIDTH

Units | : | Integer.
Default Value | : | 8

Specifies the number of bits in a data word. The default value is correct for all I2C memories and there should be no reason to change it.

PREADDRMASK

Units | : | Integer.
Default Value | : | 0xF0

For a memory device with a PRE pin this property defines the mask value used against the value in last memory byte when determining the protected memory base address.

See the section on PRE Pin Support for more information.

PREBASE

Units | : | Integer.
Default Value | : | None.

For a memory device with a PRE pin this property defines the base address from which the protected memory base address is offset.

See the section on PRE Pin Support for more information.

PREBLOCKSIZE

Units | : | Integer.
Default Value | : | None.

For a memory device with a PRE pin and one or protection block select (PB0 and PB1) pins, this property defines the size of the protection block selected by the PBx pins.

See the section on PRE Pin Support for more information.

USESIMLOG

Units | : | Integer.
Default Value | : | None.

When this property is defined Yes then ordinary information messages are placed in the main (Proteus VSM) simulation log as well as the memory models private log window.

You should note that:

  • Information messages are automatically placed in the main simulation log when a non-interactive (i.e. graph-based) simulation is run as no popup windows can be used for this type of simulation.

  • Warning and error messages are always placed in both the memory models own log window and the main simulation log.

List of all Log Properties

Log, Warning and Error Messages

LOG_STARTUP

Units | : | Boolean
Default Value | : | No.

This property controls whether or not the model issues information messages concerning the reception of start and stop conditions.

List of all Log Properties

Log, Warning and Error Messages

LOG_SWP

Units | : | Boolean
Default Value | : | No.

This property controls whether or not the model issues information messages concerning the Software Write Protection functionality.

List of all Log Properties

Software Write Protection

Log, Warning and Error Messages

LOG_CMDS

Units | : | Boolean.
Default Value | : | No.

This property controls whether or not the model issues information messages concerning the reception and handling of command words.

List of all Log Properties

Log, Warning and Error Messages

LOG_ADDRS

Units | : | Boolean.
Default Value | : | No.

This property controls whether or not the model issues information messages concerning the reception and handling of address words.

List of all Log Properties

Log, Warning and Error Messages

LOG_DATA

Units | : | Boolean.
Default Value | : | No.

This property controls whether or not the model issues information messages concerning the reception, transmission and general handling of data words.

List of all Log Properties

Log, Warning and Error Messages

LOG_ACKS

Units | : | Boolean.
Default Value | : | No.

This property controls whether or not the model issues information messages concerning the reception and generation of acknowledge bits.

List of all Log Properties

Log, Warning and Error Messages

LOG_EDGES

Units | : | Boolean.
Default Value | : | No.

This property controls whether or not the model issues information messages concerning edge transitions on SCK and other pins are generated.

List of all Log Properties

Log, Warning and Error Messages

LOG_OTHER

Units | : | Boolean.
Default Value | : | No.

This property controls whether or not the model issues information messages concerning all other conditions not controlled by other LOG_xxx properties.

List of all Log Properties

Log, Warning and Error Messages

WARN_TIMING

Units | : | Boolean.
Default Value | : | Yes.

This property controls whether or not the model issues warnings about invalid timing.

List of all Warn Properties

Log, Warning and Error Messages

WARN_CMDS

Units | : | Boolean.
Default Value | : | Yes.

This property controls whether or not the model issues warnings about invalid command words.

List of all Warn Properties

Log, Warning and Error Messages

WARN_ADDRS

Units | : | Boolean.
Default Value | : | Yes.

This property controls whether or not the model issues warnings about invalid address words.

List of all Warn Properties

Log, Warning and Error Messages

WARN_OTHER

Units | : | Boolean.
Default Value | : | Yes.

This property controls whether or not the model issues warnings about other conditions not specifically enabled/disabled by other WARN_xxx properties.

List of all Warn Properties

Log, Warning and Error Messages

TD_WRITE

Units | : | Integer.
Default Value | : | None.

This is the time taken by the device to perform an erase/write operation. This property must be defined.

If the BYTETIMING property is set FALSE then this time is the write time for any write regardless of whether it is a single or paged write operation. If the BYTETIMING property is TRUE then this time is the timer per byte and, for example, for a paged write of say, six bytes, the write time will be six times this value.

The time is measured from the time of the stop condition following the write command. During this time the model will not acknowledge any command words.

Timing Diagram.

Memory Timing.

TD_CLK_SDO

Units | : | Seconds.
Default Value | : | None.

For a memory read operation, this is the time delay between a negative clock edge on SCL and the device driving data on to SDA. This property must be defined.

Timing Diagram.

Memory Timing.

TD_CLK_ACK

Units | : | Seconds.
Default Value | : | TD_CLK_SDO

This is the time delay between the negative clock edge on SCL after the last bit has been written to the device and the device driving the SDA pin as part of the acknowledge bit.

Timing Diagram.

Memory Timing.

TD_CLK_UNACK

Units | : | Seconds.
Default Value | : | TD_CLK_SDO

This is the time delay between the positive clock edge on SCL at the end of an acknowledge bit and the memory device releasing the SDA pin.

Timing Diagram.

Memory Timing.

TD_CLK_ENDDATA

Units | : | Seconds.
Default Value | : | TD_CLK_SDO

This is the time delay between the positive clock edge on SCL at the end of an acknowledge bit and the memory device releasing the SDA pin.

Timing Diagram.

Memory Timing.

TD_CLK_HIGH

Units | : | Seconds.
Default Value | : | 0

The minimum time the SCK pin must be high. This time is verified by the model and a warning issued for any violation.

Timing Diagram.

Memory Timing.

TD_CLK_LOW

Units | : | Seconds.
Default Value | : | 0

The minimum time the SCK pin must be low. This time is verified by the model and a warning issued for any violation.

Timing Diagram.

Memory Timing.

TD_RSTART_SETUP

Units | : | Seconds.
Default Value | : | 0

The minimum time between a repeated start condition and the previous positive edge on SCK. This time is verified by the model and a warning issued for any violation.

Timing Diagram.

Memory Timing.

TD_START_SETUP

Units | : | Seconds.
Default Value | : | None.

The minimum time between a start condition and the previous positive edge on SCK. This time is verified by the model and a warning issued for any violation.

Timing Diagram.

Memory Timing.

TD_START_HOLD

Units | : | Seconds.
Default Value | : | 0

The minimum time a start condition and the following negative edge on SCK that marks the start of the first data bit. This time is verified by the model and a warning issued for any violation.

Timing Diagram.

Memory Timing.

TD_STOP_SETUP

Units | : | Seconds.
Default Value | : | 0.

The minimum time between a stop condition and the previous positive edge on SCK. This time is verified by the model and a warning issued for any violation.

Timing Diagram.

Memory Timing.

TD_DATA_SETUP

Units | : | Seconds.
Default Value | : | 0.

When data (a command, address or data word) is being written to the device this is the minimum time between a change on the SDA pin and the following positive edge on SCK that clocks the data in. This time is verified by the model and a warning issued for any violation.

Timing Diagram.

Memory Timing.

TD_WP_SETUP

Units | : | Seconds.
Default Value | : | 0.

The minimum time between any change on the WP (or similar write control/protect) pin and a stop condition that marks the end of a memory write operation. This time is verified by the model and a warning issued for any violation.

Timing Diagram.

Memory Timing.

TD_WP_HOLD

Units | : | Seconds.
Default Value | : | 0.

The minimum time after a stop condition that initiates an erase/write cycle and any change in the WP (or similar write control/protect) pin. This time is verified by the model and a warning issued for any violation.

Timing Diagram.

Memory Timing.

TD_PRE_SETUP

Units | : | Seconds.
Default Value | : | 0.

The minimum time between any change on the PRE pin and a stop condition that initiates an erase/write cycle. This time is verified by the model and a warning issued for any violation.

Timing Diagram.

Memory Timing.

TD_PRE_HOLD

Units | : | Seconds.
Default Value | : | 0.

The minimum time after a stop condition that initiates an erase/write cycle and any change in the PRE pin. This time is verified by the model and a warning issued for any violation.

Timing Diagram.

Memory Timing.

TD_BUSFREE

Units | : | Seconds.
Default Value | : | 0.

This is the minumum time between a stop condition (positive edge on SDA whilst SCK is high) and a start condition. This time is verified by the model and a warning issued for any violation.

Timing Diagram.

Memory Timing.

BYTETIMING

Units | : | Boolean
Default Value | : | No

If set to FALSE (the default) then the length of an erase/write cycle (specified by the TD_WRITE property) is independent of the number of bytes being written and is fixed at TD_WRITE per erase/write cycle.

If set to TRUE then the length of erase/write cycle will be the TD_WRITE per byte written. For example, if a paged write operation writes four bytes to memory then the erase/write cycle takes 4*TD_WRITE to complete.

Timing Diagram.

Memory Timing.


ModellingNewDevice

MODELLING NEW DEVICES

Introduction

In order to use the I2C Memory model to model a new device you need to perform two operations :

  • Draw out a new schematic device in ISIS. The new device must have pins with the correct electrical type and name.

  • Make the device (using the Make Device command on the Library Menu) and ensure values are assigned to various device properties. The device properties to be assigned fall in to two categories: those required by VSM to link the schematic part to the model (System Properties) and those required by the model itself to determine its behaviour (Model Properties). These are discussed in more detail in the following sections.

System Properties

The simulation properties that need to be defined are the PRIMITIVE, MODDLL, ITFMOD and MODDATA properties, and should be added as follows :

PRIMITIVE=DIGITAL

MODDLL=I2CMEM.DLL

ITFMOD=I2CMEM

MODDATA=???,255

These tell Proteus that the part is a digital part, which DLL contains the VSM model, the name of the interface model (that defines the electrical interface of pins) and how persistent storage should be allocated for the model's use. Note that the value used in the MODDATA property (indicated by question marks above) should be the same as that specified by the model's MEMSIZE property (see below). All these properties are all covered in detail in the Proteus VSM documentation.

Model Properties

There are a large number of properties used to configure the model's behaviour (the section Model Properties contains a complete list). The following, however, should act as a guide to which properties need defining:

  • The MEMSIZE, WPAGESIZE, TD_CLK_SDO and TD_WRITE properties must be defined. There are no default values for these properties.

  • If the device uses extended (two byte) addresses then you need to define the ADDRWIDTH property according to the number of bits in the two byte address that are used.

  • If the device is a ST Microelectronics™ device you may need to define the APWAA property.

  • If the device is a Microchip Technologies™ device with a WP pin you may need to define the ALWAYS_ACK_DATA property.

  • If you are modelling a device with a write protect pin that only write protects part of the memory then you need to define the WPLOW and WPHIGH properties

  • If the device has a PRE pin (usually only devices from ST Microelectronics) then you will need to define the PREADDRMASK property. If the device also has PB0/PB1 pins then you will also need to define the PREBASE and PREBLOCKSIZE properties.

  • If you want the model to perform validation of signals generated by the master, then you should define one or more of the timing properties.

Having made the device you should now be able to place it on the schematic, wire it up and simulate it.


PIN NAMES

It is important for the schematic device to have it’s pins correctly named and electrically typed. For some pins the model supports more than one name in which case any name can be used as appropriate to the device and/or manufacturer.

The following table defines pin functions, ISIS electrical type and name(s).

I2C Clock | SCL or SCK or CLK | Input
I2C Data | SDA or DATA | I/O
Hardware Write Protection | WP or $WC$ | Input
First Device Select Pin | A0 or E0 or E | Input
Second Device Select Pin | A1 or E1 | Input
Third Device Select Pin | A2 or E2 | Input
First PRE Block Select Pin | PB0 | Input
Second PRE Block Select Pin | PB1 | Input

All '0' characters are zeroes.


PRE PIN SUPPORT

Introduction

The model supports the behaviour of the PRE pin as used on some memory devices manufactured by ST Microelectronics.

On these devices if the PRE pin is held high, and the bit 2 in the last byte of the EEPROM contains a zero, part of EEPROM becomes write protected and behaves like ROM. The remaining area continues to function as unprotected EEPROM. The protected region extends from the address pointed to by the most significant bits in the last byte up to and including the last byte of the memory.

Configuring the Model

To use the PRE pin functionality the model must be configured as follows:

  • The schematic device must have a pin named PRE. This is the Protection Enable pin.

  • The schematic device may have zero, one or two Protection Block select pins named PB0 and PB1.

  • The PREADDRMASK must be set to determine which bits of the last memory address are used to form the address pointer. This mask is applied directly to the last memory byte (without any bit shifts) to determine the first address of the protected memory. For example, a PREADDRMASK value of 0b11111000 (0xF8) indicates that the device can protect up to thirty-two blocks of eight bytes each.

  • The PREBASE property must be set to define the base address from which protected memory blocks start. For small memory devices this is usually zero but for larger devices this may well be half the memory size so allowing only the top half of the memory to be write protected.

  • The PREBLOCKSIZE property is set to the size of the blocks selected by the PB0 and PB1 pins, if present.

PRE Pin Functionality

The device models the PRE Pin functionality as follows :

  • If the PRE pin is active and bit 2 (0b00000100) of the last byte of the memory is clear then the protection mechanism is active and all or part of the memory will be protected. If the PRE pin is inactive or bit 2 (0b00000100) of the last byte of the memory is set then the protection mechanism is inactive and all of the memory can be both read or written.

  • When the memory protection mechanism is active all memory at and above a base address, up to and including the last memory byte, is protected. Memory below the base address behaves as normal read/write memory.

  • The protected memory base address is calculated as follows:

    PREBASE + (PB0*PBLOCKSIZE) + (PB1*2*PBLOCKSIZE) + (LASTBYTE & PREADDRMASK)

    Where:
    PREBASE, PREADDRMASK     and PREBLOCKSIZE are the values of the respective properties,
    PB0 and PB1 are 0 if the associated PB0 and PB1 pins are not present or are inactive; PB0 and PB1 are 1 if the pins are present and active,
    LASTBYTE is the value in the last byte of the memory.
    The plus (+) character presents an integer addition, the asterisk (*) character an integer multiplication and the ampersand (&) character a bit-wise AND operation

Example

An example of the modelling of the ST24W16 device (a 2k memory device) is shown below:

PRE | 0x07FF | PB1 | PB0 | Protected Memory
0 | xxxxxxxx | x | x | None
X | xxxxx1xx | x | x | None
1 | 00000000 | 0 | 0 | 0x0400-0x07FF
1 | ... | 0 | 0 | ...
1 | 11110000 | 0 | 0 | 0x04F0-0x07FF
1 | 00000000 | 0 | 1 | 0x0500-0x07FF
1 | ... | 0 | 1 | ...
1 | 11110000 | 0 | 1 | 0x05F0-0x07FF
1 | 00000000 | 1 | 0 | 0x0600-0x07FF
1 | ... | 0 | 1 | ...
1 | 11110000 | 1 | 0 | 0x06F0-0x07FF
1 | 00000000 | 1 | 1 | 0x0700-0x07FF
1 | ... | 1 | 1 | ...
1 | 11110000 | 1 | 1 | 0x07F0-0x07FF

An 'x' indicates a 'dont care' value.


SOFTWARE WRITE PROTECTION

The I2C memory model supports an a software write protect (SWP) function whereby the memory becomes write-protected (i.e. read-only) when a write operation occurs with a unique command byte.

To enable this functionality in the model the SWPCMD property should be set to the value expected in the upper nibble of the command byte for the software write protect command. For example, if the SWP command byte is of the form 0b0110xxxx then the SWPCMD property would be defined as 0x06.

The memory model will only enable memory protection given the following conditions:

  1. A command byte is received where the value in the upper nibble of the command byte is equal to the value of the SWPCMD property.
  2. The SWPCMD lower nibble of the command byte must contain the correct device address if this is enabled on the device being modelled (see Device Selection).
  3. The RD/WR bit of the command byte must be set for a write operation (bit zero must be clear).
  4. A complete and proper write sequence must be performed. The value of the address and data bytes is ignored by the model.
  5. The memory is not protected by any hardware protection mechanism.

Note that model only supports the enabling of the Software Write Protect (SWP) function – once activated the memory can only be read and write protection cannot be disabled.

The range of memory protected by the SWP function defaults to the entire memory. However the range can be restricted using the SWPLOW and SWPHIGH properties. These two properties respectively define the first and last byte of the range of memory protected by the SWP function. For example, a 256 byte memory where only the upper half of the memory is protected would have SWPLOW defined as 0x80 and SWPHIGH as 0xFF.


TIMING DIAGRAM