Introduction

Introduction

The HC11 microprocessor model can be used to simulate the MC68HC11A8 and MC68HC11E9 variants of the popular Motorola Micro-controller. Support for other HC11 variants may be added in the future - please tell us what you are using.

The entire instruction set and full range of peripherals are modelled with timing simulated accurately to within at least one machine cycle and generally one clock cycle. Full speed (real time) operation may be achieved on a 600MHz or faster Pentium PC.

The MC68HC11 Datasheet contains full details of how to program the HC11 processor.

Properties

The HC11 model supports the following properties:

Property | Defaults | Description
PROGRAM | - | Specifies one or more program files to be loaded into the model's internal code memory. The file extension must be specified as it is used to determine the file format. Use commas to separate multiple file names. See Specifying The Program File for more information.
CLOCK | 8MHz | Specifies the clock frequency of the processor. For reasons of efficiency, the clock circuitry is not simulated, and the clock rate of the processor is determined solely by this value.
DBG_STOP | TRUE | Causes the model to suspend the simulation when a STOP instruction is encountered.
DBG_FETCH | FALSE | If TRUE, causes the model to simulate external program fetches when operating in expanded mode. This mode of operation is extremely slow, but will allow you to test external program memory decode circuitry.
DBG_ECYCLE | FALSE | If TRUE, the model drives the E pin high and low during every machine cycle. Otherwise the E pin is only driven when external memory locations are accessed in expanded mode. Driving the E pin at the machine cycle rate reduces the simulation speed by at least 50%, as two extra simulation events will be created on every machine cycle.
DBG_PORDELAY | FALSE | If TRUE, the model simulates the 4064 cycle reset/power on delay. Otherwise, the model executes the reset/vector sequence as soon as it sees that RESET is logic high.
DBG_ADCBREAK | FALSE | If TRUE, the model forces a mixed mode simulation breakpoint each time the ADC needs to sample an input voltage. Otherwise, the model interpolates the sample value. This generally very accurate, unless your program does things which could affect the analogue input voltages seen by the ADC. If the ADC is running in continuous mode, setting this option will dramatically slow down the simulation.
DBG_VECTOR | 0 | If equal to 1, the model will write a message to the simulation log each time an interrupt is honoured. If equal to 2, the model will suspend the simulation whenever an interrupt is about to be honoured.
EXTROM | - | Specifies regions of the memory map that correspond to external ROM. This allows for much faster simulation of external memory accesses. See Modelling the Memory Map for more information.
EXTRAM | - | Specifies regions of the external memory map that correspond to external RAM.. See Modelling the Memory Map for more information.
CONFIG | OF | Initial value for the CONFIG register.


IAR UBROF LOADER

The UBROF format is owned by IAR Systems and is a common symbolic debug format used across the entire range of IAR compiler products.

UBROF files for the HC11 have the extension '.D07' and contain full symbolic debug information including source line address and variable data. To load a UBROF file into the model, you will need to set the program property with the full filename and extension. e.g.

PROGRAM=MYFILE.D07

Note that the UBROF file contains absolute paths to the 'C' source files, and problems may arise if the project is moved from one directory to another. The solution is to re-compile the project within IAR workbench.


MODELLING THE MEMORY MAP

The MC68HC11 can operate in one of two basic modes: Single Chip Mode and Expanded Mode. In single chip mode, the issue of simulating external memory does not arise, but in expanded mode it is quite common to have external RAMs, ROMs or EPROMs present within the memory map.

By default, all external memory accesses are fully modelled. That is to say that each external memory cycle involves simulating the numerous transitions of E, AS, R/W and PORTB/C. A typically cycle will involve around 50 pin state transitions and is thus vastly expensive in terms of simulation time.

In contrast, all program op-code fetches from the internal ROM are simulated internal to the HC11 model - that is to say that the program bytes are looked up in a memory buffer internal to the chip and no pin-state transitions are simulated. This optimization can be disabled by specifying.

DBG_FETCH=FALSE

For applications which make extensive use of external memory, two further optimisations can be specified:-

EXTROM Property

This specifies regions of the external memory map which can be treated as ROM and simulated internally to the HC11 model. A typical example would be:

EXTROM=4000-7FFF,C000-DFFF

This would specify two regions of external ROM memory.

EXTRAM Property

Similarly, external RAM can be simulated internally to the model by specifying:

EXTRAM=0000-7FFF

Any external memory writes to the region 0000-7FFF will then modify a data buffer internal to the HC11 model only and will not be seen by external circuitry.


SPECIFYING THE PROGRAM FILE

The HC11 model can load program data from Motorola S19 format files and IAR UBROF files. The latter file format contains full symbolic debug information and allows for source level debugging of programs written with IAR's 'C' compiler for the HC11.

You can specify more that one file within the PROGRAM property as in:

PROGRAM=FILE1.S19,FILE2.S19

Note that only the first source file will be loaded into a source code popup window.