Introduction

CORTEX-M3 MODEL HELP

Device Support

The Cortex-M3 model includes variant support for the following LM3S, ATSAMx, NXP and STM32 microcontrollers:

LM3S300 | LM3S301 | LM3S308 | LM3S310
LM3S315 | LM3S316 | LM3S317 | LM3S328
LPC1342FBD48 | LPC1343FHN33 | LPC1343FBD48 |
LPC1311FHN33 | LPC1313FHN33 | LPC1313FBD48 | LPC1342FHN33
ATSAM3N00A | ATSAM3N00B | ATSAM3N0A | ATSAM3N0B
ATSAM3N0C | ATSAM3N1A | ATSAM3N1B | ATSAM3N1C
ATSAM3N2A | ATSAM3N2B | ATSAM3N2C | ATSAM3N4A
ATSAM3N4B | ATSAM3N4C | STM32F103R6 | STM32F103T6
STM32F103C4 | STM32F103R4 | STM32F103T4 | STM32F103C6

Each processor is packaged per the datasheet with one or more of QFP, QFN, TQFP, PQFN or LGA footprints.

Datasheets for each device are available via the Data button on the Edit component dialogue form of the device. Please check the Texas Instruments website (www.ti.com) for the latest information and errata on these devices.

See Also:

  • Getting Started - Compiler Support and Integration
  • Model Properties
  • General Model Limitations
  • Internal Debug Module

This help file last modified 29th March 2017.


Limitations

MODEL LIMITATIONS

General Model Limitations

The following summarises the limitations in the model, correct at the time of writing:

General

  1. Bitband alias regions are of type XN (Execute Never). Fetches from these regions are invalid.
  2. Cache information is not used.
  3. SysTick Calibration value Register (SYST_CALIB) is ignored.
  4. Alignment of memory accesses is not analyzed
  5. Data Barrier instructions (DMB, DSB) are treated as NOP.
  6. Simulations are unlikely to run in real time with high clock speeds. This will affect performance but not accuracy of simulation.

System Control

  1. Register PLLCFG is not modeled
  2. Reference to unknown RCC2 register is not modeled - it exists in fact but is not described in the datasheet
  3. Clock Verification Timers are not modeled.
  4. Internal brown-out (BOR) detector is not implemented.

GPIO

  1. Register ODR is dummy – writing doesn’t change the model behavior.
  2. Registers DR2R, DR4R, DR8R, SLR are not modeled.

I2C Module

  1. Loopback feature is not modeled due to lack of information


Loaders

COMPILER SUPPORT & INTEGRATION

The ARM Cortex model can load program files in ELF/DWARF debug formats as well as the exact same hex file that you would program a physical device with. The advantage of the debug format is that it contains symbolic debug information (source code, variables,etc.) which enables you to not only simulate your system in Proteus but also to single step debug. The following is a summary of supported formats with basic instructions on how to get started.

See Also:

Proteus VSM Tutorial

VSM Studio IDE

By far the easiest way to get set up for simulating in Proteus is through the integrated VSM Studio IDE. This tool is integrated into the Proteus Design Suite, will detect installed compilers and you can directly download and install additional tools from inside the IDE.

Installed compilers are automatically configured by VSM Studio to produce debugging output suitable for driving Proteus VSM. If however you need to make changes all of the compiler options are made available in the Project Setting dialogue inside VSM Studio.

Once you have written some code and compiled your schematic will automatically be programmed with the firmware. You can then both simulate and single step debug inside VSM Studio. Active popups let you add 'schematic snippets' to VSM Studio so that you can view and interact with the simulation while debugging the source code.

See Also:

VSM Studio Tutorial (New Project)

Schematic Only

If you choose or prefer to work in your own IDE and use Proteus VSM only for simulation then several debug formats are available. The process in each case is to produce the required debug file from your compiler and then to load this file as the PROGRAM property in the Edit Component dialogue form of the PIC microcontroller.

ELF/DWARF

The ELF/DWARF format for Cortex-M3 is a public domain symbolic debug format used by GCC Compilers and others.

ELF files '.ELF' and contain full symbolic debug information including source line address and variable data. To load ELF/DWARF files into the model, you will need to set the program property with the full filename and extension. e.g.

PROGRAM=MYFILE.ELF

Note that the ELF file contains absolute paths to the 'C' source files, and problems may arise if the project is moved from one directory to another. The corresponding DWARF file should be in the same directory as the ELF file.

HEX

Failing all else, simply specify the HEX file as the program property for the processor on the schematic. This will simulate but will not single step debug as there is not enough information to provide a source window.


Properties

MODEL PROPERTIES

The following is a list of the properties available for configuration in the CM3 Models:

Program Property

This property specifies the name of the program file that will be loaded into the model. The file should be either Intel Hex (.HEX) or ELF (.ELF) format. The file extension must be specified as this is used to determine the format of the program file.

Crystal Frequency

This property specifies the main clock frequency of the processor. For reasons of efficiency, you can set this parameter to appropriate value other than 0, but in this case modifying registers of the SYSCTRL Module will not affect this frequency.

Setting this value other than 0, you should not use of PLL registers (especially tuning system frequency), because in this case the SYSCTRL Module is bypassed.

Disassemble Binary Code

This property controls internal disassembler behavior. It can be useful if you want trace librarian code or inspect code flow (every instruction) since processor started. If this feature is disabled and user press “Start Debug”, program run till first source line. Otherwise, if this feature is enabled, execution stops at the first instruction after Power-On-Reset.

Warning Messages

The LM3S3XX model may issue a warning message when it detects illegal or ambiguous behavior. The display of messages is controlled by “Configure Diagnostics”.

A list of all warnings issue by the model are listed below.

Unresolved address 0x12345678

There is no peripheral module having specified address.

Unknown target bus for address 0x12345678

Recipient of the bus transaction owns specified address is not found.

Invalid register request at 0x12345678

There is no known peripheral register at specified address.

Unpredictable memory region cross while writing

Instruction tries to access to different peripheral modules at the same time.

Access to register of unclocked peripheral at 0x12345678 cause BUS_FAULT

Instruction at PC=0x12345678 tries to access to peripheral module whilst it is disabled. The BUSFAULT exception is raised.

Stack frame integrity failed

Stack integrity mechanism works with exception processing and can detect erroneous stack writes in handler routines

Invalid access

Write access to read-only memory region.

Oscillator source is Main Oscillator (disabled)

Main oscillator is selected as a clock source, but it is disabled (RCC.MOSCDIS =1).

Oscillator source is Internal Oscillator (disabled)

Internal oscillator is selected as a clock source, but it is disabled (RCC.IOSCDIS =1).

RCC.OSCSRC = 3 (reserved value)

The bitfield RCC.OSCSRC has reserved value and can lead to undocumented behavior.


InternalDebug

INTERNAL DEBUG MODULE

In addition to source level debugging, model diagnostic messaging and other standard debugging windows, the Cortex-M3 module incorporates an internal debugging module which allows you to send messages to the ISIS simulation log from your firmware. This is implemented as a single read/write register (at address 0xFFFFFF00). the user would write some text to this address with a trailing zero and the text would then be displayed in the simulation log window.

Typical Usage:

#ifdef TARGET_PROTEUS

void print_str(const char* s)

{ char* dbgout = (char*) 0xFFFFFF00; // Addressing the debugging module

while(*s)

{ *dbgout = *s;

++s;

}

*dbgout = 0; // Trailing zero – required!

}

#endif