Introduction

CORTEX™-M0 MODEL HELP

Device Support

The Cortex-M0 model includes variant support for the following NXP ARM® microcontrollers:

LPC1110 | LPC1111 | LPC1112 | LPC1113
LPC1114 | LPC1115 |  |

These microcontrollers are available individually and can be selected with following packages: HVQFN with 33 pins (FHN suffix), LQFP with 48 pins (FBD suffix), SO with 20 pins (FD suffix), TSSOP with 20 pins (FDH suffix).

Please check the NXP Semiconductors website (www.nxp.com) for the latest information on these devices.

See Also:

  • Getting Started - Compiler Support and Integration
  • Model Properties
  • General Model Limitations
  • Internal Debug Module

This help file last modified 15 Sept 2014.


Limitations

MODEL LIMITATIONS

General Model Limitations

For reasons of efficiency some modules have several limitations:

Common

1. Bitband alias regions are of type XN (Execute Never). Fetches from these regions are invalid.

2. Cache information is not used.

3. SysTick Calibration value Register (SYST_CALIB) is ignored.

4. Alignment of memory accesses is not analyzed

5. Data Barrier instructions (DMB, DSB) are treated as NOP.

6. Power monitoring and Brown-Out Detection circuit are not implemented.

7. Flash programming firmware is not supported.

LPC111X specific

1. Hysteresis bit CONIO.HYST is not modeled.


Loaders

COMPILER SUPPORT & INTEGRATION

The ARM® Cortex™ model can load program files in ELF/DWARF debug formats as well as the exact same hex file that you would program a physical device with. The advantage of the debug format is that it contains symbolic debug information (source code, variables,etc.) which enables you to not only simulate your system in Proteus but also to single step debug. The following is a summary of supported formats with basic instructions on how to get started.

See Also:

Proteus VSM Tutorial

VSM Studio IDE

By far the easiest way to get set up for simulating in Proteus is through the integrated VSM Studio IDE. This tool is integrated into the Proteus Design Suite, will detect installed compilers and you can directly download and install additional tools from inside the IDE.

Installed compilers are automatically configured by VSM Studio to produce debugging output suitable for driving Proteus VSM. If however you need to make changes all of the compiler options are made available in the Project Setting dialogue inside VSM Studio.

Once you have written some code and compiled your schematic will automatically be programmed with the firmware. You can then both simulate and single step debug inside VSM Studio. Active popups let you add 'schematic snippets' to VSM Studio so that you can view and interact with the simulation while debugging the source code.

See Also:

VSM Studio Tutorial (New Project)

Schematic Only

If you choose or prefer to work in your own IDE and use Proteus VSM only for simulation then several debug formats are available. The process in each case is to produce the required debug file from your compiler and then to load this file as the PROGRAM property in the Edit Component dialogue form of the PIC microcontroller.

ELF/DWARF

The ELF/DWARF format for Cortex-M3 is a public domain symbolic debug format used by GCC Compilers and others.

ELF files '.ELF' and contain full symbolic debug information including source line address and variable data. To load ELF/DWARF files into the model, you will need to set the program property with the full filename and extension. e.g.

PROGRAM=MYFILE.ELF

Note that the ELF file contains absolute paths to the 'C' source files, and problems may arise if the project is moved from one directory to another. The corresponding DWARF file should be in the same directory as the ELF file.

HEX

Failing all else, simply specify the HEX file as the program property for the processor on the schematic. This will simulate but will not single step debug as there is not enough information to provide a source window.


Properties

MODEL PROPERTIES

The following is a list of the properties available for configuration in the CM0 Models:

Program Property

This property specifies the name of the program file that will be loaded into the model. The file should be either Intel Hex (.HEX) or ELF (.ELF) format. The file extension must be specified as this is used to determine the format of the program file.

Crystal Frequency

This property specifies the main clock frequency of the processor. For reasons of efficiency, you can set this parameter to appropriate value other than 0, but in this case modifying registers of the SYSCTRL Module will not affect this frequency.

Setting this value other than 0, you should not use of PLL registers (especially tuning system frequency), because in this case the SYSCTRL Module is bypassed.

Disassemble Binary Code

This property controls internal disassembler behavior. It can be useful if you want trace librarian code or inspect code flow (every instruction) since processor started. If this feature is disabled and user press “Start Debug”, program run till first source line. Otherwise, if this feature is enabled, execution stops at the first instruction after Power-On-Reset.

Warning Messages

The LPC111X model may issue a warning message when it detects illegal or ambiguous behavior. The display of messages is controlled by “Configure Diagnostics”.

A list of all warnings issue by the model are listed below.

Capture mode selected but CCR != 0

Invalid bit combination in the CCR register of the Counter/Timer 16/32.

Invalid value for PCON register

The PMU detects invalid bit combination in the PCON register.

Invalid Data Size: SSPCR0.DSS

The SPI module requires data size of 3 or greater.

Params are modified whilst SSICR1.SSE = 1

Software should write the appropriate control information to the other SPI/SSP registers and interrupt controller registers, before setting this bit.

Invalid frame format

Software should select the SPI, TI or Microwire frame format for SPI transmission.

CPSR should be > 1

The SPI clock prescaler value should be between 2 and 254 (even numbers only).

Invalid bits combination. Source: IER.Reserved[4..6]

The UART register IER contains invalid bit combination.

Registers Window

While the CM0 model makes use of all of the debugging windows in Proteus VSM, the registers window is customized to the processor. The window “Registers” shows current values for general purpose registers. Red color depicts that value has been changed. Also you can see the current mode: Privileged or User, Thread or Handler.

  • MSP – main stack pointer;
  • PSP – program stack pointer;
  • sign «*» denotes the register currently used as the active stack pointer;
  • IRQ – active interrupt request being processed;
  • Pri – current priority level divided to group priority and sub-group priority.
  • The APSR register value is detailed (magenta color)


InternalDebug

INTERNAL DEBUG MODULE

In addition to source level debugging, model diagnostic messaging and other standard debugging windows, the Cortex-M0 module incorporates an internal debugging module which allows you to send messages to the ISIS simulation log from your firmware. This is implemented as a single read/write register (at address 0xFFFFFF00). the user would write some text to this address with a trailing zero and the text would then be displayed in the simulation log window.

Typical Usage:

#ifdef TARGET_PROTEUS

void print_str(const char* s)

{ char* dbgout = (char*) 0xFFFFFF00; // Addressing the debugging module

while(*s)

{ *dbgout = *s;

++s;

}

*dbgout = 0; // Trailing zero – required!

}

#endif