Introduction

AVR MODEL HELP

Device Support

The Proteus VSM AVR Model can simulate the behaviour of the following microcontrollers from Atmel:

AT90S1200 | AT90S2313 | AT90S2323 | AT90S2333 | AT90S2343 | AT90S4433
AT90S4434 | AT90S8515 | AT90S8535 | AT90USB646 | AT90USB1286 | ATMEGA8 (32 Pin)
ATMEGA16 | ATMEGA16U4 | ATMEGA32 | ATMEGA32U4 | ATMEGA48 | ATMEGA48P
ATMEGA64 | ATMEGA88 | ATMEGA88P | ATMEGA103 | ATMEGA128 | ATMEGA162
ATMEGA164P | ATMEGA165 | ATMEGA165P | ATMEGA168 | ATMEGA168P | ATMEGA169
ATMEGA169P | ATMEGA324P | ATMEGA325 | ATMEGA325P | ATMEGA328P | ATMEGA329
ATMEGA329P | ATMEGA640 | ATMEGA644 | ATMEGA644P | ATMEGA645 | ATMEGA649
ATMEGA1280 | ATMEGA1281 | ATMEGA1284P | ATMEGA2560 | ATMEGA2561 | ATMEGA3250
ATMEGA3250P | ATMEGA3290 | ATMEGA3290P | ATMEGA6450 | ATMEGA6490 | ATMEGA8515
ATMEGA8535 | ATTINY10 | ATTINY11 | ATTINY12 | ATTINY13 | ATTINY15
ATTINY24 | ATTINY25 | ATTINY44 | ATTINY45 | ATTINY48 (32 Pin) | ATTINY84
ATTINY85 | ATTINY88 (32 Pin) | ATTINY261 | ATTINY461 | ATTINY861 | ATTINY2313

Datasheets for these devices can be viewed by placing and editing the device on the schematic and then clicking on the datasheet button from the resulting Edit Component dialogue form. The letter suffix for individual part indicates revisions of the part and we have modelled devices based on a particular revision.

Please check the Atmel website for the latest information and errata on particular devices.

For a guided tour on Proteus VSM for Arduino™ AVR please watch our tutorial movie on our website or on the YouTube Channel

Compiler Support

Source Level Debugging is supported

  • for the Imagecraft and CodeVision ‘C’ Compilers, through a COFF Loader.
  • for the WINAVR / GNU compilers through an ELF/DWARF loader.
  • for the IAR 'C' Compiler through a UBROF Loader.

See Also:

  • VSM Studio IDE : Support and Integration
  • Loaders
  • Model Properties
  • General Model Limitations
  • Mega 8/16/32 Model Limitations
  • Mega 64/128 Model Limitations

This help file last modified 06th November 2014


Limitations

MODEL LIMITATIONS

General Model Limitations

In the current release the following elements of the device functionality are not modelled:

  • Brown-out Reset is not implemented.
  • Power supply voltage changing is not supported.
  • JTAG interface is not supported.
  • External programming of memories is not supported.
  • Electrical characteristics dependency of the temperature is not implemented.

MEGA 8/16/32 Model Limitations

In the current release of the Mega 8/16/32 model, the following elements of the device functionality are not modelled:

  • The USART is modelled as a UART only. Also the additional UART features such as parity and double rate clocking are not modelled.
  • The OSCCAL register has no effect; the clock speed is set by the CLOCK property only.
  • The XDIV register has no effect; the clock speed is set by the CLOCK property only.
  • The effect of the boot lock bits is not modelled.
  • The JTAG interface is not modelled.

We plan to complete modelling of the USART in a future release.

MEGA 64/128 Limitations

In the current release of the Mega 64/128 model, the following elements of the device functionality are not modelled:

  • The USARTs are modelled as UARTs only. Also the additional USART features such as parity and double rate clocking are not modelled.
  • The OSCCAL and XDIV registers are not modelled; the clock speed is set by the CLOCK property only.
  • The effect of the boot lock bits is not modelled.
  • The effect of the SM0 and SM2 sleep mode bits is not modelled; the modelling of the sleep instruction is approximated to either the “Idling” or “Power Save” modes according to whether SM1 is cleared or set.
  • The JTAG interface is not modelled.

We plan to complete modelling of the USART in a future release.


Loaders

LOADER FORMATS

ELF/DWARF

The ELF/DWARF format is a public domain format used by AVRStudio and the open source GNU compiler chain.

Both the ELF and the DWARF files must be in the same directory as the source files and the ISIS design file and you specify the ELF file as the program property. e.g.

PROGRAM=MYFILE.ELF

Note that the Proteus supports the DWARF2 format - you may need to change compiler options to force this if it is not the default configuration on your toolchain.

COFF

The COFF format for AVR is a public domain symbolic debug format used by a number of tools including AVR Studio.

COFF files for the AVR have the extension '.COF' and contain full symbolic debug information including source line address and variable data. To load a COFF file into the model, you will need to set the program property with the full filename and extension. e.g.

PROGRAM=MYFILE.COF

Note that the COFF file contains absolute paths to the 'C' source files, and problems may arise if the project is moved from one directory to another.

UBROF

The UBROF format is owned by IAR Systems and is a common symbolic debug format used across the entire range of IAR compiler products.

UBROF files for the AVR have the extension '.D90' and contain full symbolic debug information including source line address and variable data. To load a UBROF file into the model, you will need to set the program property with the full filename and extension. e.g.

PROGRAM=MYFILE.D90

Note that the UBROF file contains absolute paths to the 'C' source files, and problems may arise if the project is moved from one directory to another. The solution is to re-compile the project within IAR workbench.

Note that Proteus supports UBROF 8 or earlier, so you will need to set the XLINK options in your project to generate output of type UBROF 8 (forced).

HEX

Failing all else, simply specify the HEX file as the program property for the processor on the schematic. This will simulate but will not single step debug as there is not enough information to provide a source window.


Properties

MODEL PROPERTIES

The following is a list of the properties available for configuration in the Atmel AVR Models:

Program Property

Specifies one or more program files to be loaded into the model's internal code memory. These files can be in Intel Hex format (.HEX), IAR UBROF format (.D90), ELF/DWARF format (.ELF) or COFF format (.COF). The file extension must be given as it is used to determine the file format.

Clock Frequency (default 1MHz)

Specifies the clock frequency of the processor. For reasons of efficiency, the clock circuitry is not simulated, and the clock rate of the processor is determined solely by this value.

Suspend on Stop (default TRUE)

Causes the model to suspend the simulation when a STOP instruction is encountered.

Simulate Power on Reset Delay (Default FALSE)

If TRUE, the model simulates the 4064 cycle reset/power on delay. Otherwise, the model executes the reset/vector sequence as soon as it sees that RESET is logic high.

Force Breakpoints on ADC Samples (Default FALSE)

If TRUE, the model forces a mixed mode simulation breakpoint each time the ADC needs to sample an input voltage. Otherwise, the model interpolates the sample value. This is generally very accurate, unless your program does things which could affect the analogue input voltages seen by the ADC. If the ADC is running in continuous mode, setting this option will dramatically slow down the simulation.

Log Events in Simulation Log Window (Default FALSE)

When TRUE the model will write System Diagnostics to the Simulation Log.

EEPROM Write Delay (Default 4ms)

This property specifies the delay used between writes to the EEPROM.

Initial Contents of EEPROM

This property allows you to load a binary image file of the initial contents of the EEPROM.

Watchdog Clock (Default 1MHz)

Specifies the Watchdog Clock Frequency.

External Reset Disabled (Default TRUE)

This option corresponds to the RSDSBL fuse bit in the ATTINY processors. When disabled the RESET pin can be used as an Input or IO pin (depending on the processor).

Clock Select Options (Default Internal Oscillator)

This option corresponds to the CKSEL fuse bits on the ATTINY processors. Depending on the configuration of this option pins may become available for IO. The optimum configuration for IO is the default option.


VSM Studio

VSM STUDIO IDE

By far the easiest way to get set up for simulating in Proteus is through the integrated VSM Studio IDE. This tool is integrated into the Proteus Design Suite, will detect installed compilers and you can directly download and install additional tools from inside the IDE.

Installed compilers are automatically configured by VSM Studio to produce debugging output suitable for driving Proteus VSM. If however you need to make changes all of the compiler options are made available in the Project Setting dialogue inside VSM Studio.

If you are using the Arduino™ toolchain inside VSM Studio and want to install new libraries please refer to the Arduino guide.

Once you have written some code and compiled your schematic will automatically be programmed with the firmware. You can then both simulate and single step debug inside VSM Studio. Active popups let you add 'schematic snippets' to VSM Studio so that you can view and interact with the simulation while debugging the source code.

Getting Started Tutorial:

VSM Studio Tutorial (New Project)

Detailed Tutorial:

Proteus VSM Tutorial

If you prefer to work inside your IDE for firmware then you need to generate a supported format from your compiler and specify that as the program property on the Edit Component dialogue form of the AVR Micro.