ARM7TDMI Microprocessor Core Model

The ARM7TDMI core model simulates the ARM7TDMI and ARM7TDMI-S microprocessor core from Advanced RISC Machines (ARM Ltd). This model is primarily intended for use as a modelling primitive within models of specific devices such as the LPC2000 series, but could also be relevant in a educational context, or where uses which to simulate an ARM7 core in conjunction with other elements of an SoC design. In this situation, the additional elements could be modelled using the VSM SDK to create additional DLL models.

Direct use of the ARM7TDMI core within user designs is for the very experienced designers only - the flexibility and complexity of the pipelined bus architecture make the interfacing of memory and other peripherals into a very complex task.

See also

§. Getting Started - Compilers and Integration

§. Introduction to LPC2000 Microprocessor Models

§. ARM7TDMI Model Properties

§. Remote Debugger Drivers

This help file last modified 03rd October 2012.


Compilers and Integration

The ARM7 model can load program files in ELF/DWARF debug formats as well as the exact same hex file that you would program a physical device with. The advantage of the debug format is that it contains symbolic debug information (source code, variables,etc.) which enables you to not only simulate your system in Proteus but also to single step debug. The following is a summary of supported formats with basic instructions on how to get started.

See Also:

Proteus VSM Tutorial

VSM Studio IDE

By far the easiest way to get set up for simulating in Proteus is through the integrated VSM Studio IDE. This tool is integrated into the Proteus Design Suite, will detect installed compilers and you can directly download and install additional tools from inside the IDE.

Installed compilers are automatically configured by VSM Studio to produce debugging output suitable for driving Proteus VSM. If however you need to make changes all of the compiler options are made available in the Project Setting dialogue inside VSM Studio.

Once you have written some code and compiled your schematic will automatically be programmed with the firmware. You can then both simulate and single step debug inside VSM Studio. Active popups let you add 'schematic snippets' to VSM Studio so that you can view and interact with the simulation while debugging the source code.

See Also:

VSM Studio Tutorial (New Project)

Schematic Only

If you choose or prefer to work in your own IDE and use Proteus VSM only for simulation then several debug formats are available. The process in each case is to produce the required debug file from your compiler and then to load this file as the PROGRAM property in the Edit Component dialogue form of the PIC microcontroller.

ELF/DWARF Format

The ELF/DWARF symbolic debugging format is becoming a de-factor standard allowing debugging tools written by one vendor to load executable files produced by another vendor’s compiler. In terms Proteus VSM, this means that you can work with any compiler that produces valid ELF/DWARF output.

We have tested Proteus VSM specifically with the following C/C++ compilers:

  • GNU ARM compiler - GCCARM V3.3.1
  • Keil ARM compiler - KARM.
  • IAR ARM compiler - EWARM.

In all cases, source level debug information is extracted from the ELF/DWARF file so you must set the compiler to both produce an ELF file and also to generate DWARF2 debugging information.

ELF files have the extension '.ELF' . To load an ELF file into the model, you will need to set the program property with the full filename and extension. e.g.

PROGRAM=MYFILE.ELF

It is important to realize than an ELF file may or may not contain DWARF debugging information (this is the locations of the program source lines and variables within memory). If you find that Proteus loads the ELF file, but does not display a source or variables window, then check the simulation log. If you see

No ".debug_line" section, cannot associate addresses to source lines.

then this probably means that the compiler has not been set to (or cannot) generate DWARF2 debugging information.

Note that the ELF file contains absolute paths to the 'C' source files, and problems may arise if the project is moved from one directory to another.

In addition, remote debugger drivers are available for the Keil UV3 and IAR EW-ARM IDEs enabling you to control the VSM debugging session much as you would with real hardware.


INTRODUCTION

Device Support

The Proteus VSM ARM/LPC2000 model can simulate the behaviour of the following microcontrollers from Philips™:

LPC2101 - 8K Flash, 2K RAM

LPC2102 - 16K Flash, 4K RAM

LPC2103 - 32K Flash, 8K RAM

LPC2104 - 128K Flash, 16K RAM

LPC2105 - 128K Flash, 32K RAM

LPC2106 - 128K Flash, 64K RAM

LPC2114 - 128K Flash , 16K RAM, 10 BIT ADC

LPC2124 - 256K Flash , 16K RAM, 10 BIT ADC

LPC2131 - 32K Flash, 8K RAM, 10 BIT ADC

LPC2132 - 64K Flash, 16K RAM, 10 BIT ADC

LPC2134 - 128K Flash, 16K RAM, 2x10 BIT ADC

LPC2136 - 256K Flash, 32K RAM, 2x10 BIT ADC

LPC2138 - 512K Flash, 32K RAM, 2x10 BIT ADC

These models make use of the ARM7TDMI core model primitive in conjunction with DLL based models for the on-chip peripherals.

See also

§. Getting Started - Compilers and Integration

§. LPC2100 Model Properties

§. LPC2100 Model Limitations

§. Remote Debugger Drivers

This help file last modified 03rd Oct 2012.


LPC2100 MODEL LIMITATIONS

The current release of the LPC2100 family model has the following limitations:

  • The FIFO mode operation of the UARTs is not modelled.
  • The AND/OR logic for multiple selected external interrupts on the LPC2114/24 is not modelled.
  • The boot-loader is not present or modelled; program execution always starts at 0x0000000 on reset.
  • In circuit programming and in-application programming is not modelled.
  • The JTAG interfaces and on chip debugging system are not modelled.
  • The timing of memory accesses via the MAM is approximated since no precise description of the MAM behaviour is available. When the MAM is enabled, the model assumes a 100% hit rate, otherwise accesses to the FLASH memory take the number of CCLK cycles specified by the MAMTIM register.
  • The timing of instructions which access the VBP peripherals is approximated. The interaction of the CCLK and PCLK is complex and not documented. The model behaviour is in broad accordance with empirical results obtained from actual hardware.
  • Whilst the PLL clock multiplier is fully modelled, there is no way you will achieve real time simulation of applications which clock the processor at the full 60MHz CCLK. Proteus VSM is capable of CPU simulation speeds of up to about 10MIPS on a state of the art (e.g. 3GHz) PC, provided that other aspects of the simulation do not consume substantial CPU resources.


LPC2100 MODEL PROPERTIES

The ARM/LPC2100 model can be configured via a number of properties, described below. Note that not all properties are meaningful for a given model and only those properties that are meaningful for a particular device will be shown on the device’s Edit Component dialogue form.

Property | Default | Description
PROGRAM | - | Specifies one or more program files to be loaded into the model's internal code memory. These files can be in Intel Hex format (.HEX), or ELF format (.ELF). The file extension must be given as it is used to determine the file format.
CLOCK | 10MHz | Specifies the clock frequency of the processor. For reasons of efficiency, the clock circuitry is not simulated, and the clock rate of the processor is determined solely by this value.Note that this value is the input to the processor, not the CCLK value achieved after PLL multiplication.
TRACE_XXX | 0 | Enable diagnostics from the peripherals. XXX can be any of SYSCON, SPI, VIC, UART0, UART1, TIMER0, TIMER1, RTC, SPI, SPI0, SPI1, I2C or WATCHDOG. Setting the property to ‘1’ causes the corresponding peripheral to write diagnostic/debugging information to the simulation log.
ELF_DEBUG | 0 | Enable diagnostics from the ELF loader. Use when directed by Labcenter Technical Support only.


REMOTE DEBUGGER DRIVERS

Remote debugger drivers are available for Keil uVision 3 and IAR Embedded workbench. These drivers make Proteus VSM appear like an In Circuit Emulator (ICE) to the IDE and allow you to control the debugging session room just as you would when debugging real physical hardware.

You can choose to run both the IDE and Proteus VSM on the same computer, or else for maximum benefit, you can run the IDE on one computer - say a laptop - and then run Proteus on another computer - e.g. your desktop. This way of working allows you to see both everything going on in the IDE’s debugger and also everything that is displayed on the Proteus schematic.

To download and install either of the drivers from our web site, please use the following links. Full documentation is included with each driver:

Download and Install remote debugger driver for Keil uVision3

Download and Install remote debugger driver for IAR EWARM

Please note that the debugger driver should be installed on the same machine as the Keil or IAR compiler/IDE.


ARM7TDMI Model Properties

The ARM7TDMI core model can be configured via a number of properties, described below. Note that not all properties are meaningful for a given model and only those properties that are meaningful for a particular device will be shown on the device’s Edit Component dialogue form.

Property | Default | Description
PROGRAM | - | Specifies one or more program files to be loaded into the model's internal code memory. These files can be in Intel Hex format (.HEX), or ELF format (.ELF). The file extension must be given as it is used to determine the file format.
CLOCK | 1MHz | Specifies the clock frequency of the processor. For reasons of efficiency, the clock circuitry is not simulated, and the clock rate of the processor is determined solely by this value.
MODE_UNPREDICTABLE | 1 | Determines if the model should generate simulation log warnings for operations which the documentation specifies as having unpredictable consequences.
MODE_SUPPRESS_BUS | 1 | Determines whether bus cycles accessing memory within the EXTROM and EXTRAM ranges are suppressed or not. Setting MODE_SUPPRESS_BUS=0 will cause full simulation of every bus cycle with consequent dramatic loss of simulation speed.
EXTROM | 0x00000000-0x0000FFFF | Specifies one or more ranges of memory considered to be ROM. Read cycles for this area of the memory map are simulated internally to the model, provided that MODE_SUPPRESS_BUS=1. The default value provides 64KB of ROM at location 0x00000000.
EXTRAM | 0x00010000-0x0001FFFF | Specifies one or more ranges of memory considered to be ROM. Read cycles for this area of the memory map are simulated internally to the model, provided that MODE_SUPPRESS_BUS=1. The default value provides 64KB of RAM at location 0x00010000.
ELF_DEBUG | 0 | Enable diagnostics from the ELF loader. Use when directed by Labcenter Technical Support only.

Property Default Description

PROGRAM - Specifies one or more program files to be loaded into the model's internal code memory. These files can be in Intel Hex format (.HEX), or ELF format (.ELF). The file extension must be given as it is used to determine the file format.

CLOCK 1MHz Specifies the clock frequency of the processor. For reasons of efficiency, the clock circuitry is not simulated, and the clock rate of the processor is determined solely by this value.

MODE_UNPREDICTABLE 1 Determines if the model should generate simulation log warnings for operations which the documentation specifies as having unpredictable consequences.

MODE_SUPPRESS_BUS 1 Determines whether bus cycles accessing memory within the EXTROM and EXTRAM ranges are suppressed or not. Setting MODE_SUPPRESS_BUS=0 will cause full simulation of every bus cycle with consequent dramatic loss of simulation speed.

EXTROM 0x00000000-0x0000FFFF Specifies one or more ranges of memory considered to be ROM. Read cycles for this area of the memory map are simulated internally to the model, provided that MODE_SUPPRESS_BUS=1.The default value provides 64KB of ROM at location 0x00000000.

EXTRAM 0x00010000-0x0001FFFF Specifies one or more ranges of memory considered to be ROM. Read cycles for this area of the memory map are simulated internally to the model, provided that MODE_SUPPRESS_BUS=1.The default value provides 64KB of RAM at location 0x00010000.

ELF_DEBUG 0 Enable diagnostics from the ELF loader. Use when directed by Labcenter Technical Support only.