What Is ARES

INTRODUCTION

The PCB layout module of the Proteus Design Suite and offers netlist based PCB design complete with a suite of high performance design automation tools.

Proteus Version 8.xx is officially compatible with Windows 10 and later.

Layout Editor Features

Major features of the Proteus Professional Layout Module include:

  • 32 bit high-precision database giving a linear resolution of 10nm, an angular resolution of 0.1° and a maximum board size of +/- 10m. Proteus supports 16 copper layers, two silk screens, two assembly, eight mechanical layers plus occupancy, slot, solder resist and paste mask layers.
  • Hardware accelerated display (Direct2d or OpenGL) using the power of your graphics to improve speed and provide true layer transparency.
  • State of the art ergonomic user interface with modeless selection, selection and activity indicators and localised functionality via context menus.
  • Live netlist and shared database binding with the Schematic capture module, including the ability to specify routing information on the schematic.
  • Thousands of library parts included as standard and a universal Library import tool supporting all the major part vendors to provide countless more in on demand.
  • Complete user control of layer stackup and drill passes. Smart vias make use of legal drill ranges.
  • Live Physical Design Rule Checker and Connectivity Rule Checker. Uses comprehensive design rule priority system, including design rule rooms on the board.
  • Powerful route editing features including topological route editing, track necking, length matching, dynamic teardrops and curved trace support.
  • World-class adaptive shape based autorouter capable of achieving completion on even the most complex of boards.
  • Template and Technology Data scheme allows for flexible re-use of board outlines and design constraints.
  • Automatic net tuning and serpentine creation to length match high speed lines. Includes specification of internal lengths in components.
  • Fully automatic Back-Annotation of component renumbering, pin-swap and gate-swap changes.
  • Full support for design re-use through schematic & layout project clips (design snippets).
  • Full metric and SMT support. This includes all dialogue form fields as well as the co-ordinate display and grid settings.
  • Output to a wide range of printers and plotters including the Valor ODB++ format, Gerber X2 and traditional Gerber/Excellon. Also output in DXF, PDF, EPS, WMF and BMP graphics formats - to file or clipboard where appropriate.
  • Built in Gerber Viewer and Panelizer - this enables you to check your Gerber output files before spending money on bureau fees or board manufacture.
  • 3D Board Visualisation with solidworks compatible IDF, STL outputs as well as 3D DXF and 3DS output.

Auto-Placement

Proteus includes an auto-placer and floorplanning feature, an addition which in combination with the auto-router makes it possible to create simple PCBs almost entirely automatically. Alternatively, you can use it interactively, either by pre-placing critical components manually and auto-placing the rest, or else by using it to place small sections of the design in turn with manual adjustments being made after each section is placed.

The auto-placer is highly configurable and can be set up to handle a wide variety of board types.

Auto-Routing

The most tedious, error prone and time consuming part of the traditional electronics development process is undoubtedly routing the PCB. As a result, it is in this area that the greatest benefits of Electronic Design Automation are to be found.

Our auto-router is a state of the art adaptive shape based router and you will find it capable of near 100% completion of designs that could take days by hand. It includes cost-based conflict reduction algorithms that allows the natural flow of the nets to emerge during routing and minimises both trace length and via count.

In addition, a direct interface is also available to the ELECTRA autorouter from Connect EDA and manual file export/import is supported for other routers such as SPECTRA™.

Power Planes

Proteus layout supports Polygonal Gridless Power Planes which overcome most, if not all of the disadvantages associated with other methods of implementing copper fills. The essence of the approach is to generate polygonal boundaries around all the objects within the target area, and then to merge them together. The resultant multi-edged hole boundaries are subtracted from the original (user placed boundary) in order to establish whether or not there is complete or partial connectivity.

3D Board Visualisation

Proteus comes with a 3D Visualisation engine, allowing you to examine the board as it will appear in real life prior to prototyping. This not only assists with layout design but also provides information on height clearance. With simple, mouse driven navigation it is now the matter of a couple of mouse clicks to launch and examine your design in three dimensional space. Mechanical model import and 3D CAD output in STEP/IGES format is also supported.

System Requirements

Performance in Proteus is scaleable according to your computer specification. The following are the recommended minimums requirements :

  • 2GHz or faster Intel Pentium processor (AMD processors fine but less optimised).
  • Graphics card supporting Direct 2D or OpenGL Version 2.0 and multi-sampling (MSAA).
  • 8Gb RAM (recommended 16Gb).
  • Windows 10 or later.

In particular, note that if your graphics card does not satisfy the above requirements the software will run in Windows GDI mode. This means that display of the screen is handled by Windows and not your graphics hardware and therefore that some features of the software will not be available.

As a general rule, manufacturer graphics cards such as ATI and NVIDEA will satisfy these requirements whilst chipset graphics such as those supplied by Intel will not.

You may find that your display works better with either OpenGL or Direct2D or even that your graphics card supports only one of the two modes. This is largely dependant on your particular graphics card and driver - you can experiment with changing modes at any time via the Set Display Options command on the System Menu.

All Windows computers will support Direct2D as this is used for the Windows Aero Desktop.

How to use this Documentation

Whereas the getting started guides (printed documentation) contains practical summaries and tutorials, the online help serves as a reference manual for the software.

The Graphical User Interface and the general intelligence of the software itself will enable many users to be productive almost from the outset. However, as with the schematic module there is a great deal of functionality 'under the hood' and you cannot expect to master all aspects of the package immediately.

For those who need some initial tuition and guidance, we have followed the adage that the best way to learn is by doing - once you have installed the package by following the instructions in the next chapter, we suggest that you proceed to work through the extensive tutorial. This takes you right the way through the PCB design process from loading a netlist to performing the final CRC and DRC checks. You can launch this file separately from the home page (Getting Started section).

The remainder of the chapters provided background detail on all aspects of the system, and for quick reference, the final chapter deals with all the commands and any associated dialogue forms.

See Also:

Getting Started Tutorial


SCREEN LAYOUT

The Menu Bar

Menu items

The Menu Bar runs across the top row of the screen and its main purpose (the selection of commands from the menus) is the same as with any other Windows application. In addition, the title bar area above the menu names is used to display certain prompt messages which indicate when the program has entered a particular editing or processing mode.

The Toolbars

As with other modern Windows applications, ARES provides access to a number of its commands and modes through the use of toolbars. The toolbars can be dragged to any of the four edges of the ARES application window.

Command Toolbars

The tools located along the top of the screen (by default) provide alternative access to the menu commands, as follows:

Command Icons

Mode Selector Toolbar

The toolbar located down the left hand edge of the screen select the editor mode, i.e. what happens when you click the mouse on the Editing Window.

Mode Icons

Orientation Toolbar

The orientation toolbar displays and controls the rotation and reflection for objects prior to placement on the layout.

Orientation icons

Toolbars visibility can be controlled from the Toolbars command on the View Menu.

The Editing Window

The Editing Window displays the part of the board that you are currently working on.

The contents of the Editing Window may be redrawn using the Redraw command which also redraws the Overview Window.

Panning

You can reposition the work area over different parts of the layout in several ways:

  • By clicking left at a point on the Overview Window - this re-centres the work area about the marked point.
  • By clicking the middle mouse button to ‘pick up’ the sheet, moving the mouse to re-position the sheet and then clicking the middle mouse button again to ‘drop’ the sheet.
  • By moving the mouse over the Editing Window, holding down the SHIFT key, and 'bumping' the pointer against one of its edges. This pans the display in the appropriate direction.
  • By using the Pan icon on the toolbar.

Zoom In / Zoom Out

You can magnify or reduce the display of the board using the Zoom In and and Zoom Out commands which can also be invoked via keyboard shortcuts (by default, the F6 and F7 keys). Additionally, you can use the shortcut key for Zoom All (F8 by default) to display a view of the entire board. You can also use the corresponding icons on the toolbar or simply roll the middle mouse button in or out to zoom in/out respectively. In particular with the latter, you can roll the mouse button while panning by clicking the middle mouse button to pick up the sheet, rolling the mouse to zoom out/in whilst moving the mouse to re-position the sheet. While this sounds complicated it is in fact extremely intuitive in practice.

Variable Zoom

An arbitrary degree of magnification can be achieved using the Shift-Zoom feature. A given area of the board can be selected to fill the Editing Window by holding down the SHIFT key, pressing the left mouse button and dragging out a box around the desired area. The area can be marked on either the Editing Window or the Overview Window.

The Overview Window

The Overview Window

This window shows a simplified representation of the whole drawing, and has a 500 thou grid on it. The blue box marks the outline of the work area as set by the Board Properties command (Technology Menu) whilst the green box indicates the region on view in the Editing Window.

Clicking left at a point on the grid re centres the Editing Window around this point.

The Overview Window is also used to display previews of objects that are selected for placement. This features helps you to orient (rotate and mirror) an object correctly before placing it on the board.

The width and height of the Overview Window can be adjusted by dragging its borders. If you drag the vertical border right over to the other side of the application Window, ARES will re-organize the display so that the Overview Window and Object Selector are located at the right hand side.

The Overview Window pane can also be dynamically hidden by right clicking on it and selecting the ‘Auto-Hide’ command from the resulting context menu. This is particularly useful where the parts are on the layout and you want to maximise the Editing Window space for layout of the board.

The Object Selector

The Object Selector

The Object Selector is used for picking components, packages, pad & trace styles and so on from those that are currently available. It always carries a label indicating what it is listing and this serves as a prompt additional to the state of the Icon Panel as to which mode is current.

The width and position of the Object Selector can be adjusted in conjunction with the width and height of the Overview Window, as described above. You can also hide this pane to maximise the Editing Window space by right clicking on the Object Selector and selecting the Auto-Hide command from the resulting context menu.

The Context Menu for the Object Selector provides a number of mode specific options, giving you quick and easy access to functionality during PCB design.

Component Mode

A common frustration with starting a layout following schematic design is the large quantity of parts to be placed that are identified only by part reference. Proteus 8 includes two additional features to the ARES parts bin to help make this simpler:

  • Part values are displayed alongside the part references.
  • Displayed contents can be limited to a selection on the schematic.

To limit the ARES parts bin contents

In ISIS, switch to selection mode, left depress the mouse and drag a selection box around the area of interest. Then, in ARES, switch to component mode and change the combo box at the top of the parts bin to 'tagged'

The Layer Selector

The Layer Selector

The Layer Selector is used to display and select the current layer or layer set. A layer is a single layer, whereas a layer set is a combination of single layers, such as 'ALL'.

The layer selector can be operated with either the mouse or the keyboard. The default keyboard controls are as follows:

Shortcut | Description
SPACE | Selects the next layer in the current layer pair sequence.
PGDN | Selects the next layer down the list.
PGUP | Selects the previous layer up the list
CTRL-PGDN | Selects the last layer in the list.
CTRL-PGUP | Selects the first layer in the list.

All the keyboard mappings above are configurable via the Set Keyboard Mapping command on the System Menu.

Selectable Layers

Which layers are displayed in the list is determined by the current editor mode, such that PCB objects cannot be placed on inappropriate layers. It will also be limited by the Layer Stackup settings on the Technology Menu.

Displayed Layers

Which layers are displayed is controlled with the Layers command on the View menu.

Colour sets allow you to configure various different layer visibility options into named groups, including paper colours and solder resist/paste mask visibility. You can then assign a colourset to a keyboard shortcut for easy access. Typical examples might be:

  • ALL : All of the layers turned on.
  • TOP: Top copper, top silk, top resist, top paste, ratsnest, board edge.
  • BOT: Bottom copper, Bottom silk, Bottom resist, Bottom paste, ratsnest, board edge.
  • INNERX: selection of inner layers in use with the current project.

Colour sets are also useful for printing, with both a MONOCHROME and a white paper option.

Note that a view of drill hole only is potentially ambiguous because whether blind/buried vias contribute depends on the context (which layer ranges are we interested in). For simplicity therefore we include display of only thru-hole pads/vias when only drill holes is selected for viewing.

Layer Associations

Layer pair sequences can be redefined using the Layer Pairs command on the Technology menu.

Technology > Layer Pairs and the Edit Layer Pairs Dialogue Form

This command defines the layer that the SPACE key will select for each layer (for example when dropping a via during route placement).

See Also:

Layer Pairs and Manual Routing (Tutorial)

Co-ordinate Display

The current co-ordinates of the mouse pointer are displayed down at the bottom right of the screen by default. The read out can be in imperial or metric units and a false origin may be set. False origin commands (keyboard toggle 'O') and metric or imperial (keyboard toggle 'M') can be configured via the Set Keyboard Mapping command on the System Menu or activated directly from the View Menu.

The X-Cursor command will display a small or large cross at the exact location of the current co-ordinates (that is, the precise snap location for placement). Again, this can be toggled via the View Menu or by using the mapped key on the keyboard (default 'x').


CO-ORDINATE SYSTEMS

Overview

The fundamental unit of linear measurement in ARES is 10nm (ten nanometers). Given 32 bit representation of the co-ordinates this allows a board size up to +/- 10m (ten meters) with some headroom for calculations. The 10nm unit divides exactly into both 1um (micron) and 0.1 thou (one ten thousandth of an inch) giving exact representations of both imperial and metric dimensions to these resolutions.

Rotational angles are stored to 0.1degree.

The co-ordinate display can be switched to reading metric units by invoking the Metric command or via the keyboard shortcut (by default this is the ‘M’ key). Restoring imperial mode is achieved by invoking the Metric command again.

You can set up default units for a template via the Set Grids command on the Technology Menu. When you instantiate a project from a template these settings are then applied. Note that this affects only the units which are set when you open the project (the start up units).

Dimension Entry Fields

A number of the dialogue forms contain fields that deal with dimensions such as pad style sizes, track widths, design rule clearances and so forth. All these fields are handled in a such a way that both imperial and imperial units can be used at will. The operation of these fields is in accordance with the following rules:

  • Values are displayed in units chosen by a heuristic algorithm which detects whether a dimension is a whole number of imperial or metric units. Thus 25.4mm (however originally entered) will always display as 1in, when the field first appears.
  • Displayed values always carry a unit. If you delete the existing value, the original displayed unit will be used.
  • If you prefer, you can enter a new value with an explicit unit. Valid units are:
    Units Description

    th

             Thou (10e-3 inch)

    in

    um

             micron (10e-6 meter)

    mm

             millimeter (10e-3 meter)

    cm

             centimeter (10e-2 meter)

    m
  • Whatever units are chosen, values must be less than +/- 10m, and are held at a resolution of 10nm.

Output Origin

For CADCAM output in particular, but also when working on a board which has to fit into a pre-designed mechanical casing, it is useful to be able to define a reference point on the board which relates to the mechanical design's co-ordinate system. The output origin defines this point within ARES, and is drawn in blue on the Editing Window as a target symbol.

  • You can re-position the output origin using the Output Origin command.
  • The output origin does not affect the co-ordinates used in Region files.

False Origin

Although the Origin command appears on the View menu, it should only be used via its keyboard short cut (default key is 'O'). Its function is to zero the co-ordinate display at the current mouse position, a feature that is most useful when laying out a complex pattern of pads given a set of dimensions on a drawing of the component.

When a false origin is set, the co-ordinate display changes colour from green to magenta as a reminder.

False Origin set to 'ON'

Cancelling a false origin is done by invoking the Origin command a second time.

Grid Display

The Editing Window includes a grid display by default. This can be toggled between ‘off’, ‘dot display’ and ‘line display’ via the ‘G’ button on your keyboard. The spacing of the dots normally equals the current snap setting (see below), but if you are zoomed out a good way, it will be multiplied by a factor of 2,4,8 etc. The threshold at which this occurs can be adjusted on the Grids command on the Technology menu.

The grid dots on the Overview Window are 0.5in apart.

Snapping Grids

Although the motion of the mouse arrow itself is smooth, you will see that the co-ordinates normally jump in fixed multiples of, for example, 50 thou. The size of these multiples is set by the Snap commands and the purpose of this is to facilitate the placement of objects on a fixed grid.

Under normal circumstances, boards tend to be routed on a 50 or 25 thou grid.

Three snap grids for each of imperial and metric modes are available at any one time, though you can redefine their values using the Grids command on the Technology menu. The current snap options are selectable from the View menu or by using shortcut keys (the preconfigured keys for the snap commands are CTRL+F1 & F2-F4).

The snapping points are computed starting from the current origin as set by the Set Origin command. This provides the means to measure out pad placement for a new component, since you can set the origin at the first pin, set one of the snap values to the pin spacing, and then advance the cursor along the pad positions using the cursor keys.

Real Time Snap

As well as snapping to the grid dots, ARES will also snap the cursor to pads and/or tracks which lie off the currently selected snap grid. This process takes place in real time - as the pointer is moved - hence the name Real Time Snap.

The rules for what is snapped to are as follows:

  • Pads are always snapped to. Only pads whose layer range overlaps the current layer range are scanned.
  • Tracks are snapped to when the either the Trace icon or Via icon is selected. Only tracks on the current layer are scanned.
  • Ratsnest lines are snapped to when the Ratsnest icon is selected.
  • The range within which the pointer will 'see' an object is either half the current snap spacing or, if grid snap is disabled, the actual bounds of the object concerned.

RTS is extremely useful when routing between components whose pins are on different grids, since it alleviates the need to constantly switch between routing grids. In this context, the Trace Angle Lock feature is also very important.


Pad Trace and Graphics Styles

PAD,TRACE & GRAPHICS STYLES

Overview

Proteus PCB Layout features a sophisticated and flexible system for defining shapes and sizes for pads, tracks and 2D Graphics.

Each pad and track is given a unique style name, and this name is then used to refer to the style whenever it is used. The dimensions and other characteristics for each style are held in layout-global table, and this makes it possible to change the dimensions of all the pads or tracks in a particular style extremely easily. At the same time, the use of names means that there is no serious limit on the number of pad and trace types that you can have per layout.

Individual 2D Graphics can be customised to specific dimensions, both in terms of line width and, where appropriate, fill style. This allows, for example, thicker line styles for 2D Graphics text than for mechanical outlines for PCB footprints.

Pad Styles

Proteus supports 7 types of pad, namely:

  • Circular PTH
  • Square PTH
  • DIL PTH
  • Circular SMT
  • Rectangular SMT
  • Polygonal SMT
  • Edge Connector

and the list of styles defined for each type displays in the Object Selector whenever the appropriate pad icon is highlighted.

When one of these lists is displayed, you can edit an existing pad style by highlighting it in the selector and then clicking on the selector toggle (the 'E' symbol). All fields on the resulting dialogue form have context sensitive help associated with them.

Editing a SMT pad style and Editing a Circular PTH pad style

The Edit Pad Style dialogue is the place to set control of paste mask and solder mask opening (guard gap) for your pads. These pad styles can then be saved into the global style library and will apply to future projects.

Plated or Unplated Status

Through hole pads are all plated by default. You can mark a loose pad as unplated by:

  1. Place the loose pad onto the layout.
  2. Right Click -> Edit Properties
  3. Switch to unplated in the resulting dialogue form..

Specifying a particular pad on the layout as unplated.

Slots

Proteus supports slots as both part of a pad and as a user drawn cutout on the board.

Slotted Pads

Slotted pads are created as a type of padstack with the definition of a slot width, height and slot tool.

Defining a Slotted Padstack

Slots are rendered in gerber by 4 strokes (DRAW) of the tool. A thin tool option is generally better as it will leave less rounded corners. Regardless, your choice of slot tool is important - use the preview on the right hand side for a guide.

Plated or unplated

By default, slotted padstack holes are plated. You can edit them and make them unplated after placement from the right click context menu.

Defining a slot to be unplated.

Output

For Gerber X2 output, slotted padstacks will be output in the appropriate plated or unplated drill file, marked as slots.

Example Slot output

As mentioned above this slot is created by four DRAW operations (D01), with the initial operation being a move to (D02).

Perhaps surprisingly, padstack slots do not output in the profile file, which is reserved for board cutout slots. Holes in the board itself - including the board edge - are defined in the Profile layer whereas holes in pads - of any type - are in the appropriate drill file.

Board Cutout Slots

These consist of graphics objects (normally lines or rectangles) drawn on the slot layer. Think of three lines around a temperature sensor acting as thermal cutoff or an actual square cutout in the board. To place, simply select the appropriate 2D graphic tool, change the layer to slot and draw as needed.

Clearances from these objects to other copper features is defined in design rule manager under edge/slot clearance. Output of board cutout slots takes place in the profile file, includes the board edge itself and is deemed unplated.

Polygonal Pads

ARES supports a user defined, polygonal pad style in order to cater for parts requiring unusual pad shapes.

To define a new polygonal pad style

  1. Using the 2D graphics Line, Arc or Path icons, draw a closed path to define the shape of the new pad style. It does not matter which layer you draw on for this purpose.
  2. Place an Origin marker within the closed path to specify the origin of the pad style. The origin is used as the connection point for tracking, and also serves as the point of alignment if the pad style is used within a pad stack.

    Note that the origin must lie within the closed boundary i.e. within the copper area of the pad.
  3. Tag the 2D graphics and origin marker by drawing a tag-box with the right mouse button.

  4. Invoke the New Pad Style command from the Library menu.

  5. Enter a name for the new pad style.

  6. Set the Polygonal pad style type under SMT.

  7. Click OK.
  8. Configure the paste mask and guard gap (solder mask opening) as required.

  9. If you wish to create the style only in the current layout, and not in DEFAULT.STY, then select Local Edit instead of Update Defaults.
  10. Click OK to create the new pad style.

It is worth noting that zones will connect thermally to the origin of the pad and not the centre of the pad.

Pad Stacks

The ordinary through hole pad styles can be placed on a single layer or on all the copper layers, but this does not provide a very convenient or satisfactory method for defining component pins which have different pad shapes on different layers. In particular, the connectivity system does not recognize connectivity between single layer pads on different layers.

Instead, Proteus provides the facility to define Pad-Stacks. There are several points about a pad stack:

  • A pad stack can have a circular hole, a rectangular slot or be surface only. The latter type of pad stack is used where you wish to defined explicit styles for the solder resist and/or paste mask apertures.
  • For each layer, you can assign a different pad style, or no pad. If you choose a pad style then the value for the layer chosen will be taken from that pad style. For example, choosing a C50-30 on top resist will take the resist setting from the C50-30 style (5th) and apply it to top resist in the pad stack.
  • For obvious reasons the hole or slot diameter of a pad stack is the same for all layers. this is specified at the left hand side of the dialogue form.
  • You must use a pad stack to create a pad shape with a slotted hole. You cannot specify a slotted hole in an ordinary pad style.
  • The layer flipping checkbox at the bottom enables the top and bottom layers, along with their solder and paste to be flipped when the component is placed solder side. Under no circumstances are inner layers flipped.

To define a new pad stack

  1. Select the Create New Pad Stack command from the Edit menu.

  2. Enter a name for the pad stack, and a default pad style. All layers will start out with this style of pad.
  3. Click Continue to proceed to the Edit Pad Stack dialogue.
  4. On this form, you can adjust the pad-layer assignments, and also assign the layer-global drill mark and drill hole/slot size.

The live preview to the right allows you to see either an X or a Y cross section of the resulting padstack. Clicking on a layer in the top graphic will render the pad shape on that layer in the bottom graphic. Turning layers off (View Menu -> Layers Command) will remove them from the graphics in the padstack dialogue form.

To edit an existing pad stack

  1. Select the Pad Stack icon.
  2. Select the pad stack you want to edit from the Object Selector.
  3. Click the 'E' for edit toggle on the Object Selector to bring up the Edit Pad Stack dialogue form..

Mounting Holes

A mounting hole can be placed as just a loose pad on the PCB. You can then edit the pad and set to drill hole only, thereby removing any annular ring around the hole.

Editing a circular pad and removing the annular ring.

Mounting Holes and Design Rules

When you change the pad to be a mounting hole the design rule that applies becomes the edge/hole rule (since there is no longer any annular ring the pad rule does not apply). While unusual you can if needed also set a specific value for zone clearance. If you do this the largest of the following 3 numbers will apply:

  • The relevant edge clearance rule.
  • Any object clearance specified on the Edit Zone dialogue.
  • The value entered for this particular pad

Pad Specific Clearance to a power plane.

Unless exceptions are needed it's best to manage the clearance entirely with design rules. Remember that regional clearances are catered for using design rule rooms.

Pad Styles and the Solder Resist Layer

The solder resist artworks are generated automatically from the pad shapes present on the top and bottom of the board. Each pads' radius is enlarged by the amount specified in the Guard Gap field of its style, as shown below:

Note that in the case of a pad stack, you can define the pad style used for the top and bottom resist layers explicitly, using the selectors in the Edit Pad Stack dialogue form. Note that the guard gap of this style is still applied in determining the final size of the aperture.

You can also specify a pad style which has no solder resist by changing the setting to 'Not Present'. In this case the pad will be covered by the resist coating. If need be, a custom graphic can then be placed on the appropriate resist layer to define the resist escape. This is shown in the movies linked below and covered in more detail in the ARES tutorial.

If you are working in hardware accelerated mode (OpenGL or Direct2D) you can turn on live display of the resist mask layer to inspect coverage using the Displayed Layers dialogue form. Bear in mind that resist and paste are inverse plots so ‘no-coverage’ on the layout equates to flood over physically, 5th expansion on the layout equates to 5th gap on the physical board, etc.

It is important to be consistent with design rules and guard gap (solder mask expansion). Since the Pad-Trace design rule dictates how close a trace can come to the pad and the Guard Gap dictates the solder clearance around a pad, you can end up with slivers of exposed copper if the two settings are inconsistent. In most cases, this will be picked up by the Resist-Trace clearance rule.

See Also:

ARES Tutorial : Hardware Accelerated Display

Creating Advanced Footprints: QFN with Thermal Pad.

Creating Advanced Footprints: Button Pads and Touch Pads

Pad styles can be edited once created by selecting the relevant pad style icon and then the 'E' button above the object selector/parts bin. You can then change the resist for that pad style (guard gap field) and limit the change to the specific layout you are working on by selecting the 'Local Changes' option at the bottom of the dialogue form. This is commonly done when you wish full resist coverage over via's on the layout.

Pad Styles and the Paste Mask

The paste mask artworks are also generated automatically from the SMT pads present on the board. By default, the paste mask aperture is exactly the same as that used for the pad itself although you can specify a shrink percentage in the edit pad style dialogue form if you want it to be smaller. Once again, in the case of pad stacks, different pad styles may be specified explicitly for this purpose.

You can specify a pad style which has no paste mask via the pad style dialogue form. This is useful - for example - when creating button pads or touch pads.

Summary:

  • Default for SMT pad styles is paste mask same size as pad.
  • You can make it uniformly smaller via the edit pad style dialogue.
  • You can turn it off via completely via the edit pad style dialogue. This allows you to create custom paste definition with solid 2D graphics blocks (e.g. stipled paste mask on large QFN center pad).

The movie links below will help you when you really have no choice but to create your own footprints. We'd advise however that you try the integrated web search first as it may save you a great deal of time.

Creating Advanced Footprints: QFN with Thermal Pad (Stipled Paste Mask).

Creating Advanced Footprints: Button Pads and Touch Pads

If you are working in hardware accelerated mode (OpenGL or Direct2D) you can turn on live display of the paste mask layers to inspect coverage using the Displayed Layers dialogue form.

Fiducials

Fiducials are represented in Proteus as pad styles with the name prefix FIDUCIAL. You can have multiple fiducial styles for global and local fiducials (e.g. FIDUCIAL_GLOBAL, FIDUCIAL_LOCAL) or just different styles for different diameter fiducials (e.g. FIDUCIAL20, FIDUCIAL30, etc.).

The important points about creating these styles and using them are that Proteus will automatically apply solder mask clearances according to the IPC-7351 standard and that the output systems can identify the pads as fiducials. Gerber X2 for example is capable of tagging fiducial pads as fiducials and the Proteus manufacturing report can output the co-ordinate positions of all fiducials which can be helpful for insertion machines.

See Also:

Manufacturing Report : Fiducials.

Pads, Power Plane Clearances and Relief Styles

Regardless of the pad style, you can configure both clearance from zones or relief type/style to the zone.

Clearance from a Pad to a Power Plane

There are several contributing factors:

  1. The zone dialogue contains fields for relief and clearance. These are defaults for all pads encompassed by the zone.
  2. The Design Rule Manager allows you to set design rules for a net with respect other nets. If such a rule exists for a net with a clearance higher than that in the zone then this value will be applied to all pads on the zone which are connected to the net.
  3. For a loose pad (e.g. Mounting hole) you can edit the pad and specify a specific minimum zone clearance.

The rule is that the largest value is applied for any pad.

Relief Styles from a Pad to a Power Plane

As with clearance the Edit Power Plane dialogue contains a relief field which allows you to specify the type of connection to make for pads on the same net as the Power plane. This will be the default, although you can right click on any pad and select the Edit Pin dialogue to change the behaviour for a particular pad (E.g. Thermal '+' to Thermal 'x').

See Also:

Example: Specifying the Default Clearance for the Power Plane

Example: Setting the Minimum Clearance for a Pad

Example: Changing the Topology of Relief Stems on a Pad

Example: Specifying the Thickness of Thermal Relief used in Power Plane Connections

Trace Styles

Currently there is just one type of trace, though in the future we may implement additional types for micro-strip etc. The available trace styles are displayed when the Trace icon is selected. You can then edit any the styles by highlighting its name and clicking on the selector toggle.

Trace styles have a single attribute which defines their width.

New trace styles can be created using the New Trace Styles command on the Library menu.

You can only create new styles when the schematic and layout are in synch. If the command is disabled you need to either disable live netlisting or synch with the schematic.

When you start placing a route the trace style chosen is the one specified in the net class tab of the design rule manager. Similarly, when you neck down to a thinner track style (SHIFT button during routing) to connect to a thin pad the necking style in design rule manager is chosen automatically. It's quite important to set this up first to ensure consistent and ease of use when manually placing routes on the board.

Setting Trace and Neck Styles for routes in a net class.

It follows that you can - and should - define net classes for signals on the board needing special attention. Notably, those which cannot be routed using the standard SIGNAL net class or the single supplied POWER net class.

Net class configuration also allows you to set different conductor widths on the inner layers than the outer layers of the board.

Via Styles

Via styles are much the same as pad styles except that only circular or square vias are permitted. The list of via styles is displayed when the Via icon is selected.

New via styles can be created using the New Via Styles command on the Library menu and edited in the usual way via the Edit Via dialogue form.

The drill range of a via is decided based on the drill spans specified in the layer stackup for the project. When routing the shortest drill span between source and destination layer will be chosen.

Once a via has been placed you can perform move / delete / change layer range actions from the right click context menu.

Via editing options on the context menu.

You can also choose to remove annular ring from layers on which there is no connection. See Non-Functional Pads for more information.

Stitching Zones with Via's

Via stitching is a technique used to tie together larger copper areas on different layers, helping keep return paths short and to reduce noise on the PCB. To stitch planes in Proteus right click on the border of the zone and select via stitch from the context menu. You then set the zone to stitch to and the spacing and offsets for the vias.

Once placed you can move and edit vias in the normal way. You can remove groups of vias with a selection box and the selection filter or you can remove all stitching vias with the remove stitching command on the zone context menu.

Stitching zones is something to be done towards the end of development because it will render the board almost un-routable.

If you receive an error message in the status bar then you have selected the wrong zone to remove the vias from. When the stitching vias or shield vias are placed, they are assigned to the zone stated in the left hand side of the form:

If you select the a zone that does not 'own' any stitching vias and select Remove Stitching Vias, you will receive the following error in the status bar:

See Also:

Example: Stitching two zones together

Shielding Zones with Vias

A via shield or picket fence is a row of via's around the perimeter of power planes or bracketing one or more routes. This can help prevent electromagnetic interference with other equipment or help isolate signals on the PCB operating at different frequencies.

To place a via shield around the perimeter of a zone start by right clicking on the zone border and then select via shield from the resulting context menu.

Specify the destination zone for the stitch (if more than one is available) and then set the spacing requirements for the vias.

Shielding Routes with Vias

To place a via shield around one or more routes first make sure you have power planes in the right place around the route(s) for the shielding vias to be placed.

Select the route or routes (holding CTRL key down for multiple selection if need be) and then invoke the via shield command from the context menu. Do not select the zone.

You need to specify which two zones are being stitched together and then the spacing between vias and the spacing between the vias and the edge of the route.

How it works:

A via shield for routes takes the edge to edge width of all the selected routes (so that you can shield multiple routes), expands it by the via-trace distance specified in the dialogue form and then places vias between the two specified power planes along the path of the routes. It follows that if the specified power plane doesn't exist at this distance from the track ends then nothing will happen.

If you set the via-trace distance to 50th and there isn't a zone there nothing will happen.

You need to make sure that there are power planes in the right place for the shielding vias to go on.

A via shield is normally done early in the design process to ensure it can be placed.

Via Tenting and Filling

Via tenting is a simple cover by solder mask and so is achieved by removing the guard gap from the solder resist for that via style.

Proteus also supports resin filling of vias (sometimes called NCVF or non-conductive via filling). Here the via is filled with special plugging exoxy and then capped on top. It is suitable (and commonly used) for via-in-pad where you don't want the solder to wick down the via hole but it does involve extra steps and therefore extra cost to board manufacture.

Specifically, resin filled vias in Proteus will specify the via protection type as type VII in the Gerber X2 output according to the IPC-4761 standard.

To specify a set of vias as being resin filled:

  1. Enter selection mode and drag a box around the area concerned (E.g. the BGA with vias in pad)
  2. Right click inside the box and select via filling from the resulting context menu
  3. Set the vias to be resin filled.

To change the via filling status of a single via

  1. Right click on the via and select edit via from the resulting context menu
  2. Select/De-select the filled checkbox.

Output Systems

When output as Gerber X2 (recommended) the ViaDrill attribute is set to be type 7 (VII) as specified in the IPC-4761 standard

For extra clarity the filled vias will be exported in a separate drill file, although you can choose to export in the same drill file as other through hole plated vias if you choose - just uncheck the Via Filling box. Note that VII will still appear as a separate AperFunction:

Filled vias are identified in the readme.txt file with a separate toolcode in standard RS274X Gerber. However the technology is newer than the output format so we do not recommend you use RS274X when filled vias are present on the board. Filled vias are not supported in the current version of ODB++ output.

Only through hole vias can be filled. Neither blind nor buried vias can be filled.

Make sure your layer stack thicknesses are correct. These can be used by the board manufacturer to inform how much epoxy is needed to fill a hole.

Filled vias are also identified in the drill table data object which is placed on the manufacturing report in Project Notes.

Non-Functional Pads

A non-functional pad is just a pad in a printed circuit board that is not connected to a track on the layer it is on. There are three main reasons why you may want to remove these annular rings:

1) Space. Makes is easier to subsequently route tracks in tight areas.

2) Unwanted/unnecessary capacitance that is significant enough to matter in some designs.

3) Easier drilling (the subject of some debate).

Despite the name we almost always mean vias rather than component pin holes/pads when we talk about NFP's and the tools provided in the software therefore apply to vias only. For component pads you can remove the annular ring on specific layers by creating and using a padstack style.

Terminology

Where a via has the annular ring removed on unused layers we refer it to as a depleted via or sparse via. The non functional pads are the annular rings that are removed.

Removing and Restoring Non Functional Pads

Removing non functional pads from vias is done via a menu command on the Edit Menu.

Remove / Restore NFP.

The applied range on the layout is by default the entire board but you can gate it to work on a selection. This allows you to select part of the board (e.g. around a BGA) and then apply the NFP removal/restoration only to that area.

The two extremities of the via will always keep their annular rings. So a through hole via will always have an annular ring on both top copper and bottom copper, regardless of whether they are connected by a track. Similarly, a blind or buried via will have annular rings on the extremities of their specified drill range. Aside from the drill range extremities all layers on which there is no connecting track will have their annular ring removed / restored.

Depleted vias are automatically restored on the relevant layer should you route to them manually.

Viewing Depleted Vias

In order that depleted vias can be seen on layers where the annular ring has been removed a sliver ring is drawn around the hole. This makes them easy to navigate around when routing with restricted layer visibility.

Viewing Inner1 only. The depleted via on the right shows a sliver ring to make it visible.

The sliver ring visibility is only relevant if you have all of the layers turned off on which an annular ring for the depleted via still exists. It's there to provide a visual indicator of the hole location. If you have a layer enabled on which the depleted via has an annular ring it will render exactly the same as a normal via. So in the picture above for example the depleted via would show exactly the same as the normal via if we enabled the top copper layer or the bottom copper layer.

Routing to a Depleted Via.

The autorouter will not connect to a depleted via on any layer which has no annular ring. Often this will lead to it being unable to complete and you will end up with missing connections / ratsnest lines.

When routing manually you can connect to a depleted via on a layer which has no annular ring. The annular ring on the tracked layer only will automatically be restored for you when you complete the route.

Non Functional Pads and Design Rules

A non functional pad remains a pad for the purposes of design rules. Where a via has been depleted so that only the drill hole remains the border of the hole is the start of the measurement point for the design rule

Style Management

When you start a new layout, an initial set of styles appears and these come from a system file called DEFAULT.STY which is kept in the "Library" directory of your Proteus installation. This file contains a selection of common pad styles that we feel you may find useful.

When you create or edit pad style you will see that the dialogue form contains a Changes groupbox. If you select Local Edit then only the copy of the style maintained within the layout will be modified. If you select Update Defaults then DEFAULT.STY will also be updated.

Package library parts contain there own copies of styles used by their pads. When the package is brought into a layout for the first time, the style definitions will be taken from the library part if they do not already exist within the layout.

2D Graphics Styles

Global Defaults

Default values for 2D Graphics are set via the Technology Menu > Set Text Style command as shown in the dialogue below.

Setting the styles for the default 2D graphic & Text styles

Changes to these settings are local to the current layout unless you save the current layout as a Template. In this case the technology information will be stored in the Template file and can be re-used by either initialising a new layout from the template or by applying the technology data to a layout via the command on the Technology Menu.

Individual Configuration

You can edit specific graphics in the normal way (right click to highlight, left click to edit). An example of each tab in the dialogue form, from editing a 2D Graphics Box is shown below.

Editing the 2D graphics box style

In order to change the width of the outline pen simply uncheck the Follow Global checkbox and enter the desired value in the edit field.

The fill style can also be edited for any 2D Graphics object which encompasses an area of free space. For example, you may well want to have a solid fill for a 2D graphics box but it has no meaning to have a fill style for a 2D graphics line.

Finally, you can tag multiple objects and then apply any changes to all tagged objects using the All Tagged Objects button. If you have multiple objects of different types tagged (for example, some graphics lines and graphic boxes) and exit with this button then ARES will update applicable changes to each object.


Layer Stack

LAYER STACK & DRILL PASSES

Introduction

The layer stack-up provides a way for the designer to define the number of layers and the method of fabrication. This information is then used in various places by the software during board layout. For example:

  • The layer stackup defines the valid drill passes which in turn enables us to ensure that vias with valid drill ranges are placed during layout.
  • The stack-up dialog also enables users to specify thicknesses for cores and prepreg which enables us to calculate the length of a via and use that information when length matching.

Users concerned with the EMC performance of their product or working with high speed design signals will typically want to define their PCB layer stack accurately and pass this information through to the fab house to ensure that board production matches the design intent. The layer stack info will export in the readme file of all CADCAM output formats and the drill pass info will also be included in the standard drill plot.

About Layer Stacks

Before looking at how layer stacks are managed in Proteus, it is worth a short recap of terminology and common fabrication options for PCB's.

  • Pre-preg is essentially woven fibreglass coated in unset epoxy resin.
  • A core is basically ready made copper-foil/pre-preg/copper-foil or copper-foil/pre-preg.

A board house will generally have double sided copper clad core in stock as a base to start from.

1) They will drill, through-hole-plate and etch, one or more of these cores.

2) They will then overlay the board with pre-preg, then either bond that to another core (this core could be a basic core or already have had additional layers of pre-preg and copper foil) or a foil, then they can go back to step 1. Multiple layers of pre-preg can be used together to make up thicker insulating layers.

This process creates a basic set of rules as to what is manufacturable using conventional processes, in particular for drilling. Let's look at a couple of examples for a 4-layer and a 6-layer board.

4-Layer Board

With a 4-Layer board there are basically two ways to create the stack.

You can use two cores, individually drilled and plated and stuck together with pre-preg and then a final drill/plate pass:

In Proteus, we call this type of stackup external layer pairs because the cores are build from the outside in.

You can use one core which is drilled and plated. Then a layer of prepreg/foil is placed on either side of the board, this is cured, etched, drilled, plated.

In Proteus, we call this type of stackup internal layer pairs because the cores are build from the inside out.

6-Layer Board

With a six-layer board, the same procedure would be extended one step further.

With 'external layer pairs' you would have three cores, each individually drilled/plated, then all stuck together with prepeg and then a final drill/plate pass.

With 'internal layer pairs' you would have two cores, each individually drilled/plated, then stuck together with prepreg. Then a layer of prepreg/foil is placed on either side of the board, this is cured, etched, drilled, plated.

This process can then extend to 8-layer, 10-layer or 12-layer boards in the same way.

Note that it is also possible to create different stackups using less cores and more pre-preg with laser drilling passes. This is more complex, more expensive to make and less common but is discussed in the topic on custom layer stacks.

Key Points

  • You need to decide how the board is to be constructed (internal layer pairs or external layer pairs). Proteus can then define the stack for you in the layer stack wizard.
  • The construction of the layer stack is crucial in determining valid drill passes. In turn, this determines what type of via ranges you can use in the PCB. Proteus can set this up for you via the drill span dialogue.
  • If at all possible, you want to set up the layer stack before you start placing and routing the PCB. Changing the layer stack mid-way through design is fraught with danger and needs careful thought !

Defining a Layer Stack

In Proteus, layer stack setup forms part of the New Project Wizard to ensure that the stackup is defined before PCB layout begins. Alternatively, you can set it up from the Set Layer Stack command on the Technology Menu.

If you define the layer stack in one of your PCB templates then each time you start a project from that template the stackup will already be defined.

The layer stack view is a grid of layers corresponding to the number of copper layers together with rows for the core(s) and pre-preg(s). A couple of examples are shown below, first for a 2 layer board (single core with top copper and bottom copper) and then a four layer board made up of two cores. In this case we have a core between top copper and inner1, a second core between inner2 and bottom and then a pre-preg to glue the two cores together.

The first task when you launch this dialogue is to specify the layer stack for your PCB. For the vast majority of boards you can create your layer stack by changing a couple of parameters in the layer stack wizard.

Layer Stack Wizard

The layer stack wizard is the place to define the type of PCB you are working on, together with the materials, thicknesses and dielectric constants. For the purposes of basic stack construction the principle fields are the first two.

The number of copper layers is obvious enough and determines the available signal and plane layers for the PCB. The board style selection then indicates the construction of the PCB and therefore the available drill ranges. This is discussed in some detail in the topic above.

For many users, this will be sufficient information and the default values for the other fields will suffice. The following is a list of where each field on the dialogue is used in the Proteus software.

  • The number of layers and the board style together provide a legal set of drill passes for the PCB. This is used when vias are placed during manual and auto-routing.
  • The number of layers determines the set of layers available in tracking mode.
  • The thickness parameters specified here are used when length matching to add via length to the routes.
  • The entire stackup information is dumped in the CADCAM readme file so that your board manufacturer is aware of your intended design.

Each field is also discussed in more detail in the context sensitive help for the dialogue.

Editing the Grid

There are seven columns in the grid.

ID

The ID is a non-editable column, providing a quick indication of the layer name.

Name

The name is an editable column where you can specify more accurate information about the use of the layer. For example, this would commonly be used with a plane layer to name the layer either VCC or GND. To edit the field, double click the mouse over the name in question and then type the replacement, hitting the enter button when done.

The names of the layers will then be found in the layer selector during tracking and placement operations.

Type

This type of layer is editable according to its function. So signal layers can be changed to be plane layers and vice versa while cores can be changed to pre-preg and vice versa. Surface layers cannot be edited.

The ability to change cores and pre-preg's adds flexibility to the stackup, essentially letting you specify whatever you like. We strongly recommend that you only do this if you are comfortable with the manufacturability of the custom stackup layout and have spoken to your fab house. All standard stackups can be auto-generated from the Layer Stack Wizard.

A layer specified as a plane layer cannot contain tracks. If you specify a net (see below) then Proteus can both autodraw the plane and maintain distance from the board edge. The distance between the plane and the board edge is governed by the Edge clearance design rule. If you are routing on the same net as a zone on a plane layer you can simply double click the mouse to drop a via to the plane and complete the connection.

See Also:

Plane Layers

Thickness

This is an editable column that allows you to specify an individual thickness for a layer. To edit, first double click on the field in question, then type the new value and either hit the enter button or click the mouse elsewhere to confirm.

Information specified here is used by Proteus only to calculate via depth for length matching. The data is also exported along with the rest of the layer stack in the Gerber X2 readme.txt file.

Dielectric

This is an editable column that allows you to specify the dielectric constant for relevant layers. Typically, this is related to the entry in the material column. The information is not currently used in the Proteus software but is exported along with the rest of the board stackup in the Gerber X2 readme.txt file.

Power Plane

This is a read-only column that indicates when a full layer power plane has been placed on a layer. The full layer power plane might have been generated from the button just underneath the grid or from the power plane generator command on the tools menu.

The 'Create Power Plane' is greyed out if there are no nets to attach the plane to. This is typically the case in the New Project Wizard.

It is very common to use this alongside the specification of the layer type to be a plane layer.

About Drill Spans

When a multi-layer PCB is constructed a separate pass of the CNC Drilling machine is required for each drill span. This means that, having set up the layer stack there is a known legal set of drill spans which are possible. For example, in the 4-layer board discussed earlier you could have three drill spans in the case you were using two cores (external layer pairs) or two drill spans in the case you were using one core (internal layer pairs).

External Layer Pairs (4-Layer Stack) | Internal Layer Pairs (4-Layer Stack)
Top Copper to Bottom Copper | Top Copper to Bottom Copper
Top Copper to Inner 1 | Inner 1 to Inner 2
Inner 2 to Bottom Copper |

If this doesn't make sense please refer to the graphics in the layer stack topic. It's important to understand that the method and the sequence in which the multi-layer board is assembled affects the available drill spans.

Key Points

  • Possible drill spans (or drill passes of the CNC machine) are determined by the layer stack.
  • When placing a route with a via, the via will acquire the shortest drill span that allows the track to go from source layer to destination layer. The available drill spans for vias are defined here.

Defining Drill Spans

Like the layer stack wizard, the definition of drill passes in the Proteus software can be almost automatic. The default position is that only a thru-hole via is included because each drill pass of the CNC machine probably adds to the cost of the board. However, Proteus knows at this stage what the layer stack is and can therefore provide you with a set of legal, sensible drill passes via the 'Create from Cores' command in the 'Drill Spans' tab.

If you wish to add a drill span manually, you can do so from this dialogue, entering the source and destination layer manually. This may be because you know that you will need to use blind or buried vias or simply because you removed a drill span and later discovered that it will be necessary.

Proteus will attempt to perform sanity checks before exiting the dialogue form, warning you if you add a drill span which conflicts with another one to make the board un-manufacturable. We would recommend at the minimum that you check with your fab house if you get a warning like this but it they are comfortable with your stackup and drill span options you can simply ignore the warning message.

You can remove any drill passes that you don't need apart from the thru-hole (top->bottom) drill pass. Bear in mind that when you place a via during routing the drill span of the via is chosen as the smallest that covers the source and destination layers.

The information you specify here is used to make intelligent decisions on drill ranges when you (or the autorouter) place a via during routing.

Smart Vias & Layer Pairs

The configuration of the layer stack and the drill passes is important because it makes life much easier when you are routing the board. In particular, Proteus knows the valid ways in which you are allowed to move between layers and so can make intelligent decisions when a via is placed. All that is left is to tell Proteus which signal layer you want to arrive on when you via from a specific layer and this is done via the layer pairs dialogue on the Technology menu.

The idea behind layer pairs is to allow you to create associations between layers This is useful for example when laying tracks – double clicking the mouse will automatically create a via from the current layer to it’s associated layer and continue tracking on that layer. To change a layer pair select a layer from the drop down list that you wish to associate with the layer specified by the text on the left.

It is not uncommon for much of this dialogue to be greyed out; you cannot create associations between layers not in the stackup. Also, only signal layers are shown here because you cannot place tracks on plane layers.

Manual Routing

When you are placing a route you can switch layers by double clicking the mouse. This will drop a via so that you can keep routing without interruption on the destination layer. What is actually happening here is the software is doing the following:

  • Using the layer pairs information to work out which layer you are on and which layer you want to go to..
  • Matching this up to the drill span information to determine the shortest via that will reach the destination layer.
  • Placing a via of this type at the point you double clicked and switching the layer selector to the destination layer.

You can also place a via by pressing the SPACE bar during routing. The process is a little more involved and works as follows:

  • User is placing a track and hits the SPACE bar to float a via on the end of the track.
  • User uses the PGUP and PGDOWN buttons to cycle through destination layers.
  • Users clicks the left mouse to drop the via and continue routing on the destination layer

In this case the via will again be auto-set to the smallest drill range available between the source and destination layers. For example if you had a top->inner1 drill pass and you routed from top copper to inner1 then you would end up with a top blind via rather than a thru-hole via because it's a shorter drill range.

If you add a drill pass, you are basically saying that the CNC machine will be run for this drill range during manufacture. Proteus will therefore make use of all available drill passes automatically during manual routing.

While slightly more time consuming there are times where the floating via method is the better choice. If space is tight on the PCB the floating via is DRC aware and you will not be allowed to place a via in an illegal spot. Also, since you can choose the destination routing layer interactively it is well suited for escaping BGA's and other tricky routing problems where it's not clear what layer you will be using until you are in the process of routing.

Connecting to Plane Layers

Since plane layers cannot contain tracking the procedure for connecting to a plane layer is even simpler. If you are placing a track and want to connect to a plane layer the only thing you need to do is double click the mouse anywhere over (or under) the plane. In this case, Proteus is doing the following:

  • Checking the net of the track that you are routing (e.g. VCC).
  • Looking down (and up) from the layer you are on to find a plane layer on the same net. Plane layers are defined in the layer stackup.
  • Placing a via to the plane layer and terminating the route.

See Also:

Plane Layers

Auto-routing

There are a couple of differences between auto-routing and manual routing. First, you specify the layer pairs in the net class tab of the design rule manager. This has the added benefit of enabling different layer pairings for different net classes.

You also have a choice on a net class basis to decide between normal vias and smart vias. A normal via will always be thru-hole whereas a smart via will use the shortest drill pass available to get the track from the source layer to the destination layer.

Via Mode

You can place a via manually by selecting via mode from the mode selector. When you do this the layer selector will switch to show the valid drill spans for vias as defined by the layer stackup. Select the one you want and then left click to place the via.

Editing Vias

If you right click on a via and select the edit via command you can change the via type manually to any specified drill span.

Key Points

  • Correct setup of the layer stack and the layer pairs will save a huge amount of time during the routing phase of the project.
  • If you add a drill pass, Proteus will use it automatically during manual routing.

Custom Layer Stacks

The layer stack wizard provides a simple and fast way to configure boards for production using standard techniques. Of course, the designer knows best and there are good reasons to create custom stackups. Proteus will allow you to do this as follows:

1) Use the stackup wizard to specify the number of layers.

2) Edit the type fields for the cores and pre-preg's to form the desired stackup.

3) Edit the thickness fields as appropriate.

For example, the 6-layer board below has a stackup normally called 'build-up' comprised of one core and then successive applications of pre-preg plus copper foil. This was created by specifying a 6-layer board (external pairs) and then changing the top two cores to be pre-preg.

We strongly recommend that you discuss any custom stackup with your board manufacturer both for feasibility and for cost.


OBJECT PLACEMENT

Overview

There are five basic types of object in ARES:

  • Components
  • Packages
  • Pads
  • Graphics
  • Zones

All are placed in much the same way although there are some slight differences which are detailed in the following topics.

Placing Components

ARES makes a distinction between Components and Packages in that a component is a part specified in the netlist whereas a package is not linked to the netlist, has no part ID, and plays no part in netlist driven design verification / modification. Assuming you are using a netlist, 99% of the parts you place would usually be components. You would only use packages for parts which, for whatever reason, were not entered on the schematic. Heatsinks are the most common example of this. If a netlist is in use, parts which are not specified in it must not be given names.

To place a component

  1. Select the Component icon from the Mode Selector toolbar. In this mode, the Object Selector lists all components not yet placed.

  2. Choose the component you want to place from the Object Selector.

  3. Set the Rotation and Mirror icons to determine the required orientation.
    You can set the rotation to non-orthogonal angles by typing into the text edit-box.

  4. Set the Layer Selector to determine the required layer. Note that the Layer Selector and the Mirror icon are interlocked, since a reflected component must be on the underside of the board.

  5. Point at the desired position for the component on the board and left click the mouse.

  6. Move the mouse to the desired location – a ‘shadow’ component will follow the mouse at the stage.
    The '+' and '-' keys on the numeric keypad will rotate the component anticlockwise and clockwise respectively in steps of 90 degrees.

  7. When the mouse is over the location that you wish to place the component left click again to drop the component at this point and exit placement mode.

See Also:

Placing Components and the Ratsnest (Tutorial)

After placement, you can edit the component and choose to hide an individual component reference or value. This is often useful in high density areas of a PCB where routing space is at a premium.

Local options to hide part reference and value text.

Note that this is a local override of the global settings. You can control visibility of part references globally via the Set Text Style Command on the Technology Menu. If you make a local change then the part will be unaffected by subsequent changes to global text styles (e.g. fonts).

Components on the underside of the board

When a component is placed on the solder side of the board, it is effectively 'turned over'. This means that it suffers both a reflection in 2D space and an inversion of the layers of its pads. More specifically:

  • The silk screen legend moves from the Top Silk Screen to the Bottom Silk Screen.
  • Pads on the Top Layer only, move to the Bottom Layer and vice versa. This caters for underside placement of surface mount components.
  • Pads on multiple layers - most commonly normal through hole pads - and padstacks are left alone. On the assumption that a padstack has been defined in a particular way to reflect the usage (signal, ground plane, etc.) of a particular layer, it would be unhelpful to invert pad stacks for solder side placements.

You can also place components programmatically via the Goto Position command (View Menu).

Once placed you can move components programmatically via the Move to command on the right click context menu. This will move pin1 of the part to the specified co-ordinates unless the origin checkbox is selected, in which case it will move the part origin to the specified co-ordinates. Note that the part origin may in fact be pin 1.

Placing Packages

As discussed above, the term Package is used to refer to a placed library part which has pins but is not linked to the netlist. In ARES, they are useful in the following circumstances:

  • If no netlist is available, or you are doing a simple 'quick and dirty' job, you can lay out a board by placing packages and wiring them up using traces and vias. In doing this, you are using ARES as a computerised light box, rather than as a true EDA tool.
  • Sometimes you need to place objects which have pads and graphics but are not actually components in the electrical sense of the word. Heatsinks with mounting holes are a common example of this. These can be placed as unlabeled packages, and as such, will play no part in the netlist driven functions of the design work.
  • In order to edit a library-package, it is necessary to place it as a package, tag it and then decompose it using the Decompose commands. The individual elements can then be edited as required prior to re-making the library-package using the Make Package command.

To place a package

  1. Select the Package icon from the Mode Selector toolbar. In this mode, the Object Selector lists all the packages picked from the libraries.

  2. Assuming that the package you want has not yet been picked from the libraries, click the 'P' for pick toggle at the top of the Object Selector.

  3. Pick the package or packages you want from the Library Pick Form.

  4. When you have finished picking packages, close the form in the usual way.

  5. Highlight the package you want to place in the Object Selector.

  6. Proceed from step [3] in To Place a Component above.

A practical example on creating footprints can be found in the appendix to the tutorial.

Placing Pads

The main reason for placing lone pads is when defining a new library-package but they are also useful for test points, drilling alignment targets and mounting holes. ARES offers six shapes of pad, namely: Circle, Square, DIL, SMT, SMT Polygonal and Edge Connector.

In addition, ARES supports pad stacks, in which a different pad shape can appear on each layer of the board.

The various pad shapes may be selected from the Mode Selector toolbar.

Given the selection of a pad shape, an actual pad style of that shape may be selected from the Object Selector. You'll see that all the pad styles have names this is a unique feature of ARES and has two advantages over other systems:

  • There is less chance of confusion or error when choosing a style (provided that you use sensible names!).
  • There is no limit to the number of styles you can have.

Pads are placed in much the same way as components and packages. The Rotation icons affect the placement of DIL, SMT and Edge Connector pads whilst the Layer Selector again determines the layer set of the pads.

You can edit a pad style by selecting it in the Object Selector and then clicking on the toggle. Any changes to the pad dimensions take effect as soon as the display is redrawn you can force a redraw with the Redraw command. This feature is particularly powerful should you find the need to tweak pad styles globally in order, for instance, to change the pad sizes used in the standard package library.

You can also place loose pads and then manually attach them to a net. This is particularly useful for RF work where you want to stitch zones together for example. After placement, simply tag and edit in the normal way and select the appropriate net from the resulting dialogue form

Assigning a Pad to a Net

You can also place pads programmatically via the Goto Position command (View Menu). This will work with either X-Y or R-Theta, depending on your currently specified co-ordinate system.

See Also:

Example: Customising Relief on a Power Plane.

Example: Specifying Minimum Clearance from a Power Plane.

Placing 2D Graphics

The 2D drawing facilities are intended, in the main, for adding text and graphics to the silk screen layers though they can also be placed on other layers by first selecting the desired layer from the Layer Selector. Objects placed on the Edge layer appear on artwork produced from any of the other layers making it a suitable location to draw the board outline.

There are 9 types of standard 2D graphic object, namely:

  • Line
  • Box
  • Circle
  • Arc
  • Path
  • Text
  • Symbol
  • Marker
  • Dimension Graphic Object

Lines are drawn by clicking left at each end.

Boxes and circles are placed by left clicking once and then dragging out the desired area, left clicking a second time to commit placement.

Arcs are placed by drawing a quadrant in the same manner as for a box or circle. They can be further adjusted by tagging and dragging the four handles. ARES arcs are actually Bezier curves.

Paths are closed figures with boundaries defined as multiple line and arc segments. Click left at each required vertex and hold the CTRL key down to place arc sections. Further adjustments may be made by tagging the path and moving the green ‘handles’ about. We strongly recommend that paths are not used to create copper fills as they are not-recognized by the connectivity database. Use zones instead.

Text is placed by clicking once on the Editing Window at the point where you want the text to appear. A form then appears which allows input of the text itself and also allows control of the text dimensions. Text orientation can be set using the Rotation and Mirror Icons.

Selecting the Symbol icon displays symbols in the Object Selector. Symbol selection is identical to package selection as described earlier. More information on the symbol library facility is contained in The Symbol Library.

Markers are used in the creation of library parts to define the origin, and also the position for component labels.

Lines (end points), Boxes (length and width), Circles (radius) and Arcs (end points) can be given specific dimensions once the graphic has been placed. Simply edit the graphic and change the dimensions as preferred:

Setting the dimensions of a 2D graphic.

This does not work for already created packages.

You should always use a 2D Graphics Path or 2D Graphics Box to form your board edge. It is important for the software to know the bounds of the board in order to limit copper flow, auto-routing and auto-placement.

See Also:

The Board Edge (Tutorial)

Dimension Graphic Object

The dimension graphic object is a useful tool for sizing objects and positioning objects relative to one another. You place it exactly like placing a 2D graphics line but it will display the length of the line drawn on completion. This provides an easy and convenient way to take measurements in ARES. By editing the dimension object in the usual way (see Editing an Object on page 86) you can specify which units you want displayed according to the options given below :

Syntax | Description
%A | Automatic Mode. This is the default mode and will use the units currently specified in ARES.
%M | This syntax specifies that the units for the dimension graphic object are millimetres
%C | Specifies units of centimetres for the dimension graphic object.
%T | Specifies units of thou for the dimension graphic object
%I | Specifies units of Inches for the dimension graphic object.

Note that, with the exception of Automatic mode, you can append unit specifiers to the syntax. In the example below the units are entered as millimetres and suffixed with the standard unit specifier.

Dimension settings

Placing Zones

Zones represent the means by which ARES handles power planes. In this section we will just describe briefly how to place a simple power plane; further documentation on power planes is given under Power Planes .

To place a power plane on a layer

  1. Make sure that you have specified a board edge. This is necessary to bound the area into which the zone will be drawn. To do this draw a board outline of the correct dimensions using the 2D graphics tools on the Board Edge layer. Ensure that the boundary forms a closed polygon. The best way to do this is to use a Path object.

  2. Select the Power Plane Generator tool from the Tools Menu.

  3. Select the net, required boundary trace style for the zone, layer for the zone and clearance from the board edge. Each of these options has context sensitive help available direct from the dialogue form.

  4. Hit the OK button to render the zone with the specified options.

To place a polygonal or partial power plane (PCB L2 or higher required).

  1. Select the Zone icon from the Mode Selector toolbar.

  2. Select the required boundary trace style for the zone from the Object Selector.

  3. To define the zone boundary, either:
    - Drag out a box with the left mouse button held down.
    - Click at several points to form a polygonal boundary.

    If a zone boundary is placed over existing tracking, it will pick up its net from that tracking. This makes it quite easy to place lots of small zones in order to ‘fill in’ between tracks.

  4. Select the required net and hatch/fill style from the Edit Zone dialogue form, then click OK.
  5. ARES will generate the ground plane

See Also:

Power Planes and Slots (Tutorial)

Examples: Power Plane Connectivity and Copper Flow Control


Object Editing

Overview

Due to is its object oriented design, all objects in ARES are treated in much the same way and we can discuss generally their dragging, copying, movement, rotation, deletion and editing. You should note that traces and vias are not regarded as objects for this purpose; their editing is dealt with further under Route Placement and Editing. However, there are operations where traces attached to objects are affected by operations performed on the object - such cases are discussed here.

The Selection Filter

Board design by it’s very nature consists of several layers (silkscreen, copper layers, edge layer, mechanical layers etc.). Despite this, ARES provides a modeless selection mechanism where the object under the mouse is identified regardless of whether it is on the current layer. This works extremely smoothly in most cases but the selection filter provides the means by which you can override the default behaviour in a given situation.

The selection filter can be found at the bottom left of the ARES application window

Selection Filter

The purpose of the selection filter is simply to determine which object types are considered ‘hot’ in any given mode. Additionally, the icon directly to the right of the layer selector determines whether all layers or only the current layer are considered to be ‘hot’. By toggling these icons you can therefore have complete control over both which objects and which layers are hot at any given time.

When the mouse is over a ‘hot’ object a visual cue will be given to light dashed line will appear to provide instant feedback telling you what exactly the mouse is considered to be pointing at.

When the mouse is over a 'hot' object it becomes highlighted

Sophisticated algorithms are in place to cater for the cases where, for example, two tracks on different layers are placed in parallel. Whilst the obvious solution is to look for a point on the desired track which is visible on it’s own, the behaviour in such a case is prejudiced by the layer currently selected in the Layer Selector. You could therefore switch the layer selector onto the layer of the trace you want to select and then click on the track.

It is extremely important to realise that this object ‘twitching’ indicates only the object that will be acted upon when you click the mouse. It does not indicate what the action will be (selection, placement, etc.) – indication of action is provided by the mouse cursor and is summarised below :

Cursor | Description
 | Standard Cursor
 | Placement Cursor - Left click will place an object according to the current mode
 | Selection Cursor - Left click will select the current object under the mouse
 | Movement Cursor - Left click will move the current object(s) selected

Using these two visual indicators together provides an extremely intuitive method for both knowing what object the mouse is over and also what action will be performed when you left click the mouse on that object.

Finally, while considerable time has been given to choosing a sensible default selection set for each mode in ARES you can override it if you decide that you prefer to operate in a different way. Default selection filters on a per mode basis can be configured via the Set Selection Filter command on the System menu.

See Also:

The Selection Filter (Tutorial)

Tagging a Single Object

Provided the object is considered ‘hot’ (as defined via the selection filter)any object may be tagged by pointing at it and clicking right. This action highlights the object and presents a context menu containing relevant actions for that object.

Right click to reveal the Context menu

Alternatively, where an object is ‘hot’ and the mouse cursor indicates selection (pointed hand) a left click on the object will select the object

A useful trick for precision movement of a part is to map the ‘Drag Object’ command on to a keyboard shortcut. You can then tag the part, invoke the keyboard shortcut and use the keyboard arrow keys to move the part by a single grid setting.

Tagging a Group of Objects

The normal way to tag a group of objects is by dragging a box around them using the right mouse button. Once the tag box is created, the enclosed space can be refined by dragging the green ‘handles’ as required. The ‘trace bounds’ selection icon can be used to determine whether only fully enclosed traces or partially enclosed traces are tagged.

After placement of the tagbox the selection filter can be used to refine which objects are tagged, providing a live update according to the current configuration – see Block Editing Facilities for more information.

Only one tag box can exist at any one time - drawing a new one will delete the old one, and untag the objects within it.

There are a few operations - notably trace editing - where you can create a selection of tagged objects using the mouse. To do this, first switch to selection mode and then CTRL+left click on each track individually. When you are finished, right click on any one of the tracks to change their width, layer or via style.

Untagging All Objects

To untag all the objects, you need simply to point where there is no object and click left. This will also remove the tag box if one has been defined.

Performing an explicit Redraw command (default key mapping 'R') will also untag all objects this can be handy if the board is very densely packed and there is nowhere free of objects on the screen.

Deleting an Object

Any tagged object can be deleted by pointing at it, clicking right, selecting Delete Object from the resulting context menu. Any traces connected to its pads will remain in place, allowing a different pad or package to be placed over them.

An important and rather subtle distinction exists when you are removing a footprint that has been placed on the board; you can either delete the package directly in ARES or you can delete the associated component in ISIS.

  • If you delete the package directly in ARES any placed tracks that connected to the package will remain.
  • If you delete the component in ISIS then, when you click on changes pending in ARES, both the footprint and the tracks connecting to it will be removed

Dragging an Object

You can drag (i.e. re position) any tagged object by pointing at it and then dragging the mouse with the left button depressed.

Any traces attached to the object will be rubber banded (stretched) unless both ends connect to it, in which case the route will be moved wholesale.

You can also programmatically move a footprint by using the 'Move to' command on the right click context menu.

Editing an Object

Some objects, especially packages, components and graphics text have properties that can be edited with a dialogue form. There are two ways to do this:

  • A tagged object can be edited by pointing at it and then clicking left as if to drag it but without moving it.
  • You can right click on an object and select Edit Properties from the resulting dialogue form.

Locking an Object

You can lock components, packages or single pads on the layout such that they cannot be moved, rotated or deleted. This is useful if, for example, you have connectors or mounting holes that need to be in a specific position on the board and you wish to ensure that they are not inadvertently moved.

To lock an object on the PCB

  1. Place the object on the layout in the specified position.
  2. Edit the object by right clicking to highlight and then selecting Edit Properties from the context menu to launch the resulting dialogue form. Note that for components you must click on the component outline – if you click on a component pad you will get the Edit Pad dialogue form instead.
  3. Check the box at the bottom of the dialogue as shown below to lock the object. Note that only the object types specified above can be locked

The Lock Position check box

While no visible indication of a locked object is provided on the layout (to avoid clutter) you can find all the locked objects on the board as follows :

To find all locked objects on the PCB

  1. Tag the entire board (right click and drag a box) and then attempt a block operation.
  2. From the resulting dialogue box select the option to tag only the locked objects on the board.

Highlighting a Component by Name

When the Instant Edit icon is selected, the Object Selector lists all the components in the design. Clicking on the selector toggle tags the selected component causing it to be highlighted, and zooms in to display it in the centre of the screen.

Alternatively, you can locate a component using the Goto Component command on the Display menu.


ROUTE COMMAND CENTRE

Introduction

The Route Command Centre is the home for all route placement editing and configuration options in Proteus. It can be launched from the Tools Menu or, more commonly, via the 'R' keyboard shortcut. Importantly the keyboard shortcut can launch the dialogue form while in the middle of placing or editing a route meaning that you can make changes or adapt the routing modes at any time.

Route Command Centre Dialogue Form

Accelerators

All the main modes of operation have keyboard accelerators as shown on the dialogue form. It's well worth learning these as you can then make changes straight from the keyboard without needing to launch the Route Command Centre dialogue form at all.

If you want to change the keyboard mappings to something that suits you better or you want to map some of the sub-modes you can do so via the Set Keyboard Mapping command on the System Menu.

Route Command Centre commands can be mapped to keyboard shortcuts of your choice.

Here are the important accelerators in Route Command Centre.

Keyboard | Action
R | Launches the Route Command Centre.
SHIFT+P | Toggles Push Mode on and off. Affects both route placement and route editing
SHIFT+D | Toggles Visual DRC view on and off.
SHIFT+A | Toggles Design Rule Aware Route Editing on and off.

Status Bar

The current routing mode is displayed on the status bar along with other useful information about the current routing operation. This is particularly helpful when you are toggling configuration options with the keyboard because you can check on the status bar what the current operating mode is.

Status bar reflecting the switching of routing modes from Push mode to FMR mode.

Persistence

Route command centre settings tend to persist in the registry, except for the route styling which will always initialise from the net class defaults when you start route placement. In practise we expect a good deal of toggling using keyboard accelerators depending on the routing situation and the configuration can be changed dynamically at any time by launching the route command centre.

You'll get some detailed information on each dialogue item from the context sensitive help. Click on the question mark at the top right of the dialogue form to launch.

Push and Shove Options

These commands toggle push mode on and off and apply to both route placement and route editing.

Push Shove Mode (SHIFT+P)

This is the main behavioural toggle, switching Push mode on and off.

  • When push mode is on the track being placed or edited will move other tracks (and vias where selected) out of the way while maintaining design rule clearances.
  • When push mode is off, route placement happens in FMR mode where you can hug other objects but not move them. Route editing is similarly unable to move other objects on the board.

Normally, you would toggle this option directly from the shortcut key with the current mode being shown on the status bar.

Allow Via Pushing (SHIFT+V)

This allows the route being placed or edited to not only move tracks but also vias as well.

It's very useful but it can disturb routes on more than one layer and therefore require more tidy up. Generally speaking, it's best left on since most via pushes are small nudges.

Bear in mind that via pushing can slow things down a lot, particularly if you are nudging a group of closely positioned vias on a multi-layer board. The best thing you can do to mitigate this is left click to place an anchor as soon as you have moved the vias to a suitable position. Placing an anchor will commit the route so far (you can still unwind by moving the mouse back over the route) and all of those push calculations no longer need to be made on every mouse move as you continue with the rest of the route placement.

If you're trying to push a via and it's not moving it could be blocked by an immovable object on another layer.

If you turn off DRC Awareness (see below) then push editing will have no effect since the track being edited cannot 'see' any other objects to push them.

See Also:

Push Mode vs FMR Mode

Route Placement Modes

These options are specific to route placement and apply regardless of whether Push mode is enabled or not.

Enable Click To Complete (SHIFT+S)

Click to Complete is a calculated solution to the destination shown as a 'shadow track' in front of the route being placed. You can complete the route at any time by pressing the ENTER key.

Notes:

  • When you are pushing tracks Click to Complete will not attempt to find a solution.
  • You may want to turn this option off if you have a very large and complex board and it is causing a performance overhead.

Use Curved Corners (SHIFT+C)

This switches the corner type from mitred to curved.

Curved cornering will typically work less well on dense boards, unless the curved routes are placed first.

You can also choose to change the cornering type of individual or all tracks from the mitre command either on the track context menu or globally on the tools menu. This will present an option to switch the cornering type between curved and linear.

Current Route Styling

The bottom left section of the Route Command Centre allows control of track width and neck width while in the middle of placing a route. These options will all be disabled unless you are in the middle of route placement so to use them you would.

  • Start placing a route.
  • Press R to launch the Route Command Centre
  • Change route and neck width as needed
  • Exit the dialogue form and continue route placement.
  • Repeat at a later point in the route as needed.

By far the most common use of these options will be to toggle necking mode on and off as you route a track in and out of a dense area. You don't need to go into Route Command Centre to do this. SHIFT+N shortcut key will toggle neck style on/off and the status bar will update to show both when you are in neck style mode and also the length of the current neck routing.

Route Styles come from the Net Class as set in the Design Rule Manager. The overrides here allow in route modification but are not intended to be a substitute for setting up net classes properly.

Route Editing Options

The route editing options are primarily concerned with design rule awareness. By default, track editing operations are design rule aware. This is almost - but not always - what you want to happen and will make tidying up the PCB a much easier job. However, sometimes you just want to get things out of the way and are prepared to deal with violations at a later point. If this is the case you can either turn off the DRC awareness off completely or tailor it to ignore components for example when editing tracks.

DRC awareness needs to be turned on in order to push other routes when editing. If DRC awareness is off there are no obstacles and you can edit into an illegal position.

Consider the example below. Here there is no legal edit to be made because our violation is at the component pins. A design rule room needs placing with specific clearances for the IC area but we may want to edit tracks in the meantime. We can't do this with DRC aware editing on because there is no legal solution to the edit, so the process has to be CTRL+A to turn off, edit as needed and then CTRL+A to toggle back on when we're finished.

No track edit will result in a DRC legal position so turn DRC aware editing off.

When editing with DRC awareness off it's a really good idea to have Visual DRC turned on. This will both show you where nearby clearances are and also indicate when the route is in violation.

Meanwhile, the snap setting will constrain editing to the current snap. This is not normally a good idea as it will reduce the number of valid positions for the object being moved and of course will not play terribly well with DRC awareness. However, it may occasionally be helpful in boards where all of the IC's share the same pin pitch.

Finally the minimum segment size provides a way to prevent tiny sliver segments of routes and will restrict the smallest segment of track allowed. This is generally ok but there are times when it causes subtle problems (nearly vertical track between two pads for example) with editing.

Visual DRC Options

Visual DRC provides a viewport around the mouse and each object shows an expansion corresponding to it's design rule clearance in an overlay. This instantly lets you see whether the route being placed/editing can move where you want it to go and then take action such as toggling push mode or changing track style to squeeze through a tight gap.

Visual DRC Auras around Tracks and Vias when placing a route.

You can choose whether only immovable objects or all objects should contribute their DRC 'auras' to the viewport area. Immovable objects are of course every object when in FMR mode but exclude tracks (and most often vias as well) when in push mode. You can also adjust the size of the viewport using the slider options - a large viewport on a dense board may impact performance slightly.

Visual DRC during Editing

If you are editing with DRC awareness on then the Visual DRC display will be exactly the same as during placement, showing you the clearances of nearby objects. However, when you turn DRC aware editing off (e.g. because the track is already in violation) Visual DRC gains two additional capabilities.

Track in Violation

The border of the Visual DRC viewport will highlight whenever any part of the route is in violation. This is an important indicator, particularly on large routes where the route segment in violation may not be the one you are editing or where editing brings the route into violation somewhere outside the screen area.

Viewport border colour indicates a violation somewhere on the route (via below).

Viewport Track in Violation

Trace segments and objects which are in DRC violation with the currently edited route inside the viewport will be highlighted. This allows for fine control during editing, allowing you to zoom in and carefully position the route without creating a DRC error.

Violation inside the viewport area is highlighted as well.

Make sure you do not have snap to grid on when attempting fine control editing operations.

Note

Visual DRC is a guidance for route placement and it is possible in some narrow circumstances to route inside the clearance 'shroud'. Consider the case below:

Net #00005 has vDRC clearance from the Room rule until the tertiary junction.

Here the pad connected to net #00005 is partially inside a DRC room with a large clearance. For performance reasons the vDRC clearance shroud covers the entire segment of track, even though the actual clearance changes as we exit the design rule room. This means that, as shown above, it is possible to move inside the shroud in that segment area outside the room. This is unlikely to happen but possible and therefore worth mentioning. The route will stop (or push) at the actual pad->trace clearance at the point of intersection. It is only the DRC Visual which may not be up to date on a route segment that traverses a design rule room. The live DRC system, violations and clearances are unaffected.


Route Placement and Editing

ROUTE PLACEMENT & EDITING

Overview

The Proteus layout software is equipped with many powerful features to help you place and then edit routes manually. In this topic we are assuming that your project has both a schematic and a layout so that the connectivity defined on the schematic forms the basis for the route placement on the layout.

Pre-Routing Checklist

There are several pre-requisites before you start routing your PCB. You should :

  1. Have a board edge.
  2. Define your layer stackup and drill ranges.
  3. Specify design rules for the board.
  4. Consider Layer Pairs.
  5. Consider power planes / zones.

Board Edge

You need a board edge to define the size of the PCB that is being made. If you don't place one at the beginning both your component placement and your tracking is likely to need extensive editing later.

The Board Edge (Tutorial)

Layer Stackup

Defining the layer stackup allows you to specify plane layers directly and also lets you set up drill ranges for vias. Proteus can then use this information when routing to place vias with the most appropriate drill range.

Layer Stackup

Design Rules

Without design rules, Proteus has no idea how close objects are allowed to be to other objects. When you place tracks manually Proteus will ensure that all the design rule clearances are honoured so it's really important to set them up first.

Design Rules

The net classes tab also lets you set track thicknesses for tracks in the same class (e.g. POWER , SIGNAL, MAINS, ..) as well as via sizes. If you set this up at the beginning then the correct track widths will be selected when you start placing a track.

Net Classes

Layer Pairs

When you are placing a track and you place a via Proteus needs to choose a default destination layer to continue tracking on (e.g. TOP copper -> BOT copper). These defaults are defined in the layer pairs dialogue but if you have multiple signal layers you should review these and make any necessary changes.

Layer Pairs (Tutorial).

Power Planes

If you set up plane layers or manually place power planes early then they will become valid targets for terminating a route. For example, when routing you can double click to place a via. Proteus will know you have a plane layer and (from the stackup / drill ranges) that it can terminate the via and connect. This is a matter of personal choice but can prove a timesaver for things like connecting bypass caps.

Power Planes

Basic Route Entry

Once everything is set up the act of route placement is actually fairly simple. Here is a walkthrough of the basic process.

First, you select track mode and switch to a valid layer.

Next you left click on the centre of a pad to start a connection.

You'll notice that if you set up net classes as in the topic above and you have auto-trace selection enabled from the Tools menu then Proteus will select a track of the correct width automatically when you start routing.

You'll see a guide arrow to the nearest destination if you are on the same layer you will most likely also see a 'shadow track'.

You'll also see a circle around the mouse and objects inside the circle which are obstacles (can't be moved) will be expanded to show their design rule clearances. If you are NOT in Push mode, then you will see that all obstacles will have their DRC area highlighted:

Visual DRC in FMR mode showing the clearances in the area around the mouse.

Visual DRC (by default) shows the clearances around immovable obstacles. What you see will therefore differ in push mode (where some objects can be moved) and FMR mode (where all objects are immovable).

You can either move the mouse to guide the track towards the destination or simply hit the ENTER key to automatically complete the track. In practise you'll find that auto-completing simple tracks is a great timesaver but that you need to give some manual guidance for more complex tracks.

If you need to place a via either press the SPACE bar to position a via on the end of the mouse or just double click to place one at the current mouse position.

Here you will switch to routing on the layer defined in the layer pairs dialogue as discussed in the topic above.

As you route the track it will step away from all the objects according to the design rules.

Left click the mouse at the center of the destination pin to complete the connection.

Sometimes, if you have switched to a fine snap and you are at high zoom then it's hard to find the pad center and the snap distance is too small to be of much help. Switch to a higher snap level (e.g. F3) so that Proteus can help snap the mouse to the pad center.

Push Mode vs FMR Mode

There are two main ways to route in Proteus, namely Push mode and FMR mode. You can toggle the routing mode at any time with the SHIFT+P keyboard shortcut.

Push Mode

This is the default mode and allows you to move tracks and vias out of the way of the route being placed while obeying all design rules. Generally faster and more productive routing as it doesn't involve a lot of manual editing to make space for route placement. Also superior in densely packed regions of the board.

Notes:
  • You can't push length matched routes or diff pairs.
  • You can't push routes on net <NONE> as otherwise you couldn't connect to them.
  • You can choose whether or not to push vias from the Route Command Centre (keyboard 'R').
  • Pushing non 45 degree tracks is unlikely to give a sensible result. Pushing quadrant arc curves is fine.

FMR Mode

This is also a fully design rule aware routing mode but will treat all objects as immovable. Useful for hugging tracks and where you want total control over all route topology. FMR mode is also needed if you want to place routes with curved corners as this is not currently supported in Push Mode.

Mode Switching and the Status Bar

You can switch between modes using the SHIFT+P keyboard shortcut. This will work at any time including during route placement, meaning for example that you can start placing a route in push mode and then switch to FMR mode to hug another route. The current routing mode is shown along with other route information on the status bar during route placement.

Switching modes displays on the status bar during route placement

Route Command Centre

You can fully configure routing from the route command centre (keyboard shortcut R). This will also work at any time, including in the middle of route placement. This provides another way to change routing modes (although less fast) but also gives you control over what objects are pushed and the size of the Visual DRC display for example.

Route Command Centre (Keyboard Shortcut 'R') is the place to configure manual routing options.

See Also:

The Route Command Centre

Troubleshooting / Common Issues

Unconstrained Routing Mode

This routing mode has no knowledge of design rules, net classes or other information. Proteus is blind when you use it so we strongly recommend it is used only when necessary (e.g. an elliptical arc in an antenna design).

There is a third routing mode which we include here for completeness.

Unconstrained Routing Mode can be turned on from the Tools Menu.

Unconstrained routing mode is a legacy routing mode which has no knowledge of design rules and works to a much simpler algorithm. It does however, allow the user to do absolutely anything (with trace angle lock off), including the drawing of elliptical arcs which may be useful in some antenna design for example.

Turning this on will disable the Route Command Centre and all Proteus 'routing intelligence' (notably design rules!). Making any change to Route Command Centre or normal use keyboard shortcuts will disable unconstrained routing mode and switch back into the normal use paradigm as discussed in the rest of this topic. You can also turn it off from the Tools Menu.

Notes:
  • This mode does interact with Trace Angle Lock so any angle routes requires the disabling of this feature. Note that such tracks will be difficult to edit subsequently because they will be at arbitrary angles. Remember to turn trace angle lock back on as soon as you are finished !
  • Elliptical curves can be drawn in this mode by holding the CTRL button down while routing. Note that normal curved routing is done in FMR mode and is fully DRC aware and compliant. These curves can also be easily edited.

Actions and Hints

There are a number of actions that can affect route placement and also a number of hints that the software provides to help guide route placement. These are discussed below:

Options

These are all toggles available at the top of the Tools Menu in the Proteus layout module. We'd recommend leaving the defaults unless you have good reason to change.

Mode | Description
Auto Track Necking | Enable the automatic narrowing of the track to the neck style (specified in net classes) in cases where it cannot fit or connect at full width.
Auto Trace Selection | Enable the automatic selection of the track style (width) when route placement begins. The track style is defined in the net classes tab of design rule manager.

Actions

Keyboard | Action
Left Click | Left click while placing a track commits the bit already completed (places an anchor). Also terminates the track at a pin or other connection.
Double Click | Places a via at the current mouse location and continue routing on the next layer (as defined in layer pairs dialogue).
Right Click | Terminates the track at a point in space.
R | Launches the Route Command Centre.
SHIFT+P | Toggles between Push Routing Mode and FMR Routing Mode. When editing other tracks and vias will push with Push mode on and be obstacles with push mode off.
SHIFT+D | Toggles Visual DRC view on and off.
SHIFT+C | Toggles corner type between mitred and curved.
SPACE | Floats a via on the end of the track. You can then move the via to desired location and left click to place. Can also use up/down arrow keys to select the via depth / drill range.
ENTER | Auto-complete the route according to the shadow track shown.
F2-F4 Keys | Change the snap level. Normally, this is fine at defaults but you probably don't want a really fine snap when terminating tracks as it makes it harder to snap to centre of pin.

Hints

Hint | Description
 | Shows you proposed route from last committed place to the mouse position. Click left to place an anchor and commit or move mouse to adjust.
 | Shows you the track that would be placed if you click ENTER to auto-complete the route.
 | Shows you the path to the nearest connection on the current layer.
 | Shows you the path to the nearest connection on a different layer (there are no possible connections on the current layer).
 | Shows you that current route position is illegal OR that you are pushing tracks into an obstacle. Try neck style or move mouse to route in a different way.
 | Cursor change and status bar change shows you are pushing more objects that are allowed. Normally this happens when you are also pushing vias which in turn are pushing objects on multiple other layers as well. You can left click to commit track so far and reset the pushed object count or move the mouse backwards and try a different way. You might also look at launching the Route Command Centre (keyboard R) and disable the pushing of vias.
 | Shows you the design rule clearances of nearby objects (SHIFT+D to toggle). Configurable in Route Command Centre ('R' Shortcut)
 | Shows you that the track being edited has a DRC violation somewhere on it's length. Only applicable when DRC Aware Editing is turned off (SHIFT+A to toggle).
 | When the route being dragged gets too close to another object in the viewport it highlights to warn of the violation. Only applicable when DRC Aware Editing is turned off (SHIFT+A to toggle).

Status Bar

During route placement the net being routed is displayed along with the routing mode, the track style and the current length of the route.

If you are pushing more objects that the allowable limit you'll end up not being able to push any further and the Push text will change to reflect that:

Most commonly this will happen when tracks you push are tied to vias because then you'll be pushing the tracks on the other layer as well as the vias and the tracks on the current layer.

If you switch to necking mode the style will update to reflect that and the length will change from the total route length to date to the current length of necked route.

In diff pair routing mode the status bar is identical except that the net display changes to say 'fatroute', reflecting the fact that two nets are being routed together.

When editing routes you will now also see the live length of the route as it is dragged along with information on the current editing mode.

If you try to make an edit which is not possible the status bar will show an error message. This includes the currently set minimum segment length (as per Route Command Centre) as this is often the reason the edit can't complete

If you try to push edit tracks which are at non 45 angles it will not work. Quadrant arc curved mode corners are fine and tracks placed normally are fine but tracks placed in unconstrained routing mode will have any angle properties and the push algorithm will perform poorly.

See Also:

Manual Routing Examples

Curved Track Segments

Proteus fully supports curved tracks and supports them as true arcs for output purposes. The segments also play a full role in connectivity and design rule checking. To toggle curved tracks when routing you use the SHIFT+C shortcut key or you can enter the Route Command Centre ('R' keyboard shortcut) and change the settings manually.

Then to place a curved segment, first commence routing as usual (e.g. click left on a pad) and route as normal. Move the mouse roughly to trace the arc, click left to fix the arc endpoint and then continue onward. You can place a curved segment at any stage of laying a route - it does not have to be the first or last segment.

Curve tracks placed in normal routing will be fully design rule aware and will avoid obstacles in exactly the same way as linear tracks. However, they are limited to circular quadrants; if you need a truly elliptical curve you must first switch to unconstrained routing mode from the Tools Menu. Be aware that the trace placement will no longer with aware of board constraints so you'll want to switch back to normal routing (SHIFT+P or toggle the menu command) when you are finished !

Sometimes it might be better to try routing in push mode and then converting to curves when you are finished placing the route. This can be done from the mitring command on the route context menu.

Auto-Track Necking

In many cases, the reason for necking down a track is so that it can pass between two pads or other obstacles without violating the design rules. The Auto Track Necking feature allows Proteus to do this for you.

In order to auto-neck during routing you need to pass through the gap in a straight line (i.e. not at an angle). The track neck will appear once you are more than half way through the gap.

The neck thickness is controlled by the Design Rule Manager command on the Technology menu. The dialogue form allows you to enter the clearances for pad-pad, pad-trace and trace-trace and also the trace style to neck to. The default neck style is T10 - a 10 thou track.

To disable ATN totally, use the toggle command on the Tools menu. You may find this speeds up route placement considerably, since the analysis involved in performing ATN can be quite complex, even if the end result is that the route is OK.

When placing a route you can force the use of necking style using the SHIFT+N toggle or from the Use 'Neck Style Checkbox' in Route Command Centre. Since this is actioned specifically by the engineer it's pretty much infallible. Left click to anchor, SHIFT+N to toggle neck style on, route as needed, left click to anchor, SHIFT+N to toggle back to normal routing style.

Advanced Routing with Necking

Trace Angle Lock

Trace Angle Lock is enabled by default and cannot be turned off when routing using DRC aware Follow-Me-Routing or Push Routing. Turning Follow-Me-Routing off via the Tools menu allows you to then turn off Trace Angle Lock. We would expect this to happen almost never but provide the information below for completeness.

Do not turn this off without good reason. If you have a good reason, turn it back on again as soon as you can. It's an important tool in keeping a tidy, maintainable layout. Push editing will work poorly if at all with non 45 degree angles on tracks.

Most people like to keep all tracking running at either 90 or 45 degrees as this gives a tidy, professional look to a layout. To make this easier, ARES has a Trace Angle Lock command which restricts route segments to 90 or 45 degree angles only.

TAL also has a more subtle effect when combined with Real Time Snap. Consider the following routing problem... You are trying to route from a pad on the grid to one that is off it. You have moved down, clicked left and moved the pointer over to the destination pad. Real Time Snap has detected the pad, and the cursor has locked onto it. However, because your first click left was on a grid dot, the horizontal part of the track doesn't line up with the pad centre. The diagram below shows the position at this stage:

TAL set to 'Off'

When Trace Angle Lock is enabled, clicking over a pad or track in this circumstance will activate Trace Angle Fixup. The result is that the previous node - in this case the route corner, is moved so that trace angle lock rules can be maintained. The result is a tidy connection as shown below.

TAL set to 'On'

Tagging a Route

To re route, delete or copy a section of tracking requires that you first tag the route containing it.

To tag a route

  1. Ensure that the trace selection icon on the Selection Filter is enabled.
  2. Point at an exposed part of the route on the selected layer, and click right. This will both select the route and present a context menu of appropriate actions that can be performed on the route.

Provided that you are not in trace mode (or put another way, that the mouse cursor is a selection cursor – pointed hand – when over the trace) you can simply left click to tag the route.

To tag a section of a route

  1. Ensure that the trace selection icon on the Selection Filter is enabled.
  2. Point at an exposed part of the route on the selected layer, and click right. This will both select the route and present a context menu of appropriate actions that can be performed on the route.
  3. Select one of the Trim options from the bottom of the context menu.

If you select Trim Manually then the point at which the mouse was clicked becomes an anchor point and you can move the mouse to the other anchor point, left clicking to select the section of trace between the endpoints.

Right click and select 'Trim Manually'

Please note that you cannot select sub-sections of tracking that run through pads, vias or T-junctions using this method.

Changing the Width of a Route

Proteus provides a few methods of changing track width. The first relies simply on the general ability of ARES to cope with new objects being placed over old.

To change the width of a Route during Placement

  1. Press 'R' to launch the Route Command Centre.
  2. Change the width from the options provided on the left hand side. Select either Current Position or From Start as appropriate.
  3. Hit OK and continue routing.
  4. Repeat as needed.

Change the Trace Styles mid-placement via the Route Command Centre.

To change the width of placed tracking by overplacement

  1. Ensure that there is no tagged route, and that Auto Trace Selection is disabled on the Tools menu.
  2. Select the new trace style in the Object Selector.
  3. Place the new tracking directly over the old. ARES will work out that there is overplacement, and will replace the old tracking with the new in the database.

The second follows the principle of allowing various editing operations to be performed on the currently tagged object.

To change the width of a tagged section of tracking

  1. Tag the required section of tracking as described under Tagging a Route. The Object Selector will display the current trace width. If the tagged route has several widths, then the width at the point under the cursor is displayed.
  2. Click right on the tracking to display the context menu.
  3. Select a new trace style from the menu.

To change the width of multiple tracks

  1. Switch to selection mode and then CTRL+left click on tracks to select them.
  2. Click right on any one of the selected tracks and select a new trace style from the resulting context menu.

Changing the Layer of a Route

To change the layer of a tagged section of tracking

  1. Tag the required section of tracking as described under Tagging a Route.
  2. Click right on the tracking to display the context menu.
  3. Select a new layer for the tracking from the menu.

To change the layer of multiple routes

  1. Switch to Selection Mode.
  2. Adjust the Selection Filter to single layer only.
  3. Use CTRL+Left Click to select the tracks you want.
  4. Right click on one of the tracks and select the destination layer from the context menu.

It is quite easy to makes mistakes such as orphaning tracks or leaving stray vias when changing routing layers. Check carefully after the operation is complete.

Modifying an L45 Route

The goal of route editing generally is to transform the route according to mouse movement while maintaining neat L45 routing. You can if needed turn off Trace Angle Lock and route any angle but in the general case the result will be less tidy and involve more small segments. We'd recommend therefore that unless necessary trace angle lock (Tools Menu) is kept on for route editing operations.

For multi-track editing where the route being dragged hits another route the rules for route editing behaviour can be broadly summarised as:

  • When Design Rule Aware Editing is on (the default) the system knows about other objects on the board and will avoid violations. If you turn this off Proteus is entirely blind and you can edit a track anywhere, including through other tracks and components.
  • When Push mode is on (the default) editing tracks will push other tracks out of the way so long as Design Rule Aware Editing is on. When Push mode is toggled off editing tracks will hug other tracks so long as design rule aware editing is on.

The most common usage is likely to be in push mode as that will maximise space on the layout. However, there are times when you want specifically to hug another track and toggling push mode off will do that.

Shortcut | Action
SHIFT+P | Toggles push mode on and off. Note that this setting applies to both route placement and route editing.
SHIFT+A | Toggles design rule aware editing on and off. This should only really be turned off if you are in a position where a legal edit is impossible (e.g. you've changed pad->track design rules and existing tracks are in violation)
R | Launches the Route Command Centre where all route options can be found

To modify an existing track

  1. Tag the route as described under Tagging a Route.
  2. Drag the segments and/or corners of the route using the left mouse button.

The rules of track manipulation are detailed below:

If you drag horizontal or vertical segments, they will move horizontally or vertically respectively preserving the angle between the adjacent segments.

If you drag inwards on a route corner then the adjacent segments will break into an L45 route, resulting in a 45 degree mitred corner.

You cannot drag outwards on a 90 corner (unless you turn off Trace Angle Lock). If you want to move a segment then you should drag the segment as above.

If you drag a 45 degree corner you can again do so inwards and it will create two new segments while maintaining L45 routing.

If you drag in the middle of diagonal segments with trace angle lock off then the diagonal segment will move such that the angle between the tracks at both ends of the segment is preserved.

If you drag in the middle of diagonal segments with trace angle lock on then the behaviour depends on the angle of the diagonal. If the angle is a multiple of 45 degrees then dragging will be as when trace angle lock is off (see above). However if the angle is not a multiple of 45 degrees then a new corner will be created. This is designed so that, in the common case of adjusting a mitre preserves the angle between the diagonals.

This last situation puts you entirely in manual mode. Once the route is no longer L45 all edits will be 'pulling points' instead of dragging segments. To be avoided unless necessary.

As you edit routes you can see the length of the route as well as the net and the current status of DRC Awareness on the status bar.

While these rules may seem a little obscure in textual format you should quickly find them both easy and intuitive to use.

To re-route a section of tracking

  1. Tag the route as described under Tagging a Route .
  2. Place a new section of tracking starting and finishing on the tagged route. ARES will then remove the section of tracking that the new route shorts out.

Note that vias which are made redundant (i.e. secondary vias) will also be removed, along with the shorted out section.

Modifying a Curved Route

Modifying a curved route with Push editing is the same as modifying an L45 route as described above. Namely, if Design Rule Aware editing is turned on, then push editing can be toggled via SHIFT+P. If design rule aware editing is turned off then push editing is off because there are no longer any obstacles on the board to be pushed. These options can also all be controlled from the Route Command Centre

Curved corners can be dragged towards 90 degrees.

By default, the minimum curve radius is an automatic value but you can override manually on the Mitre dialogue form (Edit Menu).

You can also drag curved corners inwards, enlarging the radius of the curve until one of the adjacent segments hit the minimum length.

Straight segments between curves can also be dragged. In the 'C' topology the curve can be dragged inwards (radii getting smaller) until we hit the minimum as discussed above or outwards (as shown below) until we form a semi-circle.

An 'S' topology is slightly more complex. In this case, the segment length is maintained and the segment position is moved with the cursor. The curves either side increase and decrease radius in equal magnitude in order to facilitate the translation of the 'moving segment'.

Note that you cannot edit the curves (serpentines) applied to differential pairs or length matched routes in this way. Dragging a length matched serpentine instead will allow you to position the serpentine in a different part (end) of the route.

Remember you can only place curved routes in FMR mode, using SHIFT+C to toggle curves on and off. You can also convert L45 mitres to curves globally via the Mitring command on the edit menu or locally to a single route via the right click context menu.

Design Rule Aware Route Editing vs Guided Route Editing

By default route editing is design rule aware and so all of the techniques above require enough room on the board to complete. The other mode of operation is known as guided route editing with SHIFT+A toggling between modes and the current mode being shown on the status bar.

When you are in design rule aware editing mode you can't drag a route into violation and everything is safe. However, there are times when there is no legal solution to a route edit. If for example a pad trace violation occurs at the pin connection there is likely no route edit that will be design rule compliant. What you'll see in this situation is a run-once error box and a status message prompting you to toggle DRC awareness off for the current route editing operation.

You can't make a DRC aware route edit when the route is already in violation.

When you are working with drc aware editing switched off (in guided mode) it's a really good idea to make sure Visual DRC is turned on because this will help the edit in two ways:

1. The border of the viewport will change colour if a violation occurs anywhere on the route. This is especially helpful for large routes or at high zoom where the problem may be off screen.

2. If you move into violation with an object inside the viewport that object will change colour to show the violation. This makes it easier to make fine adjustments.

Violations in the viewport are highlighted to allow dynamic editing.

If Design Rule Aware route editing is off then by definition Push editing is disabled since there are no objects contributing obstacles to be pushed.

Default ON or Default OFF ?

We have set Design Rule Aware editing defaulted on because it's a safer option and you can only push edit when the system knows about design rules and clearances. However, it is situation dependant and also a matter of preference. There may well be a lot of violations caused by a component move for example and DRC awareness needs to be toggled off for all of the resultant tidying. Also, some engineers prefer to sort localised design rules (design rule rooms around large IC's) at the end of the routing phase and so work with a lot of violations as a matter of course. In this situation you're best just leaving DRC awareness off altogether and then turning it on for space saving drags or final tidying.

Both modes are useful so the best option of all is to learn the toggle shortcut and then switch between modes according to the situation.

Auto-Completing a Route

When routing tracks on the PCB Proteus will now search ahead of the mouse and display a shadow track to a legal destination. You can then simply hit the ENTER button on the keyboard to automatically complete the route as shown by the shadow track. The shadow track will update as you route with the mouse. This allows you to guide the process and then auto-complete when you are happy with the result.

Auto-complete is on by default but can be turned off via Route Command Centre or SHIFT+S. For performance reasons Auto-Complete will not be available for a route if the destination is on another layer or if tracks have been pushed.

Length Matching Routes

Length tuning or length matching is often used with higher speed or longer distance signal runs on the PCB to improve signal timing or signal integrity. The basic idea is that the shorter trace follows a detour or meander in order to lengthen it to match the length of the longer trace. Length matching can be configured from the 'Configure Length Tuning' command on the Technology menu and tracks can then be length matched by selecting the routes and then choosing the appropriate match command from the right click context menu.

See Also:

Length Matching Tracks

High Speed Routing Examples

Teardrops (on Pads)

Placing teardrops at the connection point between track and pad is often useful in preventing drill breakout during board manufacture. Proteus includes both a global configuration for teardrops and a local override on a particular pad/connection.

Global Configuration

The teardrop configuration dialogue is launched from the Technology Menu as shown below.

The two checkboxes at the top enable teardrop connections globally for through hole and surface mount respectively. Where teardrops are used they would normally be applied to drilled pads only; the option for undrilled pads is included for completeness.

The annular ring setting gates the creation of the teardrop on the copper thickness between the edge of the hole and the edge of the pad. You can therefore specify a maximum annular ring size below which a teardrop connection will be made. In undrilled pads the distance considered here is centre pad to furthest pad edge.

The teardrop length setting controls the depth from the pad onto the track with which to form the teardrop. It is set as a proportion of the width in order to ensure a consistent gradient/shape across various pad sizes on the PCB.

Teardrop Configuration Dialogue Form.

This length should be considered as a maximum teardrop length. If the length that the teardrop extends onto the track is longer than the section of track (because of a corner), the teardrop will be shortened such that it fits onto the connecting section of track.

If the generation of a teardrop connection would violate a design rule then it will not be generated at all.

Teardrops are dynamic. After placement you can edit the track entry point to the pad and the teardrop will re-generate automatically. Once enabled teardrops will automatically be created on route completion or edit.

There is a modest performance overhead to turning teardrops on early in the design process but on an average sized board it shouldn't make too much of a difference with a modern PCB.

Local Override

The edit single pin dialogue allows you to control the teardrop connection to a single pad. The default is the global configuration settings as described above but you can either force enable or force disable if necessary.

Note that teardrops are fully design rule aware and will not be added in cases where their presence would violate an existing design rule.

Teardrop Tutorial Movie.

Teardrops are fully DRC aware and therefore are dependant on the netlist. Clearing down the netlist will remove all teardrops on the board.

Troubleshooting

When teardrops don't appear where you would expect it is normally for one of three reasons:

  • Incompatible annular ring.
  • Incompatible teardrop length.
  • Design rule errors.
Annular Ring

In this example the teardrops are not present because the radius of the BGA ball is larger than the maximum annular ring value. Where a pad is undrilled the distance measured for annular ring is from center pad to edge where track connects. The solution is to increase the size of the annular ring - setting to 13th in this example would cause the teardrops to render.

Teardrop length

In this example there is no teardrop into the long finger pads of the IC. Since the connection is made to the short side of the rectangle (width) the distance measured for 'annular ring' is from center pad to that side which is normally greater than the specified teardrop length. In summary, the teardrop would be hidden by the copper of the pad. If you really want teardrops here you would need to increase the teardrop distance value to more than half the length of the pad. However, this would likely result in some odd looking teardrops elsewhere.

Design Rules

In this example, there is a teardrop missing from one of the vias. The distance between the top of the via and the track above is 5th. The pad to pad clearance is specified as 5th and so this is fine. However, the teardrop would render from the top of the pad and the trace to trace clearance is specified as 6th. The teardrop cannot therefore render as it would violate the design rules to do so. The solution is normally to adjust spacing on the layout accordingly.

Teardrops (on Tracks)

Teardrops on tracks - commonly known as track tapers - are small shapes designed to gently adjust the width of the track from the normal routing size down to the necked routing width. The goal is to avoid the sudden change in width seen with a severe change in track size. The tapered trace adds an angled piece of copper to taper the track thickness improving the mechanical structure of the change in thickness. Trace thickness changes can be there for mechanical reasons (like routing from a flexi area to a rigid area) or for signal integrity reasons where a high speed line needs thinner tracking to connect to a terminating pin/ball. It can also be helpful in impedance control with RF routing.

Functionally, the teardrop between the thick and thin tracks behave identically to those between a pad and a track. Track tapers are enabled from the same teardrop configuration dialogue form (Technology menu) and the tapering length is a function of the track width to ensure consistency across the board. Track tapers are also dynamic and will re-generate after route edit operations.

See Also:

Teardrops (on Pads)

Mitring a Route

Proteus will allow you to mitre the tracks on the board either as a global command on all the tracks on the board (via the Edit menu) or on a per track basis (by right clicking on the track). This is typically at it’s most useful as a post routing step to minimise track length or to avoid solder traps.

Mitre traces from the Edit menu (Left) or by route context menu (Right)

The resulting dialogue depends on which of these options you select. The most common (and useful) would be to transform a single route - or selection of routes - locally via the context menu. To do this either:

  • Right click on a single route and invoke the Mitre command from the resulting context menu.

OR

  • Hold CTRL down and left click to tag multiple routes.
  • Right click on one of them and invoke the Mitre command

Local Mitring Dialogue Form

This allows you to change minimum and maximum mitring distance based on track width or absolute units. You can also set the cornering type between linear and curved and, importantly, check the box to convert existing corners. This checkbox together with the cornering type is what enables you to edit and change existing routes. If the checkbox was not selected only 90 degree corners would be mitred.

Things are largely the same if you choose to effect a global mitre change via the edit menu command.

Global Mitring Dialogue Form

The only difference here is the enforce minimum distance in route editing checkbox. This is discussed in the curved route editing section above, although it applies also to normal segment dragging.

Important Note:

One common item of confusion is what a mitre actually is. A mitre is a corner cut out of two 90 degree routes. It sounds obvious but it's easy to be confused why a mitring command has no effect. For example, the following is not a mitre and so any mitring commands will not impact this route at all.

Note that running the unmitre command after a mitre does not guarantee that the board will be returned to the condition it was in prior to mitring. For example, you may have manually mitred tracks on the board which will be unmitred by a global unmitre. If you want to undo a mitre operation directly you should use the undo command (CTRL+Z on the keyboard by default).

Copying a Route

To duplicate a route

  1. Tag the route as described under Tagging a Route .
  2. Click right on the tracking to display the context menu.

  3. Select the Copy command.

  4. Click left at each position for the duplicate routes; click right to finish.

This feature provides an excellent way do memory buses and other repeated patterns of tracking

Deleting a Route

To delete a route

  1. Tag the route as described under Tagging a Route .
  2. Click right to display the context menu.
  3. Select the Delete command.

Any interconnections specified in the netlist that were formed by the deleted tracking will automatically appear as ratsnest lines.

Note that you can also delete all tagged tracking by using the Block Delete icon. This can be quicker than the above procedure if no other tracking is tagged.

To delete a section of a route

  1. Right depress the mouse at the start of the section of route you want to delete.
  2. Drag the mouse to the end of the section of track you want to delete and release the right mouse button.
  3. The section will now be highlighted – proceed as outlined above to delete.

See Also:

Deleting a Route (Tutorial)

Tidying the Routes

Extensive route editing can lead to the creation of unwanted secondary nodes between tracks segments that join at 180 degrees. These nodes waste memory and also degrade the quality of plotted output. One of the processes carried out by the Tidy command is to scan for and remove such nodes.

The Tidy command may be found on the Edit menu.

Route Placement - No Netlist

We do not recommend professional board layout without the benefit of a schematic and a netlist as it renders Proteus blind to connectivity and severely limits functionality such as power planes.

Placing a new trace on the primary layer is done by first selecting the Trace icon and the required trace style from the Object Selector and then left click to start placing a trace. Placement will follow the path of the mouse while obeying the default board constraints as defined in Design Rule Manager. Left clicking at consecutive nodes (change of direction) will commit the route placement to that point and right click will finish track placement.

Double clicking the mouse will place a via if it is legal to do so and routing can then continue on the associated layer as defined by the Layer Pairs command. Hitting SPACEBAR will float a via on the end of the mouse and a single left click will then deposit the via and switch layers. Floating vias have the advantage of snapping to valid destinations (such as via under SMT).

The type of via used will be defined by the drill passes and layer stackup for the project. The drill range of the via will be the shortest available, given the specified drilling passes. You can also place, replace, tag, drag and delete vias manually in this mode. The mouse buttons work in the same was as for ordinary objects.

You can change layers whilst routing using the Layer Selector keyboard controls. The default controls for these commands are PGUP, PGDN, CTRL-PGUP, CTRL-PGDN – you can configure your own shortcuts via the Set Keyboard Mapping dialogue on the System menu.

Should you start to enter a trace, and then decide you wish to abort it entirely, simply press the ESC key.

Troubleshooting Route Placement

Performance Problems in Push Mode

This normally happens because a lot of objects are being pushed. Bear in mind that a via push can in turn push multiple tracks on different layers, some of which in turn might push other tracks as well. In order that you can move backwards and unwind all of the pushes at the same time these push calculations need to happen every time the mouse is moved until you commit the changes (even if you are past the objects you've moved). So, if you simply keep routing without anchors things will slow down. The best way to use push mode is:

  • Push object(s) until you're happy with their current position and can proceed past them in the way you want.
  • Left Click to place an anchor. This commits everything to date, including all the objects - no more push operations.
  • Repeat as needed.

Cancelling the route and pressing undo (CTRL+Z) can return everything to the way it was before route placement started if you change your mind.

This probably isn't necessary when few objects are being pushed and there's space but definitely will be on complex multi-layer boards with lots of tight, parallel tracking.

Can't Push Objects / No Entry Sign

This basically means that the push has hit an obstacle. Most often it's obvious why (sometimes by zooming out if the problem is outside the current viewing area). However, there are a couple of possible reasons why you can't push an object that you think you should be able to.

  • If it's a via it's quite likely to be blocked on another layer.
  • If it's a track it might well be length matched or a diff pair. These are treated as immovable. If it's on net <None> it also can't be moved (so that you can connect to it if necessary).

Visual DRC will give you an indication of what might be immovable since objects that can be pushed are not enlarged by their clearances. Note that this means the object might be able to be pushed - it still won't be pushable if it's blocked on the board.


Block Editing Commands

BLOCK EDITING

Overview

Four block operations are provided: Copy, Move, Rotate and Delete and each operates on the currently tagged objects and the traces & vias within the tag box. If there is no tag box, then a default one is assumed comprising the total area occupied by the currently tagged objects. If there are no tagged objects, nothing at all will happen.

Block Copy

After creating a tag box as described in Tagging a Group of Objects, right clicking inside the tagbox and selecting the Block Copy command will cause a second box to appear over the tag box which you can then re position using the mouse. Clicking left will cause a copy to be made of the objects within the tag box whilst clicking right will abort the operation. Notably, the point at which you right click inside the tagbox defines the pickup point for the copy providing you with full control over the operation.

Control over what is tagged is handled via the selection filter. In particular, you can determine whether partial traces or only traces for which both ends of the trace are included in the tagbox are copied.

Beware that copying components will generally leave the netlist management out of kilter as there will be multiple placements of the same component references. If, having routed a module that is to be repeated several times, your intention is to copy it out to save re-routing, you should turn off live netlisting, clear the netlist, perform the copy, sort the annotation to match and then sync up the layout. Note however that this is not a recommended process - It is much better and far safer to use Project clips which were designed for this purpose.

Introduction to Project Clips movie.

Block Move

After creating a tag box as described in Tagging a Group of Objects, left depressing the mouse inside the tagbox and dragging will pick up the block and move it. Again, the pickup point is the point inside the tagbox at which you depress the left mouse button. The mouse cursor will change to be the movement cursor to provide a visual indication when you can perform this operation.

Trace segments with one end only inside the tag box will be rubber banded.

Alternatively, you can right click inside the selected box and use the 'Move-To' command on the resulting context menu to programmatically position the block.

If you have one or more locked components/pads inside the tagbox you will be presented with a dialogue form allowing you to either select everything apart from the locked objects or to leave only the locked objects selected. The former will then allow you to move everything apart from locked objects while the latter will identify locked objects which you can then edit to unlock.

Block Rotate

After creating a tag box as described in Tagging a Group of Objects, right clicking inside the tagbox and selecting the Block Rotate command presents you with the Rotation dialogue form allowing you to specify an any-angle rotation on the selected block.

Control over what is tagged is handled via the selection filter. In particular, you can determine whether partial traces or only traces for which both ends of the trace are included in the tagbox are copied.

  • Trace segments with one end only inside the tag box will be rubber banded although this generally leaves something of a mess it's best to rotate only completely enclosed sections of a layout.
  • Rotation of whole groups of components to non-orthogonal angles (even 45 degrees) creates large numbers of off grid pads. Routing such boards can be very tricky, even with features such as real time snap and trace angle fixup.
  • You can specify a rotation relative to various origin points. Typically, the center point is what you want but setting a false origin and then using that can also be useful (e.g. aligning pads in a circle).

The autorouter will also perform poorly under such circumstances.

Block Delete

After creating a tag box as described in Tagging a Group of Objects, clicking on the delete button on the keyboard (or the Block Delete icon on the resulting context menu) will delete all tagged objects. Use the selection filter to control the object types and layers affected by the delete operation.

Remember that you can control which objects are selected in the tagbox by adjusting the selection filter, either before or after the tagbox has been created.

Align and Distribute

The align and distribute commands are designed to automate the neat spacing of like objects. They both work on the right click context menu from a block selection and also work with a discrete selection created by holding the CTRL key and left clicking consecutively on the parts.

Roughly place parts and then use Align and Distribute to neatly handle the spacing.

Both dialogue forms are similar and allow you to align/distribute to any edge or to center either vertically or horizontally. In typical usage you would align the parts and then distribute them.

Align and then Distribute the components inside the selection.

The Align and Distribute keyboard shortcuts are very handy to learn and make this type of operation quick and easy. The commands can also be found on the Edit Menu in the layout module.


FILING COMMANDS

Overview

ARES makes use of the following file types:

  • Project Files (.PDSPRJ)
  • Project Clips (.PDSCLIP)
  • Panels (.PDSPNL)
  • Workspace Files (.WORKSPACE)
  • Region Files (.RGN) - legacy support only, replaced by project clips.
  • Library Files (.LIB)
  • Style File (STY

All data from the pcb is collated and stored as part of the Proteus project file with extension 'PDSPRJ'. This is a compound file containing the schematic data, the layout data, the project database and potentially other simulation related files. Backup copies made when saving over an existing file are prefixed with 'Backup of...'.

Information about which modules are open in Proteus (e.g. Schematic, Bill of Materials and Layout) together with their positions on your monitor(s) and which frames they are in are stored in the project workspace file. This allows you to return to the same project state when you reload a project.

A region of a layout can be exported to a section file and subsequently read into another board. Region files have the extension 'RGN'. and are read and written by the Import and Export commands on the File menu.

Symbol and package libraries have the extension 'LIB', while the trace and pad style file has extension STY.

Starting a New Project

To start a new design you need to create a new Proteus project. You do this by invoking the New Project Wizard either from the home page or from the file menu. This wizard guides you through the setup of your next Proteus project. There is a start page in which you specify the project name and destination directory and then potentially three main screens for schematic, PCB and firmware.

Schematic

When creating a schematic check the box at the top of the screen and then select the template on which you want to base the schematic. Those provided by Labcenter basically contain different sizes of work area, although you can customize and save your own templates from within the schematic capture module.

PCB Layout

If you are creating a PCB check the box at the top of the screen and select from the available templates. PCB templates contain pre-defined board edges, mounting holes and a full set of technology data (design rules, layers in use, default units, etc.) As with schematic, you can customize and save your own templates from within the PCB layout module.

This screen will only be presented to you if you have a license for one of the Proteus PCB design products.

Firmware

If you are creating an embedded design and want to simulate your firmware, check the create firmware box at the top of the screen and then select your controller and compiler using the combo boxes. If selected, the quick start files checkbox will generate a skeleton firmware project for you and configure project settings for compilation.

Creating a firmware project requires a schematic in order to simulate so you cannot proceed from this screen if you opted not to create a schematic earlier in the wizard.

The combo boxes on this screen are license aware so you cannot create a firmware project for a controller than you cannot simulate in Proteus.

There is also a summary page at the end allowing you to review your setup before the wizard exits and generates the project files.

Loading an Existing Project

Loading an existing project can be done in four ways:

  • From the command prompt as in: PDS.EXE <my_project>
  • By clicking on the Open Project button on the Proteus home page.
  • By using the Open Project command on the File Menu inside Proteus.
  • By double clicking the PDSPRJ file in Windows Explorer.

Importing a Legacy Project

Older versions of Proteus typically contained several files such as a DSN file for schematic and a LYT file for layout. The Import Wizard on the home page and File Menu is used to bring these projects into Proteus 8.

To import a legacy project

Launch the import wizard.

Browse for the old schematic (.dsn file)

If a PCB file (.lyt file) is associated with the schematic it will automatically appear in the Layout field. If there is no layout file associated with the schematic then leave this field blank.

If an old VSMStudio file (.vsmp) with the same name as the schematic exists in the same directory it will automatically appear in the VSM Studio edit box. If the wrong VSMP file appears or there is no corresponding VSMP file then either browse for the file or leave blank.

The project name and path are taken from the filestem and location of the schematic being imported. You can change this if required from the fields at the bottom of the dialogue box.

If you change the path for a VSM project then you will need to manually change the PROGRAM property of the microcontroller, otherwise your simulation will fail.

When you are finished use the import button to create an import a Proteus 8 project.

Saving the Project

You can save your Project when quitting via the Exit command, or at any other time, using the Save Project command. In both cases it is saved to the same file from which it was loaded. The old version will be prefixed with the text ‘Backup of’.

The Save As command allows you to save the Project to a different file.

Import Region

The Export Region command is deprecated in Proteus 8 and has been replaced by Project Clips.

Legacy region files can be imported via the Import Project Clip command and then adjusting the file type selector to V7 Region Files. After import you should then immediately created a project clip from the imported circuitry.

Import / Export Project Clip

Project clips (.PDSCLIP) can be imported and placed on the schematic/layout. If you are importing a clip which contains both a schematic and a layout portion you must import and place inside the schematic module (ISIS).

Project clips can be exported by first dragging a selection box around the area in the schematic and/or layout that you want to export and the invoking the Export Project Clip on the right click context menu or on the File Menu.

Export is only available for valid selections - please refer to the rules for project clips.

See Also:

Project Clips

Backups and Last Loaded Files

Proteus includes a comprehensive backup and recovery system to help protect your work in the event of a crash or application hang. In particular, the auto-save and recovery mechanism provides a last stop guarantee should the worst happen and the program crashes. This is discussed in detail in the topic linked below:

See Also:

Backup and Recovery

While Proteus includes significant protection and recovery from application faults we strongly recommend that you organise and maintain your own backup procedures to complement those provided by the software.


Keyboard Configuration

KEYBOARD SHORTCUTS

Configuration

ARES provides an interface for you to map the keyboard to a command set. This allows you to ‘bring out’ the functionality you commonly use according to personal preference. Context Sensitive Help is available for all fields within the configuration dialogue box.

Notes :

  • Accelerators can use any combination of CTRL, SHIFT and ALT keys. For example, CTRL+X, CTRL+ALT+T,SHIFT+CTRL+1, etc.
  • A Reset option is provided to reload all Proteus standard shortcuts. This will overwrite any configuration you currently had.
  • Some European keyboards have an ALT GR key (normally found directly to the right of the space bar). Where present this translates to be CTRL+SHIFT for the purposes of assigning keyboard shortcuts.
  • If you assign an ALT accelerator that is used as a menu accelerator then you will no longer be able to accelerate the menu from the shortcut. For example, ALT+T by default expands the Tools Menu within ARES. If you assign ALT+T to the Tidy command then you would have to have to access the Tools Menu using the mouse.
  • Some commands are locked and their keyboard shortcuts cannot be assigned or re-assigned to another command. The assignation box on the dialogue box is grayed out for these commands.
  • When the NUM LOCK is on the keys 0-9 on the numeric keypad are distinct from the 0-9 keys on the main keyboard. For example, you could assign CTRL+0 up to CTRL+9 on the main keyboard as shortcuts to the Most Recently Used file list (MRU list) and on the numeric keypad you can assign CTRL+NUM-0 up to CTRL+NUM-9 for different commands.
  • When the NUM LOCK is off keys 0-9 on the numeric keypad action their secondary functions and these functions are considered identical to those on the main keypad. The key for the number 5 on the numeric keypad has no secondary function when NUM LOCK is off.
  • You can save your custom keyboard configuration via the ‘Export Keyboard Map’ command on the Options tab. This allows you, for example, to port your keyboard configuration to another computer. Similarly, the ‘Import Keyboard Map’ command allows you to reload a custom keyboard configuration that has previously been saved.


MANUAL ROUTING EXAMPLES

Introduction

The examples below cover a range of common routing tasks in Proteus. In all cases it is assumed that the board has been set up with the basics. This means:

  • The basic design rules from the Design Rule Manager and that you have a basic understanding of Net Classes.
  • A layer stackup and drill spans have been thought about and defined.
  • Layer pairs have been configured as required.

Example: Routing a Simple Connection

Simple Route required from U9:4 to C62:2

This is a simple example where we can place the route on one layer. The process is:

1) Select Trace Mode icon.

2) Left click on the centre of a pad to start routing.

3) Guide the route towards the destination pad.

4) Press the ENTER key when you're happy with the preview route to accept the automatically created route and complete.

Important Concepts

While trivial in terms of routing, the software is doing a fair bit of work based on information that you (should) have supplied. Understanding how this works will make a big difference when things become more densely packed and complex.

  • At the beginning and the end of track placement, Proteus will snap the mouse to the centre of the pad to ensure a solid connection. The amount of snap is based on your settings from the View Menu (but normally toggled by keyboard shortcuts). Typically, you work with a looser snap when zoomed out (e.g. F3 or F4 on the keyboard) and a finer snap when zoomed in tight (e.g. F2). If you are missing the pad center, change the snap setting to a looser one.

Make sure you understand snap settings and the keyboard shortcuts (from smallest to biggest it's CTRL+F1 -> F2 -> F3 -> F4). You can change the values from Technology Menu - Set Grid Snaps command. The goal is to always work with the biggest snap setting you can ... if you find yourself missing the center of the pad then chances are good that your snap setting is too fine.

  • When you move the mouse to place a track the style (thickness) of the track comes from the Net Class tab of the Design Rule Manager on the Technology menu. Since it is very easy to create your own net classes, this provides the means to automatically route with different but correct trace widths for various power and signal connections.

    You can override this behaviour by turning off Auto-Trace Selection from the Tools Menu or by changing the trace style from the Route Command Centre. However, for all but the most simple of boards it is extremely useful and as we'll see in more complex examples, a little time spent setting up net classes will vastly simplify routing the board.
  • When you route close to the via or near another pad/track the software will either push it out of the way or stay the required distance away depending on which mode you are in. We'll look at these options below but they are controlled either by keyboard accelerators (SHIFT+P to toggle push mode) or from the Route Command Centre. These distances are set up in the Design Rule Manager on the Technology menu.

The single most important thing you can do to make manual routing easy is to set up both your Design Rules (clearances) and your Net Classes before you begin. The more complicated the board, the more important this becomes but even on simple boards it's a vital QA tool as well as a productivity win.

Example: Guiding a Route with Anchors

This is the single most important skill to master, whether completing a single route or weaving a complex push route through a densely packed BGA.

Simple Route required from U9:4 to C62:2

This is the same route as before except instead of using the auto-complete we are going to place anchors to guide the route exactly where we want it to go. The basic technique is to left click to commit the route up to the point of the mouse. You have two degrees of freedom (two track segments) to allow a more natural flow with route guidance. You'll find that normally therefore you left click to commit some track before you change direction. Here is a full sequence for this route:

1) Select Trace Mode icon.

2) Left click on the centre of a pad to start routing.

3) Come straight out and then up from the pad (remember two degrees of freedom). Left click to commit.

4) Head along the horizontal until nearly at the destination and then head up for a little 45 corner. Left click to commit.

5) Move mouse into destination pad and left click to complete the connection.

Important Concepts

This was probably harder to explain than to actually do but the technique is very important later on when it comes to pushing other objects out of the way and it will probably also lead to the neatest tracks once you become proficient in it's use. Here are a few things to remember.

1) You can unwind the track so far and go backwards if you need to! Simply move the mouse back over the route segments you've completed to erase them and then try again.

2) A left click will commit the two segments between the mouse and the previously committed route (or starting pad/via). Don't try to commit each segment because you'll end up with lots of nearly colinear, tiny second segments. Work with the two segments, move the mouse around until you're happy and then commit them both.

3) Keep an eye on the auto-complete shadow track. Often you can guide it part way there by left clicking and placing anchors and then the result is good enough to just hit ENTER and complete. This will save time.

4) Remember, if you're not happy you can segment drag the track afterwards to correct. Or you can just use CTRL+Z to undo and try again.

Example: Pushing another Track or Via while Routing

Now lets look at how we can move other tracks to better route the one under the mouse. Here's a really simple example

There's still quite a bit of space here but it will be helpful starting point in explaining how push mode works. Let's assume we wanted to move the existing route a little to better connect the remaining track.

1) Start by selecting route placement icon and clicking on the pad to begin routing. The status bar will tell you whether you are in push mode or not.

Switch to push mode (SHIFT+P shortcut) if you are not already in it. You can also see (and change) the mode from the Route Command Centre (keyboard 'R').

2) Move the mouse down from pin 1 and then diagonally along, pushing the existing track out of the way as you go. Go slowly and if you don't like what you see move the mouse backwards and push against a different part of the track. When you've pushed the route sufficiently left click to place an anchor and commit.

Commit the push with an anchor

This is a really important technique. If you need to push something then go slowly and anchor when you're happy with the push. The push vectors change as you move the mouse so the pushed route(s) will change as well. You can always move the mouse backwards to rewind but it's best to take your time and anchor as you go.

3) Now simply move the mouse along and down to complete the route.

Complete Route after Push

After placing the anchor you could turn push mode off (SHIFT+P) and then simply hug the other track in to make the connection. Selectively turning push mode on and off is very powerful - just remember to place an anchor before you toggle the routing mode!

Let's look at another example where we want to move an existing route along with a via.

Start of route where we want to connect to GND trace at the right but are blocked.

The shroud around the mouse is called Visual DRC and provides a visual indicator of how close you can get to immovable obstacles. The track to the right of the mouse does not have a clearance because we are in push mode and it is therefore movable.

The procedure is exactly the same. When we start routing, notice that the track and via do not have clearances shown in the Visual DRC circle (see above). Since Visual DRC by defaults shows us clearances around immovable obstacles this means two things:

  • We are in Push mode. In FMR mode we can't move anything so everything has clearances shown.
  • We can push both the track and via. Sometimes via pushing is turned off (from Route Command Centre) and in that case the via would show it's clearance.

Now we can move the mouse along the bottom of the route to push both the track and the via above the route being placed and free up the route.

Then we can route to our connecting track and commit.

The most important thing to remember about pushing vias is that it affects more than one layer. This means both that it might not be possible because it's blocked and you can't see where but also that you might need to tidy up routes that have been pushed on other layers of the board.

See Also:

Route Command Centre

Push Mode vs FMR Mode.

Example: Routing Across Two Layers

Simple Route needed to connect U6:4 to U6:8

In this example we need to route out from U6:4, drop a via, route under the blocking ground track and then via back through to make the connection. This procedure works in both push mode and FMR mode so it doesn't matter which we're using.

1) Select track mode.

2) Left click on the pad and move the mouse to start routing.

3) Double click the left mouse button to place a via and continue routing on bottom copper.

4) Route under the ground track and double click again to come back to top copper.

5) Route to the track, left click on the track and then right click to finish routing.

Connection with vias.

Important Concepts

In addition to the technologies used in the first example above, the software does a couple of other things for you in this case. Notably:

  • When you double click to place the via, the via style (drill hole, diameter, soldermask, etc.) comes from the Net Classes tab of the Design Rule Manager.
  • When you drop the via you switch to routing on a different layer. While a simple decision for a two-layer board, the layer toggle for via's is defined from the Layer Pairs command on the Technology Menu.
  • The layer range of the via will be the smallest possible drill range (as defined in the layer stackup) that gets you from the current layer to the associated layer pair. If you have only one drill range then the vias will always be thru-hole but if you set up blind or buried layer ranges and then set up routing layer pairs Proteus will use the best via range automatically.
  • When you terminate a connection on a track you must first left click on the centre of a track to complete the route and then right click to exit route placement. This is different from terminating on a pad where a single left click will both complete the track and terminate route placement.
  • After completing the track the (GND) plane on bottom copper is punched out to make space for the track. The clearance from the power plane to the via edge is the applicable pad -> trace design rule.

Example: Routing to a Plane Layer

In this example, we want to route from the bypass capacitor down to one our previously specified plane layers. Our procedure is therefore:

1) Select track mode, start routing on the capacitor pin and move a little into free space

2) Double click to drop the via and complete the connection.

Important Concepts

This is an excellent example of where preparation saves a lot of effort during routing. If you have defined a layer stack, specified the plane layers and created your power plane on the plane layer then Proteus is armed with all of the right information. It knows you are routing on the VCC net and it knows there is a VCC plane layer underneath you so when you double click to place a via it understands that you are connecting to the plane layer and can complete the connection for you.

Example: Routing Across Multiple Layers

Tracking on multiple signal layers.

Here we have something quite a bit more complex. The main problem is that you don't know which layer to use to escape from the BGA until you are actually placing the route. Once out from the BGA things are still quite crowded and you need control over where on the board your via destination layer is going to be. Use the following process to help with this kind of work .

1) Make sure that you have fully set up your layer stack. In particular, check your drill spans to ensure that you have enough via coverage to escape from the BGA on different layers.

You can launch the Layer Stackup dialogue at any time from the Technology Menu.

2) Setup Layer Pairs. Make default rules for where you are most likely to go when placing a via on a particular layer.

3) Use Push Mode. It's going to be much easier to navigate a dense area of board if adjacent tracks and vias can be nudged a little.

4) Keep or switch Visual DRC on. This will show you where you cannot go due to clearances and also which objects can be moved if need be (those without Visual DRC clearances).

3) Use Floating Vias. When you place a route press the SPACE bar to float a via on the end of the track. Use PGUP and PGDOWN to select destination layers in the layer selector and then left click to drop the via. This takes a little getting used to but has the added benefit of letting you precisely position the floating via before dropping it (it will obey design rules while floating).

Practise with floating vias until you've mastered the technique. You will end up positioning via's in better places and routing multi-layer tracks far more smoothly.

Example: Dense Routing and Necking

Track necking is needed to escape the BGA.

Here is a classic example of a case where two track widths are needed. The track style is the desired width for the route and neck style is the minimum acceptable width (preferably over small distance). For this kind of routing you need to:

1) Set up design rules carefully. In particular, a tight trace->pad clearance is vital to allow tracks to snake through breakout vias.

2) Set up net classes carefully. The track, via and neck style for each net class needs to be specified. It may be necessary to create additional track styles or via styles as well.

3) Set layer usage and layer pairs as in the example above. No question this is going to be multi-layer !

4) When routing from the ball use the SPACE bar to float the via and use PGUP, PGDOWN to select the destination layer in the layer selector. Left click to drop the via.

5) Use SHIFT+N to toggle neck style on and off (or launch the Route Command Centre and do manually). In the example above, I switch to neck style at the via (SHIFT button down) and then back to track style on exit from the BGA (SHIFT button released).

The SHIFT key puts you in control over track widths during routing. When space is at a premium or obstacles are preventing you getting through, depress the SHIFT key and try in neck style. It's invaluable with this type of dense routing.

Example: Curved Routing

Placing a route with curved corners can be helpful with signal integrity and net tuning or simply for aesthetic reasons. In Proteus, you can only placed curved corners in FMR route (although you can convert them after placement in push mode) and you toggle curved route placement on and off using the SHIFT+C shortcut key (or the Route Command Centre) The process of placing the route is therefore:

1) Left Click the mouse to start the route.

2) Switch to FMR mode if not already there (SHIFT+P).

Status Bar shows the current routing mode - change with SHIFT+P

3) Use SHIFT+C to turn on curved corners or launch the Route Command Centre and configure that way.

4) Route as normal and left click the mouse on the destination pad to terminate the route.

If you need or prefer to route in push mode then you can:

1) Route in push mode with mitred corners.

2) Right click on the completed route and select mitring from the context menu.

3) Change from mitred to curved corners. Space permitting the entire route will change corner style.

Example: Length Matching Routes

Matching the length of routes on the PCB can be essential for signal timing and signal integrity with longer routes and higher speed signals. The process itself in Proteus is extremely simple, namely :

1) Configure the length match settings in the dialogue form (Technology Menu)

2) Route the tracks normally.

3) Hold the CTRL button down and successfully left click on the completed tracks to highlight them.

4) Right click on any one of the now selected tracks and choose the length match command from the resulting context menu. Success will be reported on the status bar.

Important Concepts

While the act of matching the lengths is fairly straightforward, choosing the correct topology for length matching can be extremely complex. Issues such as crosstalk coupling, signal distortion and advanced timing all need to be considered with respect the signal rise time. In addition, the PCB land may prove to be an issue (e.g. some patterns will block via sites more than others) and some topologies for matching may not actually be feasible given existing design rules and the presence of other obstacles (pads, tracks,etc.) already on the board.

We strongly recommend that you also read the dialogue level help. There is more detail on each option and the trade-off between them.

Length matching currently works from pin to pin. If you choose to, you can length match across layers and the length of the via(s) will be taken from the layer stack setup. Bear in mind however that using vias is not recommended from a signal integrity viewpoint.

Length matching where a tertiary junction is involved is ambiguous.

Once a matchgroup is formed by matching routes to each other then the software will attempt to maintain it. So, if you edit one of the tracks and change it's length then the others will attempt to match up again within tolerance. This is intended to be a manual operation only though (e.g. to make space) and so length matched tracks cannot be pushed by other tracks.

See Also:

High Speed Routing Examples.

Differential Pair Routing Examples

Example: Via under SMT

Routing towards connection on the other side of the board.

Here we are routing on bottom copper to terminate on a surface mount pad on top copper. We could via up and then track across in the normal way but we can also via straight up from under the pad to form the connection. So:

1) Route underneath the destination pad.

2) Use SPACE to float a via.

3) You are looking for the pad to brighten to indicate that you are in the contact point (hardware accelerated mode). It's often useful to change snap level up (F3 or F4) as this will snap you onto the center of the pad.

4) Left click to commit placement and complete the route. You'll know when it's connected because the ratsnest line will disappear.

Completing the route by via-under-smt.

You may then want to specify the via(s) as resin filled for manufacture.


Length Matching

LENGTH MATCHING ROUTES

Introduction

Length matching or net tuning is often used with higher speed or longer distance signal runs on the PCB to improve signal timing or signal integrity. The basic idea is that the shorter trace follows a detour or meander in order to lengthen it to match the length of the longer trace.

Matchgroups

After traces have been matched in length they belong to a matchgroup. A matchgroup is simply a container for a set of routes that have been successfully length matched. It includes the target length, the tolerance, the serpentine configuration and a list of the routes that belong to it. You can have as many matchgroups as you need in a design, each with different serpentine configurations and tolerances; Proteus will take care of managing and storing the configuration for each matchgroup.

Matchgroups are internal data structures with no direct user interface but you can browse and select them via context menu commands.

Length Matching tracks to each other

Normal Track Matching

Here we are looking at matching the lengths of tracks that are not part of a differential pair.

First, access the length tuning dialogue form via the Technology menu. Configuration of various options depends on signal speed and designer priorities but at a minimum make sure that the length tolerance is suitable.

You'll find a lot more information on the various configuration options by clicking on the question mark (?) to access the dialogue level help.

We do not recommend switching to uniform height unless you have no choice. This severely constrains the algorithm and is likely to result in failure to complete where space on the PCB is limited.

2) Hold the CTRL button down and successively left click on the two routes such that both are highlighted. Right click on one of the tracks and select the match length option from the resulting combo box.

3) A successful match will be indicated, together with the actual delta between the traces on the status bar.

Length matching in Proteus takes place from designated connection point to designated connection point (in other words center pad to center pad). Since the route of the signal from the connection point on the PCB to the component is unknown the earliest available point at which to start length matching is the center of the pad.

You can add tracks to a group of already length matched tracks by including one of the already matched tracks in the length match operation. Similarly, you can remove individual tracks from a matchgroup via the right click context menu.

Once a matchgroup has been formed Proteus will attempt to maintain it after edits. So, if you edit one track it will automatically re-match (space permitting) the other tracks to keep all the lengths within tolerance. Length matched tracks will not be disturbed by normal push mode routing (cannot be pushed) so this refers to deliberate manual editing of a track in a matchgroup.

See Also:

High Speed Routing Examples.

Differential Pair Length Matching

It's important to understand that we're not matching the length of one track in the differential pair to the length of the other track in the differential pair. This is done automatically by differential pair phase matching. What we are doing here is matching the length of one differential pair to the length of another differential pair.

Start in the same way as before by configuring the length match options via the technology menu. This time we want to switch to the differential pair tab of the dialogue.

This dialogue allows you to control the topology of the differential pair length matching. Since tolerances are typically part of the protocol specification you'll set them separately in the differential pair tab of the design rule manager dialogue. As an example here we might typically set the serpentine sizes to be multiples of the separation between the two diff pair tracks and opt for mitred cap styles.

Now we follow the same process as for normal length matching. Hold the CTRL button down and successively left click on one route in diff pair number 1 and then a route on diff pair number 2 such that both are highlighted. Then right click on one of the tracks and select the match length option from the resulting combo box.

The shorter differential pair will then serpentine according to the specified topology in order to match length with the longer pair.

Matched Diff Pairs

Note: Length matching serpentines will add corners which can change the lengths of the two tracks in the differential pair with respect to each other at a given point on the route. A phase matching pass is done after the length matching is completed but in turn it's possible that this adds length to the pair. It's important therefore to know what the phase matching tolerance (sometimes called skew) and the length matching tolerance are for your signal speeds and to set the parameters correctly in the design rule manager. More information can be found in the section on phase matching. The phase matching visualizer is also a really useful tool in showing you the phase status across the entire route.

Length Matching tracks to a specific value

Instead of matching the length of the tracks with respect the longest track in the selection you can choose to match the length of the tracks to an absolute value by inputting the target length.

The original length of the longest selected track is shown above the edit box. The target length you enter must be longer than this otherwise the operation will fail.

You can do exactly the same with a differential pair by right clicking on either track on the differential pair (no need to highlight them both) and entering the target length as shown above.

Removing Length Matches

To remove a serpentine from a track simply select and use the remove length match command on the context menu.

This will work for several tracks as well - simply hold CTRL down, left click the tracks you want and then invoke the remove length match command from the context menu.

If you remove the longest track from the matchgroup (the target track) then the track will be removed from the group and the rest of the matchgroup will regenerate with the next longest track as the target length for the group.

Moving Serpentines on the Route

To move the serpentine to a different section of the route simply left click to select and then drag with the left mouse button.

Moving a Serpentine section to a different place on the route

Notes:

  • When matching a lot of routes in a tight space it is often best to match a few routes and then move the serpentines manually to create the most space for matching the remaining routes.
  • You cannot move a serpentine onto a segment of route that is part of another matchgroup. This often happens with daisy chain topologies where one segment of track is part of multiple matchgroups.

Pin-Pin Matching

Length matching in Proteus currently works on a pin-pin basis. If via's are used then the length of the via is determined from the layer stack information. You cannot length match through a tertiary junction because the meaning in ambiguous (which route is being matched).

Complex Length Matching

It is sometimes unavoidable that one section of track belongs to more than one matchgroup. A good example of this is the fly-by routing of the CMD/ADDR lines with DDR3. As an example, consider the following topology.

Simplified fly-by configuration example.

AB, AC and AD are all critical signals and will need to be matched to specific lengths. It is inevitable however that some track segments will be included in multiple matchgroups.

This section of track is an example of one which will be included in several matchgroups

There are two important points to remember when length matching something like this:

Selection

The user needs to help the software by limiting the selection to an individual, pin-to-pin, route. In a complex configuration, this means holding the CTRL button down and left clicking on track segments to tag only the full route that you want to match. The route must start at a component pad and must finish at a component pad.

In our simple example, you would first select the track from A to B through the via.

Select the full pin-pin route from A to B

In Proteus, this is done by left clicking on one segment of track (Eg. pin to via) and then holding down the CTRL key and left clicking again to highlight the second segment of track (e.g. via to pin.)

Use the CTRL key to select stub lengths of track and ensure that you have the full correct route tagged.

Once the route is selected, we can right click and input the target length for the route.

Distance travelled through the via is taken from the values specified for layer thicknesses in the layer stackup (Technology menu).

Next, we would select the track from A to C through the via.

Select the full pin-pin route from A to C (note the stub to B is not tagged)

Again, in Proteus we select the first track and then hold the CTRL button down and left click to select the second track to tag the entire pin to pin route.

Make sure that you tag only the desired signal route before length matching.

We input the target length for this route and then continue with exactly the same process for route AD.

Ordering

The example we have used is one in which the order of length matching is important. The user should first match AB to its required length as shown below. Since AB has less space to serpentine it is more likely to require the common trace section for lengthening.

First, set the target length for AB.

Once a trace section belongs to a matchgroup it cannot have it's length changed when it is included in another matchgroup. The setting of target length for AC can therefore only change the length of the trace segments to the right of the first via.

Only the green sections are available for serpentines in order to achieve the target length for AC.

Our final action is then to set the target length and length match route AD.

Summary
  • Make sure to select a complete and un-ambiguous route from source pad to destination pad.
  • Where multiple length match operations will share some track segments, start with the route containing the shortest length of common track and work upwards to the longest one.

Adding Internal Lengths

With Proteus, you can easily add internal lengths to footprints on the layout. This enables more accurate matching for critical signals, particularly with BGA’s where the signal delay inside the chip can be relevant.

Internal lengths are created as a simple CSV file of the format

<pin name>, <internal length>,

where the internal length data is sourced from the manufacturers toolsuite. This is applied to the part in ARES via the context menu command.

Length matching will then include internal distances when matching. For each route both the live status and the dump file report will show etched length and total length separately (total length being etched length plus internal length).

If you are using software such as TimingQuest and you know of a format that can be exported and contains this information (pin name, internal length) then please let us know as we may be able to import it directly. (support@labcenter.com)

Viewing and Browsing Matchgroups

You can browse and tag all length matched nets and routes by selecting connectivity highlight mode and changing the filter to show length matched only.

This will filter the view to length matched tracks only and display in the matchgroup viewer

This view is grouped by matchgroup and the right hand side shows compliance with the target length. Hovering over an item provides tooltip information on the target length and the tolerance for the matchgroup. Where a set of tracks are matched to a target length the right hand side will compare the length to the target (e.g. len=T). Where tracks are just length matched to each other one of the tracks (the longest one) will be the target and so simply say T on the right hand side.

Members of a matchgroup that are non compliant will show in red whether they are greater than or less than the target length.

When you double click on an entry you'll tag the route in question. Alternatively, use the T button at the top to select the current route.

Selecting M at the top (in this mode) will tag the entire matchgroup that the currently selected route is part of. Similarly, when you right click on an entry and select length matched tracks then all matched tracks on the net will be tagged on the PCB

These are often but not always the same thing. It is quite possible to have a net on which some routes are length matched and others are not.

Pre-Production Check

The target length for a matchgroup is stored with the matchgroup and the pre-production check will test against this length prior to board manufacture to double check than no track nudging has taken place.

Length Match Reporting

To generate a length match report open the Project Notes module and select the length match template.

Alternatively, if Project Notes is already open you can select a new note from the File menu. The module needs to be unlocked to enable the new note command

The report lists etched length for all the matched tracks along with any internal lengths and tolerances. At the right hand side is a tick/cross indicating compliance with the current tolerances.

If you make changes on the layout (E.g. to correct a non-compliant route) you can reload the report from the right click context menu.

Like all Project Notes reports you can save out as PDF or simply store with the Proteus project. The report is timestamped to indicate the last time it was re-generated.

The same process can be followed with the dedicated differential pair report to produce detailed information on differential pair length matching.


DIFFERENTIAL PAIRS

Introduction

Differential pairs consist of two routes on the PCB designed to carry a differential signal. In this setup the receiving circuit responds to the electrical difference between the two signals, rather than the difference between a single wire and ground. Proteus supports differential pairs with both configuration and design rules and also with an assisted routing mode and a post-process phase matching pass.

Setup

In Proteus a differential pair is defined on the schematic and then configured on the layout before routing. Specifically, on the schematic we need to know the component pin names of the differential pair pins and we also need each differential pair to have a unique name or identifier. We then need to configure a net class for the differential pair, set some specific clearances and set up a couple of design rules before we begin routing.

This is discussed in a dedicated topic linked below.

See Also:

Differential Pair Setup

Routing

Once the setup is complete we can now route the differential pair. Proteus includes a dedicated routing mode for differential pairs which, depending on the routing problem, will be used for all or some of the routing task. The most important thing to remember is that you can route in either differential pair or standard mode. Regardless of how the two routes get completed Proteus can detect the completion of the differential pair when the connections between the pins are complete and will then perform any required phase matching.

Indeed, for all but the simplest of routing scenarios, the designer is going to have to help with the routing problem. For example, with a BGA normal routing mode would be used to fanout to stub vias on both sides. The assisted diff pair routing mode can then be used to route between the two sets of vias.

Organise the fanout at both sides in normal routing mode.

Next, switch to diff pair mode, select the routing layer and then click on a track or via on the fanout from the source device to pick up the dff pair. Route as normal to the destination/receiver and click on one of the fanout stubs at the other side to complete.

The Pre-production Check will test all differential pairs and warn you if they are not compliant with the configuration. You can also generate a detailed differential pair report at any time via the Project Notes module.

It would be very helpful for us to see real world situations where the assisted routing (both tracks at once) fails. If you come across this and are able to submit your board to support@labcenter.com it would be much appreciated and will help us improve the routing algorithm.

If you find yourself in a situation where you have set off routing and cannot finish at the end point - and get something like:

This will be because the DRC rules are preventing the tracks from connecting to the end pads. You will need to either set the track thickness to be smaller in the Net Classes tab of the DRC form, or change the Pad-Trace DRC rule for your Diff pair net Class.

A good indication that this is the case is that the ghost tracks and arrow do not appear:

it should look like:

See Also:

Example: Routing a simple differential pair on one layer.

Example: Routing a differential pair with vias / fanout.

Example: Routing a differential pair through a passive component.

Example: Routing a differential pair with taps / branches to passives.

Example: Routing a differential pair in manual routing mode

Phase Matching

Phase Matching (sometimes called skew correction) is needed where the lengths of the two tracks differs beyond the specified tolerance. This means that the equal and opposite differential signal is likely to be no longer opposite and so corrective action is needed. Almost all of the time, the track lengths drift due to cornering and the corrective action is a short serpentine on the shorter track after the corner is complete.

Regardless of how you route the diff pair you can phase match it when it is complete. If you use the assisted routing mode the phase matching will happen automatically when you complete the route. If you complete manually then you can phase match from the right click context menu. Regardless of how it happens it's important to understand that phase matching depends on signal direction.

The direction of travel during routing determines where serpentine segments are used to equalise the trace lengths.

It is assumed that you are routing from source to destination and the phase matching takes place accordingly. If this is not true and you have routed from destination to source you can reverse the route via the right click context menu. This will automatically re-calculate the phase matching to be correct for the new direction of travel.

Reverse the direction of the differential pair.

The direction currently in force is normally fairly obvious by looking at which end of the corner the corrective serpentine segments occur but it is also indicated in the differential pair report.

The differential Pair report includes indication of which component is deemed the source.

Visualising Phase

Probably the easiest way to analyse the phase situation on the differential pair is to use the display phase offset command on the context menu for the differential pair.

Green outlined segments are in phase (signals 180 degrees offset), yellow segments are out of phase but inside tolerance (acceptably skewed) and red segments are skewed beyond the phase tolerance. You'll notice corrective serpentines take place on the straight segment immediately following red segments to minimise out of phase distance. Click anywhere in free space to remove the visualisation.

You can use this visualisation together with the reporting to refine or tune the diff pair. You may need to adjust parameters or re-route using a slightly different topology.

Length Match the Pair

You can set a target length for differential pairs in much the same way as normal tracks, namely via the 'Input Target Length' command on the right click context menu.

Diff Pair Length Matching will lengthen both tracks to the target length with serpentine segments as shown above.

Similarly, you can match the length of two differential pairs by selecting one track on each pair and then using the length match command from the context menu.

You can click on either one of the tracks on a length matched serpentine and then drag the serpentines along the route to a position of your choice. This works exactly the same as for 'single track' length matched serpentines.

See Also

Example: Length Matching a Differential Pair

Length Matching vs Phase Matching

After length matching the differential pair the automatic phase matching will be applied. Since this can of itself add length your differential pair may end up outside length match tolerance. You can check all of the tolerances via the diff pair report at any time. If this happens and you want to make changes there are a couple of things you can do.

1) Review the routing topology. Phase matching is required normally when the differential pair routing corners. Removing unnecessary cornering will reduce the amount of phase matching required.

2) Review the tolerances. It might be that you can relax the phase match tolerances such that phase matching is not required after length matching. This in turn will help keep the length matching inside tolerance.

Adjust the tolerances from the differential pair tab of the Design Rule Manager (Technology Menu).

3) Review the length matching settings. Phase matching serpentines will not be placed inside a length match serpentine. It is therefore often better to have smaller length match serpentines (more of an 's' shape than a 'u' shape) so that you don't have a long straight segment of track that is out of phase. All of the length matching options are available on Technology Menu.

Changing the Length Tuning settings can have a big impact on the routing and also the amount of track that is out of phase.

If you want to start the length matching again after making configuration changes you should first select the remove length matching command from the context menu on either of the tracks. After the existing length matching is removed you can length match again with the new tolerances.

Remove existing length matching from the diff pair before trying again with new tolerances.

You can use the phase visualisation command on the context menu at any time to see over what distance the diff pair is out of phase.

In the end, much will depend on the application. Since phase matching occurs automatically after both route completion and a length matching operation it has priority over the target length being set. The steps above outline what you can do to change this behaviour (e.g. make phase tolerance big) should you find for example that absolute length is more important in your application.

Differential Pair Reporting

Creating/Opening the Report

The differential pair report provides valuable data on the routed pair along with a compliance check against specified parameters. To launch the report you first open the Project Notes tab and then select the report from the list of templates.

Creating a new Diff Pair Report in Project Notes.

Alternatively, if you have another report already loaded in Project Notes you simply add the differential pair report via the file menu command.

Create a new report from File Menu in Project Notes.

Finally, you can also insert the differential pair table to a custom report via the Project Data button at the top of the Project Notes module.

Add the Differential Pair data object to an existing report.

The report itself comes from a basic Labcenter template and so we've included quite a bit of explanatory text and prompts for user input. You should edit/modify to your corporate standards and then save as template (Template menu) so that future reports are based on your own templates.

Report Data

The data table contains information about each differential pair along with a compliance status column on appropriate fields.

Example Differential Pair Report Table in Project Notes.

Note that the rows containing the route lengths also indicate the direction of the route (source pin -> receiver pin). This is normally taken from the way in which the tracks were routed but is easily changed from the reverse route direction command on the track context menu. This is always worth checking as the direction is important for all phase matching calculations.

Also note that both the etched distance (tracking only) and the total distance are displayed in different columns. There are three factors which can contribute to the length of a diff pair:

  1. The tracked / etched length.
  2. Any specified internal length of the pins.
  3. The distance between the pins of any pass through components on the PCB.

The system will calculate 1 and 3 automatically and you can add internal pin lengths yourself via the right click context menu on the components.

See Also:

Routing with Pass Through Components.

Reverse the Route direction to ensure source to receiver in the report.

Each report is time-stamped and does not update as changes are made to the layout. You can update a particular data table from the right click context menu on the table. In the case of a custom report where you have multiple data objects (e.g. Diff Pair Data, Length Match Data, Stackup Data) you can update the entire report from the Reload Project Report command on the Edit Menu.

Phase Tolerance

This is the allowable difference in track length due to length mismatch (e.g. a corner) before we are considered out of phase. Serpentine routing is applied at the end of a corner to equalise the track lengths when we are deemed to have drifted out of phase.

It's important to note that serpentine routing for phase matching can only be applied at the end of a corner. This means that long corner (E.g. a large curve) can create a significant distance before serpentine routing can is applied.

Despite a difference in length as we corner the two tracks are not out of phase until they exceed the phase tolerance.

Be aware that phase matching depends on the direction of the route. You may need to reverse the route direction from the context menu - see phase matching for more information.

You can see phase tolerance as yellow segments using the display phase offset command.

Total Length Out of Phase

The total distance over which the two tracks are deemed to be out of phase according to the phase tolerance. Unlike the unpaired length here we are considering tracks which are obeying the pairing distance. We are measuring the length over which these tracks differ in distance from the source pad(s).

The source pads are determined by the routing direction (src->dst) and are indicated by the pin descriptions in the table. You can reverse the differential pair from the right click context menu on one of the tracks on the layout if you have routed from dst -> src .

All coupled, out of phase segments

Distance out of phase is shown as red segments using the display phase offset context menu command.

Max Length Out of Phase

This is the maximum contiguous paired length that the two tracks are deemed to be out of phase according to the phase tolerance. It doesn't include serpentines or segments where the track separation exceeds the paired distance.

Largest length out of phase

Max Phase Mismatch

This is an indicator of the worst case scenario and provides the largest distance that the two tracks deviate by over the course of the route.

Pairing Distance

This is the default (and also preferred) separation of the two tracks as set in the Design Rule Manager (+ 1th tolerance).

Unpaired Length

This is the total distance over which the two tracks are spaced at a distance greater than the pairing distance. It is the cumulation of all the unpaired segments of the route.

Max Unpaired Length

The maximum distance that the tracks are unpaired for in the route. The actual value reported is the longer of the two lengths of track over which the separation exceeds the pairing distance.

Unpaired length generally results from serpentine segments used to equalize the track lengths. To correct an overly large reported unpaired length you need therefore to look at the corners during routing (causing the length mismatches) and/or the max unpaired separation specification (influencing the distance that the tracks are unpaired for).

It can also result from fanout from the source/receiver pins, covering the etched track distance used to get from the two pins into a paired state. Generally this is routed manually by the user and is unavoidable.

Longest section of unpaired trace

Max Unpaired Separation

This is the maximum space between the two tracks that occurs when the two tracks are not honouring the pairing distance.

While the specified value will be enforced for serpentine segments note that the actual maximum may well be due to an unavoidable fanout or termination routing which you have placed manually.

Largest distance allowed between two traces


DIFFERENTIAL PAIR SETUP

Introduction

Routing a differential pair on the layout first requires setup and configuration of the differential pair both on the schematic and in the design rule system on the layout. This topic covers all of the general setup requirements that enables you to route differential pairs in Proteus.

See Also:

Example: Routing a simple differential pair on one layer.

Example: Routing a differential pair with vias / fanout.

Example: Routing a differential pair through a passive component.

Example: Routing a differential pair with taps / branches to passives.

Schematic Setup

On the schematic there are two tasks required for a diff pair, namely to identify the differential pair pins and then to name the diff pair itself. Both of these are done with the diff pair configurator tool which is launched from the right click context menu on one of the two diff pair wires.

The differential Pair Configurator when opened.

1. Diff Pair Class.

Name of the diff pair class. This is used when setting clearances and separations for the diff pair. Can use an existing one if , for example, you have multiple channels.

2. Start Component.

The start component and the two diff pair pins on the start component.

3. Signal Path Indicator

Shows whether the diff pair signal path is completely specified from source to destination.

Examples of how the Signal Path Graphics inform you of configuration progress.

4. End Component.

The end component and the two diff pair pins on that component.

5. Manage Pass through components.

Manually specify pass through components if the heuristic fails to do it correctly. A deduced pass through will be suffixed with a question mark. If correct save will commit, if incorrect specify manually via the Manage Passthroughs button.

A pass through has 2 pins on at least one of the diff pair lines. A tap, branch or shunt is not a pass through component and will be ignored by the configurator. The goal of managing the passthroughs is to specify the two pins of the component that are on the line - a simple task for a two pin passive but possibly needs manually specifying for a 4-pin part spanning both lines.

6. Component pin count.

Since the start and end component are unlikely to be 2 pin devices this setting serves only to remove the clutter from the component pin listings.

Workflow :

This workflow assumes everything is placed and wired on the schematic. Make sure your connections are made with terminals and terminal labels and not junction dots and wire labels.

Use terminals and terminal names, not junction dots and wire labels.

  1. Name the diff pair class.
  2. Find the start component.
  3. Find the end component.
  4. Select the start component pins.
  5. Select the end component pins (if not done automatically)
  6. Manage the pass through components (if not done automatically)
  7. Save and exit when the configurator dialogue shows a complete signal path.

Start and End Components

Right click on one of the diff pair lines and select the diff pair configurator from the resulting context menu.

At the top, give the diff pair a class name or select an existing one. It's quite possible to have multiple diff pairs sharing the same class and this can be helpful when setting up diff pair routing rules on the layout. Next, select the start component and the end component.

Find the start and end components.

Start and End Pins

Next, select the two pins on the start component that form the differential pair.

If there are no passthrough components the end pins will populate automatically as you specify the start pins.

If there are no pass through components then the end component and pins should appear automatically and you can simply exit the dialogue form. If there are other components on the net the configurator will try to add them to the signal path along with the corresponding destination pin. Any pass through that the configurator adds will be suffixed with a question mark.

The configurator scans for pass through components.

If the pass through components are correct (and they usually will be) you don't need to do anything else and can simply save and exit the configurator when you are finished specifying the pins. If however, the pass through components are not correct or it's a single component with a lot of pins then you'll need to manage the pass through manually.

Add Pass Through Components

A pass-through component is one which has two pins on the same diff pair line (that the signal passes through). Sometimes, these have to be added manually to complete the signal path for the differential pair. Do this using the Manage Passthroughs button at the bottom of the configurator.

Specifying a placed and wired diode as a pass through component on a diff pair line.

Normally, you'll either be adding one component twice with different pins (e.g. a 4-pin component sitting across the pair) or two components with their pins as shown below.

Both diodes have been specified as pass-throughs and the signal path from source to receiver is complete.

Notice that the pass through components are not suffixed with a question mark because they have been added manually rather than deduced from the net topology.

It's possible to have pass through components on the diff pair at both ends in which case you just need to add them one by one to the configurator.

Pass through components on the other side still to be added - back to Manage Passthroughs Button.

Adding all of the pass through components results once again in a completed signal path from source to receiver.

All pass through components added - complete signal path shown. Save and Exit.

A branch or a tap or a shunt is not a pass-through. For example, if there were resistors to ground they would not affect the signal path and the configurator could be exited directly after setting the end component.

This ESD Protection device is NOT a passthrough component - only 1 pin per line.

Complete signal path - no pass through components on the diff pair lines.

Setting up pass through components allows the diff pair to be treated as a single entity from start pin to finish pin in terms of length matching.

See Also:

Example: Routing a differential pair through a passive component.

Net Class Setup

After the schematic setup is complete we are into the design rule manager on the layout module (Technology Menu).

Creating a new Net Class for the Differential Pair

We want to create a new net class so that we can:

  1. Specify routing styles such as track widths.
  2. Create specific design rules which we can apply only to the net class (the rules themselves are created at a later stage).

After setting the routing styles as required switch to the differential pair tab, select the correct diff pair and assign the net class to the diff pair.

Assigning the configured Net Class to the Differential Pair.

Note that unlike the normal assigning of a net class (with a wire label) all you need to do for a diff pair is set the net class on the dialogue form. This is because Proteus already knows about the wires via the setting of the PAIR name. This system allows you to configure one net class / design rule set and apply it to multiple differential pairs.

You may find it useful to change the ratsnest colour for the differential pairs in the net class tab. This will make them easier to find on the layout and, since they'll typically be routed early it's helpful to distinguish them from other connections.

Differential Pair Setup

The differential pair tab contains some extra fields for configuration. There is one field to control the length matching of the two tracks to each other and then several parameters to specify the allowable separation of the two tracks.

Minimum Paired Separation

This is the minimum (and also preferred) distance between the two tracks. Any increase from this distance would be considered unpaired and can happen either due to phase match serpentine segments or at the start and end of the routes while making connections to the pads. This value is used by the assisted routing mode to apply the separation between the two tracks. It is also used in the reporting to indicate when tracks may be uncoupled and the Pre-Production checker uses this value to test for compliance.

Note however that this is not automatically made into a design rule. We set up a specific design rule for this manually in the next section.

Maximum Unpaired Separation

This is the maximum distance between the two tracks that is allowed at any time.

Note that this affects the ability of the differential pair to phase match because it constrains the maximum height of a serpentine segment.

Max Phase Shift

Differential pairs are length matched against each other but this length matching cannot just be done at any time. To keep differential signals opposite you want to equalise the track lengths as soon as possible after they deviate.

Phase shift (sometimes called skew) is when the lengths of the two tracks becomes different. This typically happens when you change direction because the track on the outside of the corner traverses more distance during the change of direction. Fortunately, Proteus knows the lengths of both tracks and will automatically add serpentine segments to equalise their lengths when you finish placing the route.

Max Phase Shift is the allowable difference in track length due to a diversion or corner before serpentine routing is applied to one track to equalise their lengths.

It's important to understand that any corrective action (adding serpentine segments) can only be considered at the end of a corner or diversion. It's quite possible with a large curved corner therefore for the lengths of the two tracks to become significantly different before any serpentine is applied to correct their lengths.

Proteus can only equalise lengths on straight segments of track after a corner or diversion.

The equalising of routes is done post process, not during routing so you'll see it after you commit route placement.

See Also:

Phase Matching

Length Match Tolerance

This is the tolerance to which differential pairs must be matched against either a target length or a second differential pair. It has nothing to do with the matching of the lengths of the two tracks in a differential pair to each other which is covered by the phase matching tolerance field above.

See Also:

Example: Length Matching a Differential Pair

Maximum Unpaired Length

This is the maximum distance that is allowed for any deviation from the paired separation.

This value is checked in the differential pairs report and in the pre-production checker but is not used to constrain the phase matching. While unlikely, it is possible therefore that required phase matching breaches this distance. Should this happen you need to review the topology of the route (how many corners and how severe they are) to reduce the necessary phase matching.

Design Rule Setup

Now we can switch to the rule tab of the Design Rule Manager to set up any additional constraints that we want to apply to the diff pair. There are two rules which we would almost always set up:

  1. A rule to ensure adequate clearance from all other objects and the diff pair.
  2. A rule to enforce the clearance between the two tracks. This should be set to the paired distance value entered in the diff pairs tab.

We create a new rule and use the net class we created to narrow the scope of the rule to only the diff pair. Then in the first case we would set it to apply with respect all other net classes. This gives us clearances between the diff pair and everything else that we can set from the fields on the right hand side.

Creating a Design Rule to apply to the Diff Pair net class with respect other net classes (case 1 ).

You often want to limit the region of this rule to a particular layer. This allows you to set wide separation to other objects (e.g 3->5 x trace width) on the routing layer while not causing DRC errors on the fanout stubs from the source/destination pins.

For the second rule we again apply to the diff pair net class but this time we set it to apply to the same net class. This lets us set clearances between the two tracks of the diff pair and so of course we want to insert the clearance value we set for paired separation as the trace -> trace clearance.

Now creating a rule to set the clearance between the two tracks in the differential pair (Case 2). The Trace-Trace clearance is the paired separation value.

One of the benefits of working through these preparatory steps (create net class -> assign to diff pair -> create design rules) is that one net class can be used for multiple diff pairs (E.g. multiple DDR4 channels). In this case we would simply assign the same net class to each diff pair. Our created design rule would then apply to them all saving quite a bit of setup.


HIGH SPEED ROUTING EXAMPLES

Introduction

The examples below cover a range of common routing tasks on high speed signals or nets in Proteus. In all cases it is assumed that the board has been set up with the basics. This means:

  • The basic design rules from the Design Rule Manager and that you have a basic understanding of Net Classes.
  • A layer stackup and drill spans have been thought about and defined.
  • Layer pairs have been configured as required.
  • The Length Tuning Dialog Form has been configured as required.

Length Matching and Net Tuning are part of the Advanced Feature Set and are only available in PCB Design Level 2 or higher.

Example: Matching the Lengths of two Routes

To match the lengths of two routes:

1) Configure the length tuning as required from the dialogue form on the Technology Menu.

2) Enter selection mode and left click to select one of the routes.

3) Hold the CTRL button down on the keyboard and left click on the second route. You will then have both routes highlighted.

4) Right click on either one of the routes and select match lengths from the resulting context menu.

You can use this matching technique with as many tagged routes as you like. However, if you have a lot of routes close together (e.g. a bus) that you want to match it can be tricky for the software to automatically find the space to match all the routes in one operation. With a large bus therefore, you would tend to match a few routes, move the serpentines sections manually to create some space, then add a few more routes.

The Tag Connections tool on the Tools Menu is really helpful here and will select all connections between two components. In the case of a bus you may even be able to select and match them all directly.

Tag Connections selecting routes between U1 and U3. CTRL+click on a segment can de-select as well as select.

See Also:

Adding Routes to an Existing Matchgroup

Moving a Serpentine on a Route

If you select a track that has been length matched you will find that both the route length and also the target length are shown in the status bar.

Example: Setting the Length of a Single Route

To set the length of a particular route:

1) Right click on the route and select input target length from the length match menu.

2) Type in the target length along with unit suffix (mm, th, etc.). Obviously, the entered value must be larger than the current length of the route.

If you have configured length matching to have uniform height this operation will fail a significant portion of the time unless you have an extremely high tolerance. This is because the difference in lengths is unlikely to be an exact number of serpentines which would be required is the serpentines are not allowed to change size. We strongly recommend therefore that you allow irregular serpentines (turn regular height off) before attempting an absolute length set operation.

Example: Moving a Serpentine on a Route

You can move or position the serpentine section on the route as follows:

1) Select the route by left clicking on it.

2) Drag and drop with the left mouse. So, left depress the mouse over the serpentine section, drag to the desired location and release the mouse to drop in it's new location.

Troubleshooting

If a serpentine will not drag it is almost always because the design rules do not allow it to move. The classic example is shown below.

The upper serpentine cannot be dragged because the serpentine on the lower track is higher than the base line of the track (where the track would run if there was no wiggles). Any movement on the serpentine will result in a DRC error and therefore blocked. The solution is simply to first move the lower serpentine such that the one on the upper route is clear (e.g. having them perfectly out of phase).

Note also when dealing with complex length matching that you cannot move a serpentine onto a segment of track that is shared between two or more matchgroups (because it would change the length of all of the routes).

Example: Adding Routes to an Existing Matchgroup

It is quite common to want to length match a large number of routes and it can be tricky to do so in a single operation. The best way to length match multiple tracks is in several stages, allowing you to move serpentine lengths to maximise free space at each stage.

1) Length match the first few tracks.

2) Move the serpentines to make as much space as possible for serpentines in the next route.

3) Select one of the existing length matched routes and a couple more that you want to be matched and then length match again.

4) Repeat stages 2 and 3 as often as required.

See Also:

Moving a Serpentine on a Route

Example: Removing a Serpentine from a Route

To remove a length match (serpentine segment) from a route:

1) Right click on the route and select Remove Length Match command from the context menu.

This will restore the route to it's previous (original) etched copper length and remove it from the matchgroup that it belonged to. Also:

  • If the routes in the matchgroup have been length matched against each other and you have removed the route with the longest original length then the matchgroup will be regenerated. All other routes will be matched to the length of the longest route remaining in the matchgroup.
  • If the routes in the matchgroup were matched to a specific length (via the input target length command) then there will be no change to the other routes in the matchgroup.
  • If the route is the last or only route in the matchgroup then the matchgroup will also be destroyed at this point.

Example: Selecting all Routes in the Same Matchgroup

To see all of the routes in the same matchgroup:

Either:

1) Right Click on one of the tracks and select 'Tag LengthMatches'

Or

2) Generate a length match report in the Project Notes module - this report is grouped by matchgroup

Or

3) Select connectivity highlights mode, change the filter to length matched only and then double click on one track in a matchgroup to select the entire matchgroup on the layout.

See Also:

Producing a Length Match Report

Example: Length Matching with Fly-By Topology

First, apply internal lengths if required.

Next, find the route with the shortest length of common track and use the CTRL button with successive left clicks to select the entire route from source pin to destination pin. You can also use the Tag Connections comtmand on the Tools Menu.

Quickly tag connections between components using the command on the Tools Menu.

Or simply hold CTRL down and tag segments consecutively.

Right click and match to calculated length. Move the serpentine segment as required.

Now hold CTRL button down and successively left click on each section to highlight the next route. Again, we are going from source pin all the way through to destination pin, including segments of track that may have been selected in our previous match.

Right click and match to calculated length.

Repeat as required with other routes.

Example: Adding Internal Lengths to the Calculations

First, get the required data from your manufacturers software. If this is coming out as a delay you'll need to use the dielectric of the chip to translate into a distance.

Open a copy of notepad or similar and type a comma separated file of pin names and internal lengths. Save the file and then apply the internal lengths via the context menu command on the footprint in ARES. The example below is for a BGA:

Example: Editing and Re-matching a Matchgroup

The good news here is that re-matching is automatic after an edit so, provided there is enough space on the layout, everything should just work. However, you still need to:

  1. Verify that everything has worked and is inside tolerance.
  2. Fix it if it hasn't.

So, let's assume we've had to nudge a memory IC a little and a bunch of routes from it are length matched. We need to assess the impact on the length matched tracks so we switch the parts bin into Matchgroup Viewer mode. Do this by selecting connectivity highlights and then filtering the result set to length matched.

See Also:

Viewing and Browsing Matchgroups

Routes are grouped by matchgroup and the right hand side of the display shows the compliance of each length matched route to it's target (T). Hovering the mouse over the selected route will show you both the target distance and the tolerance in a tooltip. Assuming all is well therefore the right hand side should all be green.

If a route is non-compliant it will be in red and an indication provided of how badly it's outside of target distance. Double clicking on this will tag the route making it easier to adjust and the display will update live after each edit.

It is possible, although unlikely, that no matching could take place at all after an edit which disturbs a matchgroup. This would create a situation where previously length matched routes are no longer length matched at all and therefore no longer in the length matched viewer. So, the first check should be that your matchgroups are all present in the viewer after editing their lengths.

Example: Producing a Length Match Report

The length match report is created in the Project Notes module and contains information about each route including pin names, matched length together with tolerances and internal lengths. To generate a length match report:

1) Open the Project Notes module and select the length match report template.

2) The report will auto-generate and can be saved out as a PDF file or stored with the Proteus project itself.

3) You can regenerate the report after changes via the right click context menu command.

The length match table is known as a data object and can be inserted into any report you like. So, you can create your own report / corporate style and then insert data objects like this into it.


DIFFERENTIAL PAIR ROUTING EXAMPLES

Example: Routing a Differential Pair on a Single Layer

This is the simplest of all cases and perhaps also the least likely to happen in practise.

Both components are on the same layer and the diff pair tracks are also on that layer (i.e. no vias)

Setup

The setup and configuration are standard and as described in the topic linked below.

Differential Pair Setup

Routing

Always try hard to rotate (or re-map) such that diff pair ratsnest lines are not crossed. Crossed ratsnest lines will make for very awkward entry at the receiver.

We start by selecting diff pair routing mode and then click on one of the target pins of the source / driver device. Direction is important for phase matching so you want to route from source to receiver. At this stage Proteus will automatically route an exit from both source pins and we can continue routing both tracks as though we were routing a single fat track. We move the mouse to a destination pin and left click to finish routing. Again, Proteus will automatically route from both tracks to the terminating pins and complete the route. Finally, when the route is complete phase matching on the tracks is performed to equalise their lengths.

Example: Routing a Differential Pair with Vias

This is a far more common situation where you either want or need to route the differential pair on a different layer than the source/receiver pins. In our test jig below we are working with a BGA and will need to escape onto an inner layer for diff pair routing.

No chance of automatic fanouts. Manual Intervention will be needed !

Setup

Follow the standard setup and configuration as described in the topic linked below.

Differential Pair Setup

Routing

The first routing task is the fanout from the source pins and the destination pins. We do this using normal routing mode.

Manual fanout in normal routing mode to set up the routing layer for the diff pair.

Note that when we pick up the route in diff pair mode it will automatically find the pairing distance so we don't need to be absolutely precise with the fanout.

Next, switch to differential pair routing mode and click on one of the vias routed from the source pins (direction of routing matters for phase matching). Route towards the receiver pins (hold CTRL down for curved routing). Either press ENTER to auto-complete or route all the way and left click on one of the vias connected to the receiver.

Routing in differential pair mode - ENTER to auto-complete, CTRL for curved corners.

A couple of notes about routing if you need to change direction:

  1. An 'S' configuration will to some extent naturally bring things back into phase as you are cornering in a different direction the second time from the first.
  2. Leave a straight segment between curved corners if you can. Phase matching serpentine segments can only occur on straight segments.

Where Phase Matching is required it will be applied automatically on the next straight segment after a corner.

When you complete the route the phase matching will take place automatically and the lengths of the two tracks will be equalised after each corner and, depending on your fanout, possibly at each end of the route.

Remember that phase matching depends on direction so you may need to reverse the route direction (ctx menu command) if you have routed receiver to source.

See Also:

Phase Matching

Example: Routing a Differential Pair with Branched Passives

This case is much the same as the previous one except for the routing topology. Here we tap off the diff pair routes to a passive device (or devices) rather than insert one in the middle of the diff pair.

Setup

Follow the standard setup and configuration steps. While we've wired on the ESD device it doesn't split the diff pair so we only need one pair and no extra configuration is required.

See Also:

Differential Pair Setup

Routing

Follow the basic routing procedures documented in the previous samples to first fanout from the source / receiver pins in normal routing mode and then route them together in diff pair routing mode. After the diff pair is routed position the passive device and connect it using standard routing mode.

Route the diff pair and then place and wire any passive branches.

Important Note:

Nothing in this process monitors the stub lengths from the passive device(s) or what their effect might be on the differential signal. The only action taken by Proteus with respect to these branches is to ignore their lengths for the purposes of the differential pair report and the pre-production check testing.

Example: Manual Differential Pair Routing

It is always possible to route the differential pair manually and then engage the phase matching from the context menu. This means that if the diff pair routing algorithm can't cope with your board topology you can still complete the pair.

Setup

Follow the standard setup procedures

See Also:

Differential Pair Setup

In particular, the design rules are critical here because you will be routing the two tracks separately.

Routing

Route the first track in normal tracking mode and then route the second track, hugging it to the first one.

Route the second track manually hugging the mouse to the first one.

Once complete, right click on one of the tracks and select phase match from the resulting context menu.

Phase match manually after you have completed both routes.

Please let us know if you have to revert to manual routing of diff pairs. If you are able to send us use cases where the assisted mode fails (support@labcenter.com) that would be a great help to us in improving the differential pairs routing algorithm.

Remember that phase matching depends on direction so you may have to use the reverse route direction command first. You want to phase match from source to receiver. The differential pairs report will show you the routing direction that Proteus has for the tracks.

Example: Length Matching Differential Pairs

You can use the length matching technology in Proteus to match a differential either to another differential pair or to a target length.

The first step is to configure the shape and style of the serpentine segments. You can do this from the differential pair tab of the length matching dialogue form.

Length Matching Configuration

You'll find detailed context sensitive help on each field via the question mark at the top right of the dialogue form.

Once we've set the topology for the length match segments we need to set up the tolerance. Since this is normally specific to the protocol you are working with it is set in the design rule manager and associated with a net class.

Length Match Tolerance.

Now that the setup is complete we can do the actual length matching. To match to a specific distance right click on one track in the differential pair and select length matching -> input target length.

Set the target length for the differential pair.

Alternatively, to match against another differential select one track on the diff pair and then hold the CTRL button down and select one track on the other differential pair. When you have a track selected on each diff pair right click on either one of the tracks and select the automatic match lengths option from the context menu.

Matching the length of two diff pairs to each other.

Phase Matching vs Length Matching

  • Phase matching (or skew correction) is the correction of the lengths in a differential pair against each other. Almost always this happens after a corner where the outside track becomes longer than the inside track as the routes traverse the corner.
  • Length matching (or tuning) is controlling the distance of both routes in the differential pair. Serpentine segments are added to both routes in sync in order to lengthen the differential pair to either a target distance or to another differential pair.

There is an interaction between length matching and phase matching that can occasionally cause problems. Since length matching adds serpentine segments it adds corners which causes the length of tracks in the diff pair to be different and out of phase. Fortunately, anything approaching an 'S' shape will auto-correct as the longer track on the first corner becomes the shorter track on the second corner.

When you length match a diff pair Proteus will first perform the length matching and it will then perform an automatic phase matching. What this means is that if the length matching requires phase matching then the phase matching itself may add slightly to the length. This is where both tolerances and placement become important. The designer needs to be aware of tolerances and may even need to tweak them when length matching to prioritise either phase or length. Placement is also hugely important and can help a lot to reduce phase mismatch during routing.

See Also:

Phase Matching

Example: Routing a Diff Pair with Pass-Through Components

A pass-through component is just a passive on the diff pair line where two pins are on the same line and therefore through which the signal will pass. These should be placed and wired on the schematic in the normal way.

Add the pass through components on the schematic in the normal way.

Then, right click on one of the diff pair lines and select the diff pair configurator from the resulting context menu.

The start and end of the diff pair should be set up in the normal way and then the manage passthrough button can be used to specify which components and pins should be considered as part of the DP.

Select and specify Pass through component

Then, on the layout side place the passives in position as you would normally. It may be necessary to fan out from the pads if the routing will take place on a different layer and this should be done manually.

Place the pass through components in position and handle any required fanout vias.

Finally, switch to the diff pair trace mode and selecting the required routing layer, you can complete the tracks as normal.

Length Calculations

When a pass through component is used in a diff pair it affects the length of the pair. Proteus constructs the diff pair length from the following:

1) the etched length of copper on the board (the tracking)

2) the specified internal length of any pins

3) the straight line distance on the PCB between the pads of the pass through component.

Number 2 is specified by adding internal lengths to a component on the PCB whereas both 1 and 3 are calculated automatically by the system.

The differential pairs report will show both the etched and the total length for each routed pair where the total length is the contribution from numbers 2 and 3 above.

Adding internal lengths to a pass through component.

You can length match differential pairs with pass through components in them in exactly the same way as you would normally.


TEMPLATES & TECHNOLOGY

Overview

ARES includes a comprehensive scheme for design re-use in the form of board templates and technology data. Whenever a new project is started, the PCB is initialised from a template which provides a way to re-use configured information.

Users can create their own templates for common layout types and then select them for re-use in future projects.

The generic templates in particular are useful as they all have pre-configured layer stacks for standard 1.6mm PCB's.

Template Files

A template file will contain the following:

  • Board Edge
  • 2D Graphics (e.g. Company Logo)
  • Loose Pads (e.g. Mounting Holes)
  • Additional components/tracks, etc.

In addition, the current settings of the technology data is always stored when a file is saved as a template.

Technology Data

The technology data set comprises all of the settings on the technology menu in ARES, namely:

  • Design Rules and Net Classes
  • Grid Settings
  • Layer Stackup and Drill Spans
  • Layer Pairs
  • Teardrop Configuration
  • Length Tuning Configuration
  • Text Styles
  • Board Properties

Changes to these settings are local to the current layout until the user saves the file as a Template, in which case the current settings are saved inside the Template for re-use in future designs.


CREATING TEMPLATES

Overview

Most users will want to create one or more Templates of their own to reflect the type of boards that they develop. This is an extremely straightforward process:

  • Define Technology Data.
  • Define Physical Board Skeleton.
  • Save the Template.

Defining Technology Data

The technology data block stored in a Template file is basically all of the options in the Technology Menu.

Design Rules

This dialogue allows you to define and organise board constraints and also to provide routing information for the auto-router. Note that on the Net Classes Tab you can now create a new net class. This allows you to set up 'placeholders' so that if you work on a schematic and define that net class the design rules will be picked up when you initialise the layout file from the template.

See Also:

Design Rules and Net Classes (Tutorial)

Routing Classes

Grids

This dialogue allows you to specify the snap settings for both imperial and metric co-ordinate systems. It also allows you to specify the default units of measurement for a new session.

The start-up units define which units ARES defaults to when you start a new session rather than which units you were last working on when you closed ARES.

Layer Stackup & Drill Spans

The layer stackup provides information on how many copper layers are in use and, together with cores and pre-preg, the construction of the PCB. This information is then exported in the CADCAM readme file for the fab house and also used by Proteus to verify via drill ranges and form connections to plane layers.

Layer Stackup Manager in Proteus

See Also:

About Layer Stackups

About Drill Spans

Layer Pairs

This dialogue allows you to specify the via through level for each layer on the board. This is used when routing manually and determines which layer you end up on when you place a via.

For example, on a two layer board, placing a via on top copper will take you to bottom copper and placing a via on bottom copper will take you to top copper.

The settings on this dialogue form are governed by the layer stackup. For example, if you have a defined a 4-layer board (Top Copper, Inner 1, Inner 2, Bottom Copper) you will not be able to set a layer pair either from or to inner 9 on this dialogue form.

Using the SPACE bar in the main application will toggle the current layer according to the layer pair configuration for that layer.

See Also:

Layer Pairs and Manual Routing (Tutorial)

Length Matching

Length tuning or length matching is often used with higher speed or longer distance signal runs on the PCB to improve signal timing or signal integrity. The basic idea is that the shorter trace follows a detour or meander in order to lengthen it to match the length of the longer trace. The settings on this dialogue then enables various configurations of serpentine pattern which will then be used when you length match traces on the board.

Length Tuning Configuration

See Also:

Length Matching / Net Tuning.

Length Tuning is part of the Advanced Features Set and requires a PCB Design Level 2 or higher.

Teardrop Configuration

Placing teardrops at the connection point between track and pad is often useful in preventing drill breakout during board manufacture. The settings in this dialogue control the placement of teardrops on the layout.

Teardrop Configuration

See Also :

Teardrops

Text and Graphics

This dialogue allows you to configure font settings and visibility for part reference, part values and 2D Graphics. You can also define the width of any 2D graphic lines used on the board.

Board Properties

This dialogue allows for the configuration of the global work area as well as the both the board and feature thickness. The latter settings are used in the IDF output from ARES and for the 3D Viewer display.

Defining Board Skeleton

The board skeleton can consist of board edge, 2D Graphics and mounting holes. In the example below, we have set up a simple rectangular board edge with 3mm mounting holes positioned for mini-locking PCB supports and have included the Labcenter company logo.

You can also include components/tracks and other objects in a template. In the example below, we have a eurocard with a placed connector.

See Also:

The Board Edge (Tutorial)

Mounting Holes and Pad Styles (Tutorial)

It is crucial to understand that templates that contain components will need to have their annotations matched to the schematic. In other words you need to make sure that the connector (J1) corresponds to the J1 connector on your schematic. If it corresponds to the J2 connector on the schematic then you need to change the annotation on the layout to be J2 before you netlist. Clearly, if you save a template with many components this may involve considerable manual re-annotation on the layout.

If you are at all unsure about this we strongly recommend that you do not save templates with components or tracks. You can easily strip these objects from an existing layout with the selection filter.

Saving the Template

Having completed the Template configuration we simply use the Save as Template command on the Technology Menu and provide a sensible name.

Whenever we start a new layout we will now be offered this Template as an option for the new board.

More information on Saving Templates can be found here.


Saving and LoadingTemplates

SAVING & LOADING TEMPLATES

Saving Templates

Invoking the 'Save Layout as Template' command on the Technology Menu will save the current board skeleton and technology data on the current layout as a Template for re-use in future designs.

Saving the layout as a template

Anything on the layout will be saved as a template when you invoke this command. This may not be what you want - for example, you may wish to use the board edge and mounting holes but not the components as they are specific to the current layout. You can easily strip such objects from the layout using the selection filter before saving as a template.

Saving a template that contains components and tracking can cause problems. When initialising from that template you must re-annotate any of the components on the layout to match the annotation of their equivalent schematic parts.

A couple of examples of removing items from a layout before saving the template are outlined below

To delete all components, zones and tracks from the layout

  1. Draw a tagbox around the entire board.
  2. Adjust the selection filter to include only loose pads (mounting holes) and graphics.

  3. Hit the delete button
  4. Remove any other unwanted graphics.

To remove stitching pads from the layout:

  1. Use connectivity highlights to select the net that the pads are on.
  2. Hit the delete button to delete the net (and therefore the pads).

To save only the board edge

  1. Draw a tagbox around the entire board.
  2. Select all object types except 2D graphics from the selection filter

  3. Hit the delete button
  4. Remove other unwanted 2D Graphics.

Saving Technology Data requires the saving of a template. If this is all you want to store you can simply delete the board entire before invoking the save command.

Loading Templates

When you create a new project you are presented with the option to initialise the layout from one of the Templates.

You cannot load a Template into an existing project as the board edge, location of graphics objects etc. will almost certainly be different. Instead, you can apply the Technology Data from an existing template into a current design via the Apply From Template command on the Technology Menu.

More information on Applying Technology Data can be found here.


APPLYING TECHNOLOGY DATA

Overview

Technology data can only be saved as part of the template but it is sometimes useful to import only the technology information into another project. This allows you, for example, to re-use a set of design rules in multiple projects, regardless of the physical dimensions of the board.

The Apply from Template command is invoked from the Technology Menu.

Effects on Current Layout

When you apply technology data from a template the basic rule is that anything in the technology data will override its equivalent setting in the current layout. Specifically, the following rules are applied to the import:

  • A net class/design rule in the current layout that has an equivalent net class/design rule in the imported technology data (same name) will be overwritten with the information in the technology data.
  • A net class/design rule that no equivalent in the imported technology data will remain unchanged.
  • The default settings (neck & relief styles and tolerances) will be overwritten with their equivalent settings in the technology data.
  • Grid Settings, Layer Pairs, Layer Usage, Text Styles will all be updated from the technology data.
  • Board and Feature thickness settings will be updated from the technology data. Work area will remain unchanged as the current layout may be larger than the settings in the technology data.


General

LIBRARY OVERVIEW

Introduction

As supplied there are 2 symbol libraries (which are shared with the Capture Module):

  • SYSTEM.LIB
  • USERSYM.LIB

and many package libraries including:

  • PACKAGE.LIB
  • CONNECTORS.LIB
  • SMTCHIP.LIB
  • SMTDISC.LIB
  • SMTBGA.LIB
  • USERPKG.LIB

You can, of course, create further libraries of your own using the Library Manager

Library Discipline

The LIBRARY directory as installed with Proteus contains two symbol libraries and over 120 device libraries as well as various essential utility files. The following extensions are used :

  • Library Files (.LIB)
  • Index Files (.IDX)
  • 3D Model Files (.VML or .3DS)
  • Master Style File (.STY)
  • Configuration Files (.INI).

The path to the LIBRARY directory is set by the installer to the users ProgramData branch. You can change or add another library path from inside the Proteus application (System Menu - System Settings command).

System Settings showing the Library section

We would recommend that you not move your LIBRARY directory (or add another one) unless you need to and that before making any changes you read the following potential issues and requirements carefully :

  • Three libraries, namely USERDVC.LIB, USERPKG.LIB and USERSYM.LIB are installed read/write and intended for users to create their own components, footprints and symbols. You can create additional libraries if need be through library manager. All other installed libraries are installed as read only and contain Labcenter supplied library parts. If you make Labcenter Libraries writable then you will lose changes to those libraries when you update your software. Labcenter libraries are overwritten by the installer to allow to continue to add support for new parts.
  • If you move your library folder onto a network then it is vital that the directory is fully read/write to all users. If Proteus cannot write the library directory it simply will not work.
  • If you elect to have more than one library folder (e.g. one local and one network) then they must be completely de-duped. Two libraries or files with the same name in different places will at best result in confusion as nobody will know which one was loaded.
  • Under no circumstances should you remove items from SYSTEM.LIB.

The Library Browser

To open the Library browser, click on the 'P' button above the Object selector, or press P on the keyboard. Each part in the package libraries is assigned a Category, a Type, a Sub-Category and a textual Description. This information is displayed by the Library Browser and makes it very easy to search the libraries for the parts you require.

Library Browser dialogue form

To search the libraries for a part using keywords

  1. Enter keywords that describe the part into the Description field. The search operates by matching the keywords against the parts’ names, descriptions, categories and sub-categories.

    If you enter several keywords, they must all be matched against a part for that part to show in the results. In other words, it is implicitly an AND search. Unless you check the Match Whole Words checkbox, then partial matches are allowed, so ‘DIL’ will match ‘DIL08’ and so on.
  2. If the keyword(s) result in a lot of matches – for example ‘capacitor’ will match many parts in the libraries, you can use the Category, Type and Sub-Category fields to refine the search.
  3. Pick the part(s) you require by double clicking them in the Results list.

To browse the libraries for a part by category and sub-category

  1. Ensure that the Description field is empty.
  2. Select the Category and (optionally) Type of the part you are looking for. This will cause the Sub-Category list to show options appropriate for the chosen category.
  3. Select a sub-category to refine the search further.
  4. If you still have a large number of results, you can type a keyword into the Description field in order to further refine your search.

If you can't find the footprint you want in the installed libraries the fastest solution is to use the library browser in the schematic capture module to import a part that uses the footprint you want. The schematic library browser includes an integrated web search returning over 15 million parts along with their associated footprints and - in most cases - 3D Step files.

Libraries from earlier versions of Proteus

Existing user package libraries from versions of Proteus prior to 6.6 will not contain category and sub-category information. Parts from these libraries will appear under the Unspecified category, and the library names will be used for the sub-categories.

Information on how to index your own libraries is provided in the Schematic help documentation

Updating the Layout from the Libraries

If you pick a package or symbol that is already loaded into the layout, ARES will update it from the libraries on disk.

Note also:

  • Where packages are concerned, you should be aware that ARES simply aligns the new part on the old part’s origin. This means that the pads may well end up in different positions and some manual re-tracking of the board will be required.
  • Where a there are two or more packages or symbols with the same name spread across several libraries, the Pick command will load the newest one. This is particularly helpful if you have changed one of our parts and put in USERPKG.LIB, since your version will be deemed newer than ours.

While generally speaking package update works seamlessly, be aware that in some situations a sensible results is simply not possible. For example, if you remake a part with fewer pins then an overlay replace is not feasible. You should always visually inspect the layout after updating footprints.

The Tidy Command

The Tidy command on the Edit menu performs several functions, one of which is to remove all packages and symbols from the selectors that are not actually in use on the layout.

This saves memory and also simplifies picking the ones you are actually using.


Package Library

THE PACKAGE LIBRARY

Overview

A package is a collection of pads and silk screen graphics used to site a component on the board. A library of many common package styles is provided and this will save you a great deal of time compared with manual methods of PCB layout. However there will be occasions when you will have to create your own packages, and the steps to follow are set out below.

While the following topics are a detailed explanation of how to create component parts in Proteus, in practise this should almost never be necessary. In addition to the many installed libraries the schematic library picker includes a web search which enables you to import from over 15 million library parts. When you import, both the schematic component and the PCB footprint will be brought in (in most cases, also the 3D STEP file). There is also a FOC part creation service so manual footprint creation should not be something you need to do.

For those customers without a valid USC (who can't therefore use the web search in the schematic library picker), you can still use the universal part importer provides support for almost all third party part vendors (Ultra-Librarian, Samacsys, SnapEDA, etc.). If the part doesn't exist in Proteus itself the next step is to search for and then import it directly from a third party vendor. This is discussed in some detail in the importer help file and shown on our Youtube Channel.

Making a Package

To make a new library package:

  1. Select the appropriate pad shape icons and place the pads of the package as required. Use the Layer Selector to place the pads on the appropriate layers. See below for more information.

  2. By default, ARES will give the pins numbers from '1' upwards, numbering them in the order they were placed. If this is not what is required, you must either renumber them with the Auto Name Generator, or else edit them manually. See below for more information.
  3. Select the appropriate 2D graphics icons and place silk screen graphics as required. A package can have legends on both the component side and solder side screens; these will be swapped if the package is placed with the mirror icon active.
  4. Tag all the objects by dragging a box round them.
  5. Invoke the Make Package command on the Library menu. The Make Package dialogue form will appear as shown below

  6. Enter a name, category, type, sub-category and description for the new package and then choose a package library to store it in - typically this will be USERPKG.LIB. When you are done you can either switch to the 3D Visualisation Tab to create a 3D model for the package or simply commit the parts to the library with no 3D information.

  7. In the 3D Visualisation tab enter 3D information according to the provided syntax to present a 3D image of the package – this will be stored and will appear in the 3D Viewer henceforth. The job is greatly aided by a 3D Preview on the dialogue form which will update live as parameters are entered and and adjusted.

  8. Click OK to commit the package (and optionally 3D information into the specified library.

Note that the description you enter via the Make Package dialogue form will be used via the Library Browser when searching via keywords. While not of particular importance in our test case you should give some thought when creating a part to ensure that the description contains keywords that you would use to identify the part during a search

The reference or 'anchor point' for a package can be determined by placing the ORIGIN marker. If there is no ORIGIN marker, the reference will be the centre of first pin placed. Markers are accessed by selecting the Marker icon.

It is also possible to define non-default positions for the reference and/or value labels. To do this, place the REFERENCE or VALUE markers at the required position(s).

See Also:

APPENDIX: Creating New Packages (Tutorial)

Creating Advanced Footprints: QFN with Thermal Pad (Stipled Paste Mask).

Creating Advanced Footprints: Button Pads and Touch Pads

Storing Vias and Breakout/Fanout tracks in the Libraries

Choosing the Correct Layers for the Pins

Ordinary pad styles can be placed on single copper layers, or on all the copper layers as defined by the current setting of the Layer Selector.

  • For ordinary through hole parts, you should placed the pads on all the layers.
  • For SMT parts, you should place the pads on the top layer only. If such a part is placed on the Solder Side, the pads will be automatically transferred to the bottom copper layer.
  • For doubled sided edge connectors, you should place separate fingers on both the top and bottom copper layers.
  • If you need different shaped pads on different layers for a through hole pin, you should use pad stacks as defined under Pad Stacks.

The Replicate Command

ARES provides a command to replicate tagged objects at a specified spacings. This will operate in X and/or Y when you are in cartesian co-ordinates and based on an angle offset and an origin when you are in polar co-ordinates (View Menu toggle) This can be extremely useful when creating new packages as you can use it to lay out rows of pads with the spacings entered directly from the keyboard.

To place a row of pads by replication (Cartesian)

  1. Make sure that the Polar Co-ordinate toggle is off (View Menu).
  2. Place a single pad of the require style at the first position of the row.
  3. Ensure no other objects are tagged, and then tag the pad with the right mouse button.
  4. Right click on the pad and select the Replicate command from the context menu.
  5. Enter the required X-Step (for a row) or Y-Step (for a column). Remember to enter a dimension suffix for these values - e.g. 20th or 1.5mm.
  6. Enter the number of copies - this should be one less that the total number of pads required as you have placed one already.
  7. Click OK - ARES will replicate the original pad as specified.

To place a circle of pads by replication (Polar)

  1. Turn the Polar Co-ordinate toggle on (View Menu).
  2. Place a False Origin on the layout ('O' Shortcut key).
  3. Orient your first pad if necessary and then place it at radius distance from the false origin.
  4. Right click on the pad, select the replicate command and specify angle (e.g. 20) and number (e.g. 17) to replicate in a circle.
  5. Click OK - ARES will replicate the original pad as specified.

This technique is demonstrated in the appendix to the tutorial in the documentation.

You can extend this principle to creating grids of pads by replicating a pre-laid row.

You can also use the Replicate command to duplicate identical blocks of circuitry. The procedure for this is :

1) Design one block inside a sub-circuit on the schematic.

2) Drag a box around the sub-circuit and block copy to make the second copy. Change the name of the block but not the name of the circuit.

3) Place and route one of the blocks in ARES.

4) Drag a selection box around the circuitry in ARES and select the Replicate command.

5) Choose the name of the second block from the bind to combo box

Pin Numbering

When a netlist is loaded, ARES attempts to match pin numbers appearing in the netlist with the pin numbers assigned to the pins of the component packages. Where a match cannot be found, this is an error and either the ISIS library part or the ARES library part must be changed.

When you are defining an ARES library part, there are three ways to control the pin numbering:

  • By default, the pins will be numbering from '1' upwards in the order that they were placed.
  • If you invoke the Auto Name Generator command on the Tools menu, you can then click on the pads in any order you like to assign incrementing pin numbers.
  • If you select the Instant Edit icon, you can click on each pin and key in the pin numbers manually.

Note that trying to use a mix of default and manual pin numbering is likely to lead you to confusion and mistakes.

Other Points

ARES normally chooses locations for the part ID and value; these labels can always be moved after a part has been placed by tagging it, pointing at the label you wish to move, and dragging with the left mouse button depressed. The locations chosen will generally be good enough as is, unless many components are closely packed together.

However, if you wish to force the label to a particular default position, you can use the REFERENCE and VALUE markers, as described above.

The size of the labels is set by the Text Style command on the Technology menu. This will apply globally except for labels whose size has been manually edited.

Editing a Package

To edit and existing library package

  1. Select the Package icon.
  2. Pick the package to be edited from the library (using the toggle on the Object Selector) and place it on the work area.
  3. Tag the package with the right hand mouse button and then invoke the Decompose command from the context menu. This will break the package into its constituent pads and 2D graphics and also place an ORIGIN marker at the location of the part's placement reference.
  4. Edit the pads and graphics as required.
  5. When you have finished you can use the Make Package command to re-store the package either with the same name as before, or as a new part.

Pick and place the package > Decompose and amend > re-make the package

Of course, if the original package came from PACKAGE, which is normally read only, you will have to store it back to USERPKG. We recommend against using Library Manager to re-copy the part to PACKAGE as this can cause problems for you when we issue a new PACKAGE.LIB - how are you going to sort out which parts have been edited by you in order to preserve them?

Note that the pins will carry the pin numbers from the original package so decomposing a DIL14, sticking two pins on the end, and then re-making is not the way to make a DIL16 unless you are prepared the to re-number all the pins manually.


Symbol Library

THE SYMBOL LIBRARY

Overview

A symbol is a group of graphic objects which are treated as a single object. For instance, using 4 lines and two arcs you can form an AND gate symbol.

A symbol may be created by tagging the objects you wish to form it and then invoking the Make Symbol command on the Edit menu. Layers are ignored for this purpose. A form will appear allowing you to name the symbol which will then be stored in the Symbol Library and made available for immediate placement from the Object Selector. If there is already a symbol with the same name, it will be replaced.

ARES quite happily allows a symbol to contain other symbols and/or other graphic objects. This allows you to make, for instance, a NAND gate out of the previously defined AND gate plus a circle.

As with packages, the placement reference for a symbol may be determined by placing an ORIGIN symbol.

ISIS and ARES symbols are essentially exchangeable, and all symbol libraries have the type 'PROTEUS SYMBOL LIBRARY'. However, ARES does not support all of the drawing appearance features of ISIS, so correct rendering of ISIS symbols with complex fill patterns is not guaranteed, especially for CADCAM output where we can say with some certainty that it will not work!


NETLIST FEATURES

Overview

A netlist is basically the extraction of electrical data from one part of a CAD package into a form that can be interpreted by other parts of the CAD package.

In traditional CAD design, the netlist is created from a schematic and transmitted at the press of a button. This is a batch operation where all of the design changes made are propagated at the same time. By contrast, a live netlist means that individual changes to the schematic are automatically reflected in the other application modules.

Proteus 8 makes extensive use of live netlisting while retaining the option of batch mode netlisting for PCB layout. The ISIS schematic capture module generates the netlist and transmits it to the rest of the system. When you make changes to the schematic that affect electrical connectivity (wiring, placement, deletion, etc.) the netlist is also changed in the background and reflected in the other application modules.

The PCB Layout module receives netlist data from the capture module in one of two ways:

  • When live netlisting is enabled data is received whenever the ARES module is open and visible.
  • When live netlisting is off data is received when you manually click on the padlock icon at the bottom of ARES. The padlock icon will appear when changes to the netlist have occurred (ISIS has changed) but have not been received.

Live Netlisting

When live netlisting is on changes made to the schematic will be received by the layout immediately if the layout module is already open and visible or immediately after it is brought to the foreground.

A change that adds to the layout will simply update on the board. For example, the adding of a connection in ISIS will add ratsnest lines in ARES.

A change in ISIS that removes tracks or components from the board requires manual confirmation. Objects which have been removed from the schematic will appear dimmed in ARES and will then be removed entirely when you click on 'changes pending' to synchronise with the schematic. Below is what is seen when the 'Dimmed' colour in Displayed layers is changed to yellow and a component is deleted.

Live Netlisting is on by default, except where a legacy project is imported in which case live netlisting is off by default and must be switched on manually before any editing.

Batch Netlisting

When live netlisting is off a change to the schematic will lock the layout until you manually choose to accept the netlist data. You do this by clicking on the 'out of sync' padlock icon at the bottom of ARES. This is equivalent of 'Netlist to ARES' in previous versions.

Once the netlist is received you may also have to accept pending changes to the layout if the schematic changes made remove objects already on the board.

Note that after importing a design and layout file (DSN & LYT) via the Import Wizard you must turn live netlisting on before working on the project. After completing the import wizard, the schematic and layout have been brought into Proteus 8 exactly as they were in Proteus 7 (i.e. two seperate entities). However, there is no binding between the two, nor has any netlist information been passed from schematic to layout (Live netlisting is switched off). This is because the relationship between the schematic connectivity and the layout connectivity is unknown and we do not want to automatically make changes to a layout that may not be intended (or go unnoticed) by the designer

See Also:

Importing a Version 7 DSN & LYT.

Switching Netlist Modes

When you create a new project live netlisting is enabled by default. You can switch it off from the toggle on the Tools menu in ARES.

Importing from Older Versions

When you import a legacy project from an older version of Proteus live netlisting is switched off by default. You must turn live netlisting on manually from the toggle on the Tools menu in ARES to synch the schematic and layout before doing any further work on the project.

This initial synch will pass the connectivity of the schematic through to the layout and will also bind the parts on the layout to the components on the schematic in the project database.

We do not imagine that anyone would import a semi-complete project but if this does happen note that no components will be available for placement on the layout until you sync (turn live netlisting on from the ARES tools menu).

See Also:

Importing a Version 7 DSN & LYT.

We would advise that during development users should work with live netlisting switched on.

The main reason for switching live netlisting off would be on larger layouts with multiple zones where there may be a performance penalty because all of the zone connectivity will be re-calculated on each schematic change. Note however that leaving Live Netlisting On and simply closing the ARES tab or frame is just as optimal - netlist updates do not occur in the background.

Netlists and Synchronization

Communication between schematic and PCB works by synchronizing the netlist generated from the schematic with the layout. As described above this can be semi-automatic (live netlisting) or entirely batch mode.

The connectivity status controller in ARES handles the synchronisation of the board with the schematic. By default, you can find the connectivity status at the bottom of the layout module beside the DRC checker and will be in one of four states at any time.

No Netlist

This is essentially the disabled state and will be shown either when:

  • There are no connections in the schematic.
  • You have cleared the netlist (Tools Menu - Clear Netlist) manually and live netlisting is switched off.

Locked

The locked state is shown only when live netlisting is switched off and the schematic has changes which have not been applied to the PCB. In this state editing of the layout is disabled.

Clicking on the lock icon will apply the current state of the schematic to the layout and the layout will be unlocked for editing. If you have made changes to the schematic that require removal of parts from the layout then you will immediately enter the changes pending state (see below).

If you really need to make a layout change while it is locked then clear the netlist from the Tools menu (return to the no netlist state), make the changes and turn netlisting back on. This shouldn't happen but it is possible.

Changes Pending

This state is shown when the current schematic information has been passed to the layout and there are items which need your confirmation.

You will see this wherever a schematic change involves the removal of object(s) from the layout. The parts and/or tracks in question will dim to illustrate that they are no longer valid and you then have two choices:

  • Click on the changes pending button to confirm the changes. Dimmed objects will disappear and the schematic and layout will be back in sync.
  • Revert the changes on the schematic either manually or via the undo button. Dimmed objects will be re-instated and the schematic and layout will be back in sync

It is worth emphasising that a dimmed object is deemed not present on the board for all but visual purposes. They serve to show the user the effect of committing changes on the schematic and as a placeholder should the user decide to revert changes on the schematic.

If you find that the dimmed devices are hard to see, you can change the colour of the dimming in the Edit Layer colours/Visibility dialogue form in the View menu.

Netlist Errors

It is not possible to run a live netlist with errors as the system requires that your netlist is valid. You therefore need to resolve netlist errors as they occur.

If you are working with live netlisting switched off you will need to resolve netlist errors at the point you unlock ARES.

Netlist errors will appear in a separate tab at the point the netlist is transferred from schematic to layout. For example, if you have unconnected power rails you will get netlist errors along the lines of the following:

You would then resolve these errors by connecting the power supplies in the Power Rail Configuration dialogue form.

CRC Display

You will see this state whenever a netlist is loaded and the schematic and the layout are in sync. In other words, most of the time! The display will change to indicate the number of missing connections on the layout based on the schematic wiring.

Clicking on the widget will launch a textual list of the missing connections and you can navigate to a connection by double clicking on its entry in the list.

Working with ISIS and ARES

In normal operation you will have a schematic design in ISIS to associate with the layout in ARES. The interaction between the modules is largely intuitive but is detailed in the ISIS reference manual. Practical examples also exist in the tutorial documentation.

See Also:

Design Iteration (ISIS Reference Manual)

Netlists and Design Changes (ARES Tutorial)

The Bridge Style and Joining Nets

It is sometimes desired to join nets at a particular point (or points) on the layout - for example, where you have an analog and digital ground and you want to keep the digital return currents off the analog net. ARES allows you to do this by creating and using a trace style called the Bridge Style. Simply drag out a track from a pad on net A to a pad on net B using the bridge style.

By necessity the bridge style ignores connectivity and DRC conditions (it is after all explicitly used to connect two nets!). It is therefore entirely at the designers discretion as and when to use this – the software will not warn you if you make a mistake when using this style.

If the Bridge style does not appear in the parts bin when Trace Mode is selected you can easily create a trace style (Edit Menu – New Trace Style) and call it bridge.

Problems with Pin Numbers

As the netlist is loaded, ARES pulls in the specified package for each component and then attempts to match the pin numbers used for that component in the netlist against the pin numbering in the library-package. If the netlist references a pin number that does not appear in the library package then it displays an error message box and you must click OK to acknowledge. Problems in this area usually arise from one of the following causes:

  • Specifying the wrong package - e.g. a bipolar transistor outline for a regulator.
  • Failing to manually number pads which require non numeric 'numbers'. A typical example might be a DIN connector which has pin numbers like A1, A2 etc. Remember that by default, ARES always numbers the pads in the order you placed them.
  • Leaving spaces on the ends of ISIS device pin names/numbers or in ARES pin numbers. This can be checked by editing the relevant object and examining closely the state of the baseline of the Data Entry Field on which the text sits. If there are any gaps in it, these designate the presence of spaces.

If you use the Packaging Tool in ISIS when creating new library parts, you should avoid any of the above problems.

See Also:

Visual Packaging Tool (ISIS Reference Manual)

Packaging Considerations

At some point during the design process, it is necessary to specify the library-package to be used for each component. With the ISIS/ARES system, this can be done:

  • At the ISIS end by storing the package name in the PACKAGE property. For pre-supplied library parts this is generally done for you, although you can change the footprint if required. For parts you create yourself, you need to add a packaging manually - normally via the Visual Packaging Tool.
  • At the ARES end as you place the part.

In the latter case, parts without a specified package will appear in the object selector in ARES in exactly the same way as those with footprints. When you then try to place the part in ARES you will then be prompted to assign a footprint to the part.

See Also:

Device Libraries (ISIS Reference Manual).

Connectivity Highlight

Connectivity Highlight mode is selected by clicking left on the Connectivity Highlight icon. You can then:

  • Highlight/tag a group of pads, tracks and vias connected to a pad by clicking left on the pad.
  • Highlight all pads, tracks and vias connected to a net by selecting the required net from the Object Selector and then clicking left on the 'T' toggle.
  • Delete all tagged pads, tracks and vias by clicking left on the Delete icon. Combined with the above this provides the means to rip up all tracking associated with a given net.
  • Untag all pads/tracks/vias by clicking right at a point where there is no object or else by invoking the Redraw command.

Cross Probing

Proteus provides comprehensive cross-probing directly from within ISIS and ARES. Inside ARES, you can right click on a footprint to find the component on the schematic or right click on a track to tag the net in ISIS.

Conversely, in ISIS you can right click on a component or wire to tag the footprint or tracks in ARES.

Finally, you can use the Design Explorer module in cross-probing mode to tag both component and footprint in ISIS and ARES respectively.

If ARES is not synched with ISIS then the cross probing may give very strange results as the layout does not correctly reflect the schematic. Similarly, attempting to cross probe to a unplaced footprint will do nothing as the footprint is not present on the layout

See Also:

Cross Probing (ISIS Reference Manual)


RATSNEST FEATURES

Overview

The term Ratsnest is used to describe the pattern you get on the screen when the pin to pin connections specified in the netlist are shown as single straight lines rather than copper tracking. Once a netlist has been loaded and the components placed (or vice versa for that matter) the ratsnest gives a good visual impression of the complexity of the routing task that is before you or the autorouter. Furthermore, it gives an indication of the quality of component placement since the presence of lots of long ratsnest lines suggests that some components would be better placed closer together.

Automatic Ratsnest Re-calculation

ARES keeps the ratsnest up to date and optimized at all times, Add a component or delete a track and new ratsnest lines will appear. Make connections and ratsnest lines will disappear. It’s as simple as that.

The term ‘optimization’ refers to that fact that ARES always displays the ‘Minimum Spanning Tree’ for each net. This means that the displayed ratsnest lines always represent the shortest interconnection pattern between the pads.

From the Design Rule Manager (Net Class Tab) you can specify a different colour for ratsnest lines of a particular net class. For example, you may have green ratsnest lines for SIGNAL traces and blue ratsnest lines for POWER traces. This is particularly useful as these colours are maintained during part placement, allowing you to make sensible decisions about the best position and rotation for the footprint.

The ratsnest can also be turned off wholesale by using the checkbox on the Layers dialogue on the Display menu. Ratsnest lines related to a particular net class can also be turned on and off using the Design Rule Manager (Net Class Tab) command on the Technology menu.

Dynamic Ratsnest

The ratsnest in ARES is intelligent and designed to help you quickly and easily manually place routes. When you initiate manual route placement on a netlisted design the ratsnest will change to indicate the nearest termination point (said point being highlighted for additional emphasis) to the current location of the mouse. Further, a ‘shadow’ trace will appear over the area that has already been tracked to indicate the layer and position of the area already tracked. The termination point and ratsnest indicator will update in real time as you move providing you with constant feedback on route termination.

Force Vectors

Force vectors are provided as a further aid to component placement. They appear as yellow arrows which point from the centre of each component to the point where it’s ratsnest length (as defined by its current ratsnest lines) would be shortest. Another way of thinking about them is to consider each ratsnest line as a rubber band. The force vector then points to the place where the component would move to if released (strictly speaking this would also depend on the elastic linearity of the rubber bands, but we won’t get into that - it’s a good analogy!)

One oddity that can arise is that if you move the component to the position marked by the tip of its force vector, the ratsnest itself may change because a better minimum spanning tree may then be found. This can mean that the force vector then points to somewhere slightly different. We do not regard this as solvable; most PCB packages do not re-optimize the ratsnest after each edit, so such effects would not be so obvious - but they are still there.

The force vectors can be turned off by using the checkbox on the Display Settings dialogue from the View menu > Edit Layer Colours / Visibility; this setting is persistent across ARES settings

Ratsnest Mode

Ratsnest mode is selected by clicking left on the Ratsnest icon. You can then

  • Specify connections manually - if you are working without a schematic but still wish to use the auto-router.
  • Perform pin and gate-swaps (where legal) by dragging tagged ratsnest lines from one pad to another.
  • Tag a connection by pointing at it and clicking right.
  • Tag all the connections for one net by selecting the net in the Object Selector and clicking left on the 'T' toggle.

In conjunction with the autorouter's ability to route all, tagged or untagged connections, ratsnest mode gives you the means to autoroute the board selectively.

ARES supports manual ratsnest entry in much the same way as you would manually route a track (with the ratsnest icon selected). You can then use the autorouter normally. Note however, that this is a less than ideal way to use the software and where possible boards should always be netlisted from ISIS or another suitable schematic package.

Manual Ratsnest Entry

If you are working without a schematic, it is possible to enter ratsnest connections manually. Connections are specified by clicking left the pads to be interconnected. ARES will automatically create net-names for connections specified in this way.

Note that where component pads are on single layers, you must use the layer selector to select the correct layer for each pad. If a ratsnest line must change layer, then you can press the SPACE bar to toggle between top and bottom whilst placing the ratsnest line.

This is not a recommended mode of working as many features - particularly power planes and design rule management - require netlist information and such functionality will not be available without a schematic netlist.


PINSWAP & GATESWAP

Overview

When used in conjunction with ISIS, ARES supports pin-swap/gate-swap changes to the connectivity whilst the layout is being routed. This means that you can choose to interchange the wiring to like pins, and/or interchange the use of like elements of multi-element parts. A full discussion of how to prepare your library parts to exploit this feature is given in the ISIS manual, but from the ARES side there are two ways of using this feature.

See Also:

Pin Swap / Gate Swap (ISIS Reference Manual)

GateSwapping Components on the Schematic (ISIS Reference Manual)

Manual Pin-Swap/Gate-Swap

To perform a manual pin or gate swap

  1. Select Ratsnest icon.
  2. Click right on the source pin. For a gate-swap, this can be any member of the gate. The ratsnest lines connected to the pin will highlight. In addition, legal destination pins will also highlight.
  3. Hold down the left mouse button and drag the ratsnest lines to the required destination pin.
  4. Release the left button. ARES will make the change, updating the ratsnest and force vectors as appropriate. In the case of a gate-swap, ARES will move other ratsnest lines automatically.

It is possible to combine a pin-swap and a gate-swap in one operation - for example, swapping input A gate 1 (pin 1) with input B gate 2 (pin 5) on a 7400 will do just this.

Pin-swaps and Gate-swaps constitute changes to the connectivity of your design. ARES uses the pin-swap and gate-swap data specified in the ISIS libraries to decide what is, and is not, a valid swap. If there are errors in this data, then ARES may well suggest illegal swaps. We will not, under any circumstances, be held liable for any costs incurred or losses arising as result of such mishaps, whether the error be in your library parts or ours or in the software itself. We strongly recommend that you check that the swaps you make are really legal, and that you prototype your PCB prior to the manufacture of large quantities.

Automatic Pin-Swap/Gate-Swap

In the case of a board with a large number of possible gate-swaps (the SHIFTPCB sample is a spectacular example) in can be very hard to find the best arrangement. For these cases we have provided an automatic gate-swap optimizer.

To perform automatic gate swap optimization

  1. Invoke the Gate-swap Optimizer command from the Tools menu.
  2. ARES will make repeated passes trying the current set of possible swaps. The process repeats until no reduction in ratsnest length is achieved.

You will need to have a PCB Design Level 2 or higher to access this feature.

The Gate-Swap Optimizer relies entirely on the gate-swap data specified in the ISIS component libraries to decide what is, and is not, a valid swap. If there are errors in this data, then the swap-optimizer is likely to make erroneous changes to the connectivity of your design. We will not, under any circumstances, be held liable for any costs incurred or losses arising as result of such mishaps, whether the error be in your library parts or ours or in the software itself. We strongly recommend that this command be used only if you are going to prototype your PCB prior to manufacture.

Synchronisation with the Schematic

Whether manual or automatic swaps are to be performed, it is a requirement that the changes can be reflected or ‘back-annotated’ into the schematic. This will happen automatically provided that your schematic and layout are in synch.

If the layout has not been synched with the schematic the gateswap and pinswap operations will fail as the changes cannot be safely passed back to the schematic.

Further discussion of pin-swap/gate-swap is appears in the chapter entitled ISIS and ARES in the ISIS manual.

PINSWAP and Netlist Errors

You may occasionally see PINSWAP errors in the netlist. This happens when you have defined swappable pins in two places for one part, namely in the component as a property and in the packaging pinout. This is not resolvable by the netlist and the solution is to remove the ambiguity as follows:

  1. Remove the PINSWAP property from the schematic component. This is largely enabled for legacy purposes; swappable pins should be defined via the packaging tool.

  2. Add the swappable pins back in the packaging(s) via the packaging tool.

  3. Accept the update all devices dialogue to reflect changes across the design.


Routing Classes

NET CLASSES

Overview

In Proteus a net class defines everything about how the nets assigned to it are to be routed. This information includes:

  • The trace and via styles to use.
  • The via type to use (normal, buried or blind).
  • Assorted controls for the auto router.

The beauty of encapsulating all these properties in a single entity and then assigning nets to it as opposed to assigning the properties separately to each net is that it greatly reduces the amount of information that need be entered on the schematic.

Net Classes and the Netlist

The assignment of a net class is made in the schematicv by placing a wire label on a wire connection.

To create and configure a net class on the Schematic

1) Right click on the wire and select Place Wire Label from the resulting context menu.

2) Switch to the Net Class tab and click the new button to create a new net class.

3) Enter a name for the net class and then define the routing styles, via type and ratsnest display on the dialogue form. For multi-layer boards you can specify different track styles for internal and external layers of the PCB

4) Click the OK button to commit.

While it is necessary to define the net class on the schematic you can, if you prefer, leave the configuration of the net class (trace widths etc.) until you are ready to lay out the board. The same options are available from the net class tab of the Design Rule Manager (Technology Menu) in the PCB Layout module.

See Also:

Routing Classes (Schematic Reference Manual)

Net Classes and Design Rules

Net Classes are extremely important in setting Design Rules for your layout. Once you have named a net class on the schematic and netlisted to the PCB module this net class becomes available as an option in the Design Rule Manager. This in turn allows you to control clearances between pads and traces for that net class by creating additional rules as required.

Since you can create as many net classes as you want it follows that you have the flexibility to control clearances on the PCB in as granular a way as is needed for you project.

See Also:

Setting Design Rules

The Design Rule Hierarchy

Design Rules and Net Classes (Tutorial)

Special Net Class Names

The most common reason for needing different net classes is to distinguish power connections from signal connections in order that the power routes can be made out of thicker tracking. Also, especially when using the autorouter it is often an idea if memory bus connections are given special treatment as they really need to be routed in an orderly, regular fashion.

In order to help with achieving the above distinctions, the net class names POWER, BUS and SIGNAL are given special meaning and certain forms of net name will automatically be assigned to these net classes.

  • The net names GND and VCC default to the POWER net class unless they are explicitly assigned to a different one in the netlist.
  • Net names of the form D[0] (it is the square brackets that are important) default to the BUS net class. This is now somewhat obsolete (at least as far as ISIS is concerned) since you can place a bus label such as CLASS=BUS directly on a bus segment. Nevertheless, this syntax may be of use with other schematics packages which do not have net properties.
  • All other net names default to the SIGNAL net class.

This scheme will enable many boards to be handled without need to explicitly specify net classes on the schematic or in the netlist.

Editing a Net Class

Net Classes are created automatically by the Netlist Loader as their names are encountered. However, you will normally then need to edit them in order to set the various fields to whatever you require.

Net Classes may be edited using the Design Rule Manager on the Technology menu.


BACK-ANNOTATION

Overview

Back annotation is the process whereby changes to the component annotation on the PCB can be fed back into the schematic. This would normally be done if it was felt that a particular order of annotation on the PCB would aid the production department in making the board. In fact, the most natural order for this purpose is if placement path for placing the components in successive order is a minimum.

Manual Re-Annotation

It is perfectly possible to re-annotate the board manually by editing each component reference label as required. Since Proteus works with a common database an annotation change in ARES will simply reflect back to the component in ISIS.

If live netlisting is enabled this will work seamlessly and without any further action on your part. If live netlisting is turned off however, the act of re-annotating in ARES will lock the layout as it involves a netlist change which - in this mode - you must manually confirm.

Some caution is required that you do not end up with two parts with the same reference. While this will not be electrically incorrect it will make population of the PCB very confusing. The software will warn you of such a condition when you export for manufacture in the pre-production checker.

See Also:

Live Netlisting

Batch Netlisting

Pre-Production Checker

Automatic Re-Annotation

Should your sole aim be to renumber the components to give a geometrically sensible placement order, then the Component Re-Annotator command on the Tools menu will do this for you.

Global annotation from the PCB (Tools Menu - Automatic Annotator) provides options for both sides of the board and directional control over the annotation process.

The effects of running the command are identical to manual annotation, namely that it will simply happen with live netlisting enabled and that it will switch ARES into a locked state with live netlisting disabled.

The option for sheet offsets on the dialogue refers to the initial annotation offset available for sheets on the schematic. Some users prefer that each logical block (sheet) on the schematic has it's own annotation base. If this is set up on the schematic then selecting this option will honour those offsets during the annotation pass on the layout.

Obviously, the position of parts on a layout is completely arbitrary and any attempt to sensibly re-annotate the board relies on heuristics. While generally a global re-annotate will perform sensibly it does very much depend on the individual board topology and you may need to make some manual adjustments.


PROJECT CLIPS

Overview

Project clips (or snippets) provide a formal way to reuse parts of an existing project in future work. The basic idea is simple; select an area of schematic and/or an area of layout and then export them to disk for import into future projects. There are however some important rules and limitations which are explained below.

Project Clips Practical Examples

See Also:

Duplication in a Project with Replicate.

Schematic and Layout Project Clip

A schematic and layout project clip is the normal scenario. You have a section of circuitry and a corresponding section of layout that you either want several copies of in a board and/or you want to re-use in future projects.

Creating

To create a schematic and layout project clip

  1. Organise your schematic so that everything you want in the project clip is on a single sheet. Drag a selection box around the circuitry in ISIS.

  2. The layout selection in ARES must precisely match the schematic selection in ISIS. If you are creating the project clip from a completed or existing project this will almost certainly require some surgery so save your project under a temporary name before you begin! Use the selection filter or simply move and delete as appropriate until you can drag a selection box around the parts and tracking that you want. When you are finished drag a selection box around the area of PCB.

  3. Right click inside the selection box and select the Export Project Clip command from the context menu. By default, this will save the project clip (*.PDSCLIP) into the SNIPPETS directory of your Proteus installation.

This is an operation involving a selection box on the schematic and a second selection box on the layout. If your monitor is big enough it's useful to split the layout tab into a separate frame so that you can see both at the same time.

You need to manually arrange the selection box on the layout as, apart from footprints, we cannot make decisions on which objects are included. Your selection box therefore tells us whether enclosed tracking, 2D Graphics, enclosed zones, etc. should form part of the project clip.

Rules for Project Clips

Importing

To import and place a schematic and layout project clip

  1. Start from the schematic module (ISIS) and go to file menu and insert project clip command.

  2. Place the project clip on the schematic.

  3. The corresponding project clip will then appear in the parts bin in ARES, denoted by a scissors icon at the right hand side.

  4. Click on any component part of the project clip and place on the layout.

Schematic Only Project Clips

A schematic only project clip is an area of schematic design that you wish to re-use in future schematics but for which there is no accompanying board layout in place. For example, an Arduino shield may be created for simulation purposes and re-used in several projects.

Creating

To create a schematic only project clip

  1. Organise your schematic so that everything you want in the project clip is on a single sheet. Drag a selection box around the circuitry in ISIS.

  2. Right click inside the selection box and select the Export Project Clip command from the context menu. By default, this will save the project clip (*.PDSCLIP) into the SNIPPETS directory of your Proteus installation.

Importing

To import a schematic only project clip

  1. Start from the schematic module (ISIS) and go to file menu and insert project clip command.

  2. Place the project clip on the schematic.

A schematic only project clip replaces the old Proteus 7.xx Section file technology. You can import existing section files via the Import Project Clip command and change the file type selector to section files. You should then create a project clip from the imported data.

Layout Only Project Clip

A layout only project clip is an area of PCB layout that you wish to re-use in future boards that does not have a direct schematic equivalent. This is both extremely unusual and potentially unsafe (annotation clashes) but is included here for completeness.

Creating

To create a layout only project clip

  1. Organise your layout so that everything you want in the project clip is on a single sheet. Drag a selection box around the circuitry in ARES and use the selection filter to define selected object types.
  2. Right click inside the selection box and select the Export Project Clip command from the context menu. By default, this will save the project clip (*.PDSCLIP) into the SNIPPETS directory of your Proteus installation.

Importing

To import a layout only project clip

  1. Start from the layout module (ARES), go to file menu and insert project clip command.
  2. Place the project clip on the layout.

Importing a PCB only project clip (or indeed copy and pasting parts of a layout) when you have a schematic and live netlisting is on can have unintended consequences. If no duplicates exist, the annotation of the clip is preserved but the footprints will bind to schematic components with that annotation which may well not be what you want to do. If you are unsure then you should first clear the netlist (tools menu in ARES), then import the project clip and fix up the annotation as desired and finally turn live netlisting back on to sync.

A layout only project clip replaces the old Proteus 7.xx Region file technology. You can import existing region files via the Import Project Clip command and change the file type selector to region files. You should then create a project clip from the imported data.

Rules for Project Clips

  • A schematic and layout project clip requires that exactly the same parts are selected in both the schematic and the layout. You cannot have a selection in ARES that contains components with different part references than those selected in ISIS, nor can you have parts highlighted in ISIS which are not highlighted in ARES.
  • A project clip on the schematic will operate only on the current sheet. Do not create a schematic snippet that contains a sub-circuit. Snippets do not propagate down through the schematic hierarchy and the sub-circuit contents will not be saved/imported.
  • A schematic and layout project clip must first be imported into the schematic. This will initialise the parts such that placement on the layout is correct and there are no annotation clashes with other circuitry.
  • If a power plane is not completely enclosed by the selection on the layout it will not be included in the project clip. The assumption is that the clip will be placed on a board where an equivalent plane is in use. If not, then clearly there will be missing connections on import.
  • Once placed on the PCB layout the project clip is no longer a single entity. Each object (component, track, via, etc.) is moved or edited independently.
  • If you import a project clip into a schematic sub-circuit it will replicate across circuits with the same name that are already placed. Subsequently adding a sub-circuit and giving it the same circuit name will not however automatically create a snippet instance. You should either import multiple snippets onto a root sheet or make very sure that you have all your sub-circuits in place before importing the snippet to one of them.


AUTOPLACEMENT

Introduction

In addition to auto-routing, Proteus PCB Layout includes support for autoplacement. At it's simplest level you can simply run the auto-placement command and let it dump the components on whichever side of the PCB you specify. In more typical use you would create groups of components in Design Explorer (e.g. POWERSUPPLY, FILTER, USBCONN) and then place those groups inside placement rooms on the layout.

In either case, it is important to think of auto-placement as a timesaver. It is intended to put all of your parts on the correct side and region of the PCB; in no way is it designed to put parts in their final position on the board.

Auto-placement is part of the advanced feature set and requires PCB Level 2 or higher.


USING THE AUTOPLACER

Overview

In operation, the placer requires only that the board outline be defined (by placing lines and arcs on the Edge layer) and that a netlist be loaded to specify the components to be placed. A more detailed sequence of events is set out below:

For anything complex you can reasonably expect the auto-placement algorithm to take several minutes. You'll find current progress on the status bar.

Simple Auto-placement

Simple auto-placement is pretty much a fully automated process. It will result on all of the selected parts being placed inside the board edge on either top or bottom. The user has no further control over placement and it is therefore serves only as a quick way to get the parts down on the PCB. The process is detailed below:

To autoplace on the PCB

  1. After completing the schematic, draw a board outline of the correct dimensions using the 2D graphics tools on the board Edge layer. Ensure that the boundary forms a closed polygon. The best way to do this is to use a Path object.

You need to have live netlist turned on (from the Tools menu on the layout) in order to autoplace.

  1. Place any components which are immovable on the board. Hand placed components are viewed as fixed, these will be treated as obstacles by the auto-placer.
  2. Select Auto-Placer command from the Tools menu in ARES and adjust the various options as you see fit. In particular, note the checkbox that allows you to place on bottom side.

  3. Select those components from the list which you wish to be placed automatically.

  4. Click OK.
  5. Once you have finished with the auto-placer, manually place any remaining components and start routing.

Groups and Placement Rooms

A group in terms of autoplacement is a set of components that you want to be placed next to each other. You assign the group to the component either on the schematic or in the design explorer.

Assigning Group on Schematic

1) Select the parts on the schematic.

2) Invoke the Property Assignment Tool (keyboard shortcut is 'A' ).

3) Make up a group name and assign it to property GROUP.

Making all selected parts part of the USBENGINE group with Property Assignment Tool..

Individual components can be added to a group by editing the component properties and typing {GROUP=NAMEOFGROUP} into the 'Other Properties' field. Curly brackets hide the property on the schematic.

Assigning Group in Design Explorer

1) Launch Design Explorer from the main toolbar.

2) Type a new group name beside a part to create a new group or select from the combo to add the part to an existing group and hit Enter.

Assigning a CAP to the new PWRSUPPLY group by typing the group name in Design Explorer.

Placement Rooms

A placement room is a graphic object drawn on the layout that denotes an area for part placement. You can have multiple placement rooms and they can apply to either side of the board. This allows you to set out a floorplan on the PCB indicating where you want parts to be placed.

Laying out a floorplan with placement rooms assigned to groups

To lay out a placement room

1) Select placement room mode from the graphics toolbar and drag out a rectangle of the correct size and in the correct place.

2) If one is already placed, right click on the room border and select Edit from the resulting context menu.

3) Change the placement to Group, specify the group name and the side of the board for placement.

Click on the question mark on the dialogue form for more detailed help on the various options.

Placing Groups inside Placement Rooms

Having set up the groups and the floorplan you can run the auto-placer and it will put the correct parts in the correct room for you. Alternatively, you can select a group from the component filter and then right click to place inside it's room.


THE AUTOPLACER DIALOGUE

Overview

The auto-placer is highly configurable and as a result the dialogue form may at first appear somewhat daunting. However, it will operate quite happily with the default settings for most purposes. The function of the various fields is discussed below.

The Auto-placer dialogue form

The Component Selector

The left hand pane show a list of all the components still to be placed, when the dialog form is first displayed the components are listed in alphabetical order with all the components selected for placement.

The function of the All and None buttons should be fairly obvious; the Schedule requires a little more explanation. By the default, the components are presented in alphanumeric order but by pressing the Schedule button they are then presented in the order that they will be placed by the auto-placer. In this case, components not-selected for placement always appear at the bottom of the list.

Rules

The Placement Grid defines the step size used by the auto-placer when trying to find a position for each component. This should always be set to a multiple of the grid size you are going to use for auto-routing. Values other than 100th, 50th or 25th would be highly unusual.

The Edge Boundary defines the minimum distance to be allowed between any component and the edge of the board as drawn on the edge layer.

The time to complete placement will change exponentially as you decrease the placement grid. If at all possible, try to keep the placement grid at 50th or higher.

Trial Placements and Cost Weightings

Auto-placement is achieved by trying the next component at various positions on the board in an attempt to minimise a number of key factors. The relative importance of these factors is set by you, the user, by moving the sliders to the right (more important) or left (less important) for each of the six categories.

Ratsnest Length

Arguably the most important weighting factor in terms of routability, this assigns importance to the minimisation of the length of inter-connectivity of components before routing. Note however that in our experience this should be balanced with some knowledge of the number of ratsnest crossings. A board with short total ratsnest length and a large number of crossings can often be unroutable.

Ratsnest Crossings

This weighting defines the importance of minimising the number of ratsnest lines which cross. As a component is moved around the board the ratsnest length and number of crossing changes, both of these factors will affect the overall routability of the final placement. It is important to get a good balance between this and ratsnest length.

Congestion

Small components such as resistors and capacitors may be encouraged to avoid highly congested areas of the board by increasing the importance of the congestion weighting. Note that when a small component has been associated with another component via the GROUP property congestion is ignored for that component.

DIL Packages

Components which are allocated DIL packages are treated as a special case. It is seen as desirable to align DIL packages such that they all have the same orientation. To this end a number of controls on the dialogue are tailored to the placement of DIL packages. Preferred DIL rotation is by default horizontal but the shape of your board may dictate that vertically placed DIL packages make better use of the available space. Two further controls in the cost weightings group on the dialogue form define how heavily penalised a component will be if the package is placed with either 90 or 180 degree rotation from the default. If you are not concerned about the orientation of your DIL packages then set these costs to zero.

Alignment

A successful PCB layout is judged not only on routability but also on aesthetics. One key factor in whether a PCB looks right is whether components are aligned. This weighting factor stresses the importance of aligning component edges. Increased alignment can sometimes also aid routing since if like components are aligned then it follows that their pins are also aligned.

We recommend that you leave the options at default until you become familiar with the behaviour of the placer as it would be quite easy to make the placement results worse.

Options

Push & Shove

The auto-placer recognises two types of component, those initially placed by the user which are deemed to be fixed and immovable and those placed by the auto-placer which may or may not have been moved by the user. The later will be pushed and shoved around the board where possible in an attempt to best place the remaining components. This shuffling can become restrictive and counter-productive on boards where the pre-placed components are in the centre of the board. In such cases Push & Shove should be disabled.

Bottom Side

Run the auto-placer on the bottom (solder) side of the board. If you want to place on both sides you should set up placement rooms and define groups of parts to go in them.


OCCUPANCY DEFINITIONS

Overview

Each component that is placed on the board is treated as an obstacle for the remaining components to be placed. By default the area which is occupied by a component is assumed to be the smallest box which contains all silk screen graphics and component pins. Any two such boxes may not touch or overlap.

It is quite feasible that you will wish to modify the area taken by an object such that, for example, a DIL package has additional space on the sides occupied by the pins, or that a connector has increased occupancy on one side only. To achieve this ARES provides an Occupancy layer onto which 2D graphics may be drawn in much the same way as silk screen graphics are added.

Occupancy graphics are not normally seen but may be examined and edited by first decomposing the package, amending or adding graphics as necessary and then invoking the Make Package command from the Tools menu.

To add an occupancy definition to a package

  1. Place a copy of the package on the layout.

  2. Tag it and then invoke the Decompose command on the Edit menu.

  3. Select the Occupancy layer in the Layer Selector.

  4. Place either a box or a circle to define the occupancy.

  5. Tag all the elements of the package.

  6. Use the Make Package command to store your handiwork back the library.

The current implementation does not support the use of path objects in the context. Multiple boxes and circles are allowed at present, but this may be dropped when we code support for path objects as testing for multiple objects carries a speed penalty.

Many of the newer library parts and in particular the IPC-7351 standard footprint libraries come pre-supplied with occupancy definitions as per the IPC standards.


AUTO-PLACEMENT

Limitations

The auto-placer is another very useful tool in the armoury provided by PROTEUS but there are a number of limitations of which you should be aware:

  • Whilst the auto-placer can operate on boards on which some components have been pre-placed, our experience is that the more of these there are, the less well it performs. If possible, it is better to let in place everything and then move things about afterwards. Pre-placing components in the middle of the board will cripple its performance because this interferes with its ability to shuffle the components about as placement proceeds. If you must have pre-placed components in the middle you may find it does a little better if the Push & Shove option is disabled but in general it will do badly.
  • Boards which are decidedly non-rectangular also interfere with the Push & Shove mechanism and again the placer will perform badly in such cases. Boards with small cut-outs etc. should not present a problem, however.


INTRODUCTION

Overview

The ARES auto router is the one of the most powerful tools in the Proteus system and is capable of saving you an enormous amount of time and effort. The two principle technologies applied in the router are discussed below.

Shape Based Auto Routing

The ARES Router features cutting-edge shape based algorithms for Shape-Based Autorouting. By contrast to traditional gridded maze autorouters, a shape-based approach allows for more efficient use of routing area and is more suited to handle complex design rules requirements of high density PCB designs.

Conflict Reduction Algorithms

In addition to its shape-based architecture, the ARES router places routes with conflicts and then uses a multi-pass cost-based conflict reduction algorithm to find a routing solution adapting to the natural flow of the nets. On the initial passes the router uses a relatively low cost for accepting a routing path solution with crossing and/or clearance conflicts. Costing are then slowly increased on subsequent passes until all conflicts are removed. By working in this way (allowing nets to be routed with conflicts, autorouted wires will initially start with an ideal path and the final routing solution will closely mimic manual routing in terms of optimum wire length and number of vias. This adaptive routing technology is a proven approach to systematically reach high completion rates on complex high density PCB Designs.

In addition to the material below you may well find it useful to refer to the practical examples in the tutorial document.

See Also:

Basic Auto-routing (Tutorial)

Advanced Auto-routing (Tutorial)

Modes of Operation

Despite the considerable internal complexity of the router, it is extremely easy to use in practise. There are three internal modes of operation, which can be thought of in simple terms as fully automated, scriptable and interactive. A fourth option exists allowing users with an installed and licensed copy of the ELECTRA router to directly invoke this application. All of these modes are discussed in more detail in subsequent topics.

The Auto-Router and Design Rules

The ARES auto-router is truly world class and can save you valuable hours of development time. However, it can only route with the guidelines you provide it and it stands to reason therefore that the more information you give the better the routing solution. Fortunately, ARES also includes a comprehensive and flexible design rule system where you can specify a series of board constraints and clearances, trace widths and via styles for named net classes (e.g power, signal) and even the layers on which you wish given net classes to be routed on. All of these rules can be created and edited from the Design Rule Manager on the Technology Menu and will be honoured by ARES when routing the board.

Whilst ARES will quite happily route a board with the pre-supplied global design rule we strongly recommend you make use of the Design Rule Manager to specify constraints and information relevant to your particular project.

It is also extremely important to manage the placement of power planes onto designated plane layers. The auto-router will place vias to connect through to such planes whereas it will ignore power planes on signal layers for this purpose.

When working with Design Rooms the auto-router can only accept rectangular room definitions. If you need a polygonal design rule area you can create in Proteus but you will not then be able to auto-route the board.

See Also:

Design Rules and Net Classes (Tutorial)

Routing Classes

Plane Layers

Live Status Reporting

Once you have specified the required design constraints and invoked the autorouter the status bar at the bottom of the editing window in ARES will report on the current routing percentage completed and provide additional information on routing behaviour. Specifically, the type of routing pass in progress, the current pass, the number of conflicts and the percentage completed.


Dialogue Form

AUTOROUTER DIALOGUE FORM

Overview

All autorouting operations – regardless of the mode of operation - start by invoking the Autorouter command on the Tools Menu in ARES. This topic discusses the various configurations on the dialogue form.

Note that the despite it’s seeming complexity, the basic operation of the router is extremely simple. Many configuration options are provided for additional flexibility and the default values are sufficient for all but the most complex of boards. Please see the examples section for more practical usage guidelines or working with the autorouter interactively for more information on this mode

Execution Modes

The main section of the dialogue form allows you to choose one of four execution modes; Automated Routing, Scripted Routing (run a script file), interactive routing (type routing commands) or, if you have a copy of ELECTRA, to launch the ELECTRA Autorouter and route the board externally. Some of these radio buttons may be disabled based on the following rules:

  • If you have a PCB Design Starter Kit, a PCB Design Level 1 or a PCB Design Level 1+ then the Scripted Routing mode and the Interactive Routing Mode will be disabled.
  • If you do not have a license for the ELECTRA autorouter or ELECTRA is not installed on your computer then the ELECTRA Mode will be disabled.

Several additional options are available in the fully automated mode. Whilst in most cases the default settings will suffice these options provide extra flexibility for more complex or densely packed PCB’s.

Fanout Passes

These passes will autoroute small escape wires with a via from SMD pads, thereby allowing easier connection to the pads during the main routing passes.

Routing Passes

The number of principle routing passes. There is only marginal benefit in increasing this beyond 50; for complicated or densely packed boards we recommend increasing the repeat phases rather than the number of routing passes.

Cleaning Passes

Cleaning passes will basically rip-up and reroute each net with high via cost and the highest cost for making clearance and crossing violation. The default value is adequate for almost all boards.

Repeat Phases

This allows you to specify the number of times the routing passes and cleaning passes will repeat. The ARES Autorouter is an adaptive shape based router so repeating the route/clean passes will typically help achieve higher completion. The default value is adequate for most boards but increasing the repeat value will have benefit in more complex or densely packed layouts.

Filter Passes

The filter pass will be performed after the router has repeated the route/clean passes the specified number of times. This will simply rip any tracks that have conflicts at the time of invocation. The default value for this is fine for almost all layouts.

Recorner Pass

This pass is performed last and changes 90 degree wire corners to 135 degrees to reduce track length.

Routing Rules

These options provide additional guidelines to the router and indicate the default behaviour for the routing algorithms. As with the scheduling options detailed above, the default values will suffice for the vast majority of boards.

Wire Grid

Specify the default wire routing grid. This advises the router as to the preferred grid for placing tracks but does not actually constrain it to routing on that grid.

Via Grid

Specify the default via routing grid. This tells the router the preferred grid for placing vias but does not constrain it to routing on that grid.

Allow Off Grid Routing?

This option, defaulted to on, determines whether the router is constrained to routing on grid (grid based routing) or is able to route off grid when necessary. We strongly advise leaving this option enabled as disabling this option will adversely affect router performance in most cases.

Conflict Handling

The ARES router works on a costing basis so it first places all tracks according to their ‘ideal’ position and then increases the costing of illegal tracks until there are no conflicts remaining. This means that in the unlikely event that the router does not achieve completion there will be illegal tracks placed on the boards and these options allow you to configure how you would like ARES to handle such tracks.

Treat Conflicts as Missings

In this case when the router is aborted or stops any tracks that cross other tracks or are deemed illegal are ripped from the layout and the connection will revert to a ratsnest line in ARES.

Treat Conflicts as Illegal Tracks

When selected, all conflicts will be left as illegal tracks (showing design rule violations and flashing in yellow). Note however, that is possible (particularly if the user aborts the router) that you can have a very large numbers of conflicts early on during the routing process and trying to sort out such a tangle in ARES is more or less impossible.

Command Buttons

The Begin Routing button is the button that invokes the router and commences the auto-routing of the board. Two additional buttons for exporting a design file and importing a session file are provided for users with the SPECCTRA™ Autorouter, whilst the Reset to Defaults button will reset all the configurable options to their initial values at installation. Finally, the Cancel button can be used to return to the ARES Editor without invoking the autorouter.


BASIC OPERATION

Overview

While the ARES Router is both complex and flexible it is also extremely easy to use. In this topic we look at some basic examples of how we might invoke the router in the different execution modes. Please see the appropriate sections of the documentation if you need more information on controlling router operation

To invoke the router in fully automated mode

  1. Launch the Auto-Router Command from the Tools Menu in ARES.

  2. Select the Run Basic Schedule Automatically radio button as the Execution Mode.

  3. If desired, adjust the number of passes from the default values.

  4. Use the Begin Routing button to autoroute your board.

To invoke the router in scriptable mode

  1. Launch the Auto-Router Command from the Tools Menu in ARES.

  2. Select the Run Specified DO file Automatically radio button as the Execution Mode.

  3. Browse for a router script (DO File) via the Browse button or type the location directly into the Edit Field.
  4. Use the Begin Routing button to autoroute your board.

This option is only available with the advanced features set PCB Design Packages (PCB Design Level 2 and higher).

To invoke the router in interactive mode

  1. Launch the Auto-Router Command from the Tools Menu in ARES.

  2. Select the Enter Router Commands Interactively radio button as the Execution Mode.

  3. Use the Begin Routing button to autoroute your board.

  4. A command window will appear at the bottom of ARES allowing you to type routing commands either globally or based on selected areas of the board.

This option is only available with the advanced features set PCB Design Packages (PCB Design Level 2 and higher).

See Also:

Interactive Routing Examples

Auto-Router Command Reference

Routing Multiple Layer Boards

It is mainly the case when routing a 4 layer board that you will route on Top copper and Bottom Copper, and the two inner layers are set to be Plane layers. See Plane Layers for more information. However, there may be the case where you wish to route on an inner layer that is a signal layer. In order to do this you need to set the layers used in the Net Classes tab of the Design Rules Manager:

First, select the Net Class that you wish to set:

Then, select the layers that you wish the autorouter to use:

Each pair tells the autorouter to route to or from a specific layer.

You will need to set these pairs for each Net Class in the list

Each net class can involve up to 8 layers on which connections assigned to it will be routed by the autorouter. The (H) layer is for predominantly horizontal routes and the (V) layer for predominantly vertical routes. Single sided routing can be achieved by specifying the same layer for both H and V routes.

Priority

This is used by the autorouter - connections assigned to the highest priority (smallest number) net class will be routed first. Net Classes with the same priority will be routed simultaneously. This will probably result in the router spending much more time 'mapping', but may lead to higher completion rates than routing them in turn, especially on single sided boards.


CREATING ROUTING SCRIPTS

Overview

The ARES Router is capable of running a pre-supplied script and will schedule routing operations based on the commands in the script. This can be particularly useful if you find that a particular sequencing of commands helps to achieve completion or produces a better result and you want to use this sequence repeatedly for different projects. Finally, for very complex boards this method of execution is ideal where, for example, you wish to let the router find the best solution overnight or over a period of several hours.

Creating and Modifying Scripts

Labcenter provide a pre-supplied scripting file that, whilst basic, will successfully achieve completion on most standard PCB’s. The intention is that this file be copied and then modified or extended as required to suit the needs of your project(s).

The contents of the pre-supplied basic script are copied below:

#==================

# BASIC DO file

#==================

bus diagonal

fanout 5

route 20

clean 2

route 25 16

clean 2

filter 5

recorner diagonal

Note that comments can be entered by preceding the line with the hash character.

More information on each of the commands used can be found in the command reference.

Once you have adjusted the script as required simply save it on your computer, specify the execution mode and location of the script via the Autoroute command on the Tools menu and invoke the router. This procedure is outline in more detail in the basic operation topic.


Interactive Routing

INTERACTIVE AUTO-ROUTING

Overview

Working with the router in interactive mode maximises the flexibility you have over the routing process. It allows you to easily route parts of the board gives you full control over the order and priority of routing tasks. You do however need to have an understanding of the basic command set and of the different routing phases in order to maximise the use of this mode of operation. It is therefore most likely to be of use in more complex designs or for users comfortable with directing the flow of the router.

Interactive mode is only available to users with an advanced feature set version of ARES (PCB Design Level 2 or higher)

Once you have invoked the autorouter in interactive mode you will see that a command window is launched at the bottom of the ARES Editing Window. It is important to understand that at this point you are in autorouting mode and therefore that any attempt to change the layout will exit the routing mode before applying your commands. Similarly, if you switch modes (for example, to component or track mode) then you are implicitly leaving autorouting mode and ARES will therefore remove the command window accordingly.

Basically, when you have entered the interactive routing mode you can:

  • Type routing commands to control the autorouter.
  • Use the mouse to select an area or net which you wish to route.
  • Use the object selector to select a net.
  • Use the mouse or keyboard to navigate the layout in the normal way.

Other operations will cause the routing mode to exit before taking place.

Specifying Nets

By default, any commands you type in the command prompt will action on the entire board. For example, if you type ‘route 20’ then twenty routing passes will occur on the entire board. It is quite common however to wish to route a particular area of the board (e.g. around a small pitch SMT footprint) prior to the global routing process. You can do this in ARES simply by dragging a selection box around the area of the board that you wish to route.

Selecting an area to route

Having created the selection area you then have two options:

  1. Limit the selection only to nets entirely enclosed by the selection area.
  2. Extend the selection to all nets where a connection on that net is partially enclosed by the selection.

You can toggle between these two options via the track selection mode icon on the Selection Filter

Track selection mode

Alternatively, you may wish to limit the initial routing to affect only a specified net. You can do this by simply clicking the mouse on a pad on that net – this will highlight all of the ratsnest connections on that net and any subsequent routing commands will apply only to the selected objects.

Single net selection

If a selection exists the router commands will be limited to operating only on the selection. This means that, if you want to revert to routing globally, you need to click the mouse on an empty area of the layout to deselect all currently selected objects

Routing Phases

In interactive mode you drive the router by indicating what you want to route (via selection) and then typing commands to direct the routers progress. In order to successfully do the latter it will be useful to look at the three phases of a typical routing schedule.

Preparation

This is the first phase where commands are issued to handle particularly difficult routing objects. A good example here is the ‘fanout’ command that should be used before routing to make access to fine pitch SMT footprints easier.

Routing

This is obviously the main phase and we typically use both the ‘route’ and the ‘clean’ commands here. It is important to remember that the router is adaptive so if you don’t reach completion repeat the process – you are not doing the same thing again!

Tidy Up

Once we are finished with the routing phase we enter commands to tidy up the board. This is where we might use the ‘filter’ command if we didn’t reach completion and where we would use the ‘recorner’ command to minimise track lengths or avoid solder traps.

A good example of the type of command set that you would use for a typical routing exercise is that used in the standard pre-supplied script which you can also find here

Command Syntax and examples of usage can be found in the command reference.

Example: Routing in Interactive Mode

This example describes how you would typically route a board in interactive mode, assuming that you have configured design rules, layer sets and net classes through the Design Rule Manager.

To route a layout interactively

  1. Launch the router in interactive mode.

  2. The preparation phase consists of the bus command followed by the fanout command to provide access to fine pitch SMT parts.

  3. The initial routing phase then consists of the route command (single parameter for number of passes) followed by the clean command to tidy up.

  4. Subsequent routing phases consist of the route command (two parameters - number of passes and start pass) followed by the clean command to tidy up.

  5. Once we are finished routing the tidy up phase consists of the filter command (if we didn't achieve completion) and possibly the recorner command for solder trap avoidance.

The router is adaptive so re-using the same route commands in subsequent passes does not simply repeat the same routing process.

Example: Routing a Net on a Particular Layer

ARES provides a User Interface for this via the design rule manager (Technology menu) where you can specify the routing layers for any given net class. However, you can directly instruct the router to do this in interactive mode. The layers in ARES are identified for routing purposes as follows:

Layer Name | Designator | Layer Name | Designator
Top Copper | TOP | Inner 8 | I8
Inner 1 | I1 | Inner 9 | I9
Inner 2 | I2 | Inner 10 | I10
Inner 3 | I3 | Inner 11 | I11
Inner 4 | I4 | Inner 12 | I12
Inner 5 | I5 | Inner 13 | I13
Inner 6 | I6 | Inner 14 | I14
Inner 7 | I7 | Bottom Copper | BOT

To route a net on a particular layer

  1. Launch the router in Interactive Mode

  2. Tag the net (e.g. GND) by selecting it in the parts bin and then clicking on the 'T' button at the top.

  3. Use the cost command to forbid routing on one or more layers.

  4. Use the route command to route the net on the remaining layer.

  5. Use the cost command again with value -1 to reset to default.

Note that restricting the layers available for routing makes achieving completion much more difficult.

Example: Protecting existing tracking

To protect tracking when routing interactively.

  1. Launch the router in Interactive Mode
  2. Use the protect command with 'all wires' prior to routing.

  3. Use the unprotect command when you are finished.

The lock command can be used instead of the protect command if you want to prevent the router connecting to tracks already placed as well as prevent the tracks being moved/deleted.

Example: Controlling Fanout on SMT Chips

Fanouts are escape wires from SMT pads which then allow the router to make connections. Typically, the fanout is one of the first commands to be executed when routing but interactive mode gives you far more control over what happens in this phase.

To execute the default fanout

fanout 5

Fanout 5 where the vias are in side the IC

To force fanouts to be outside the IC

fanout 5 (direction out)

Now note that the vias are outside the IC

To allow via sharing on a fanout

fanout 5 (via_share on)

Note that C1 and X1 now share the same via

Example: Setting the Maximum Number of Vias for a Track

To specify a maximum of two vias to be used when routing the GND net.

  1. Launch the router in Interactive Mode
  2. Tag the net (e.g. GND) by selecting it in the parts bin and then clicking on the 'T' button at the top.
  3. Use the 'limit via 2' command to limit the number of vias

  4. Route the net.

  5. Reset to defaults by using -1 with the limit command.


COMMAND REFERENCE

The following is a description of the command set exposed to the user that will execute routing operations in ARES. These commands can be typed in directly when routing in interactive mode or used to construct a custom routing script when working in scriptable mode. Typically, you might only use the first six of these commands for interactive mode whereas you may well need to use some of the more advanced commands when in scripting modes. Each command includes a description of usage, the command syntax and an example.

The BUS Command

This command invokes a bus routing pass only on regular array of pins with collinear connections where the pins share a common X or Y coordinate. This is particularly effective on memory arrays. In this mode, the router will not generate conflicts, so rules must allow for sufficient space. By default traces are routed orthogonally, unless the diagonal option is specified. Typically, this command should be the first issued in a routing script.

Basic Syntax:

bus [diagonal]

Example:

bus diagonal

The FANOUT Command

This command autoroutes small escape wires with a via from SMD pads. Recommended for use at the start of routing where there are more than two signal layers. Not recommended for use with two layer boards as it will block routing spaces.

Typically, this command should be issued immediately after the bus command and prior to any route commands.

Basic Syntax:

fanout <number of passes>

Example:

fanout 5

The fanout direction can be also be set so that fanout vias are added inside SMD components and/or outside. Fanout can be limited by pin type, for example pins connected to power nets only.

Full Syntax:

fanout [<passes>]

[(direction[in_out|in|out])]

[(pin_share [on|off])] [(via_share [on|off])]

{[(pin_type [active|signal|power|unused|all|single])]}

[(max_len <positive_dimension>)]

Example: Depth for blind and buried vias

fanout (depth opposite 2) (share_len 500)

fanout 5 (pin_type signal) (via_share on)

Example: Fanout using a grid of 25

fanout [via_grid 25]

The ROUTE Command

This command tells the autorouter to perform a specified number of routing passes and is the basic command used when routing. Typically you would use this command iteratively with the clean command to acheive completion. The start_pass parameter should only be used on the second or subsequent routing phases and sets the initial costing of the first routing pass of that route set.

Basic Syntax:

route <number of passes>, <start pass>

Example:

route 20 (first routing phase)

route 20,16 (subsequent routing phases)

The CLEAN Command

The clean command will basically rip-up and reroute each net with high via cost and the highest cost for making clearance and crossing violation. This command is typically used iteratively with the route command perform some routing passes, clean, perform some more routing passes, clean again, etc. However, when full completion is reached the clean command can be used to minimise vias.

Basic Syntax:

clean <number of passes>

Example:

clean 2

The FILTER Command

At the end of a routing session you may end up with wires/vias in conflicts (crossing or too close to each other). The filter command will remove these conflicts by unrouting the minimum number of connections that are currently in conflict

Basic Syntax:

filter <number of passes>

Example:

filter 5

The RECORNER Command

The recorner command changes 90 degree wire corners to 135 degrees. It is performed on wire corners exiting pins and vias as well as bend and slant wire configuration. This command is used after completion is reached to reduce track length. This command is typically issued last.

Basic Syntax:

recorner [diagonal]

Example:

recorner diagonal

The CHECK Command

This command can be used to run a DRC (design rules check) and visually tag the violations. This is used in particular when a rule is changed. A check is automatically invoked after every routing pass. The total number of violations is shown on the status line and visual feedback is added to the layout view to indicate conflict locations.

Basic Syntax:

check

Example:

check

The CIRCUIT Command (Advanced)

This command is used to schedule the routing order priorities, specific vias to be used and allowed routing layers amongst nets and net classes.

Basic Syntax:

class <class_id> | net <net_id> circuit {<circuit_descriptor>}

<circuit_descriptor> ::=

[(priority <positive_integer> |

(use_via {<padstack_id>}) |

(use_layer {<layer_name>})]

The value of priority ranges from 0 to 255, the default is 10.

The use_via rule assigns one or more via padstack to a class or a net. If more than one padstack is defined, the autorouter will favor the smallest padstack in size.

The use_layer rule assigns routing layers where nets and classes must be routed. Note that the use_layer rule will override a layer unselection .

Example: Routing a net/class to specific layers

net sig1 (circuit (use_layer L1 L2))

class fast (circuit (use_layer M1 M2))

Example: Assigning Routing Priority

net sig1 (circuit(priority 200))

Example: Routing a defined class to specific layers and using specific vias

(class special net1 net2 net3 net4 net5

(circuit

(use_via via.VIA1__1_10.bv1_10 via.VIA3__4_5.bv4_5 via.VIA3__6_7.bv6_7)

(use_layer SIGNAL_1 SIGNAL_3 SIGNAL_4 SIGNAL_5 SIGNAL_6 SIGNAL_2)

)

(rule

(width 0.007)

(clearance 0.007)

(clearance 0.001 (type via_via_same_net))

(clearance 0.001 (type smd_via_same_net))

)

)

The COST Command (Advanced)

This command sets the internally defined costs to a fixed value. By default, some of the cost values get internally modified during autorouting. It is not recommended to change cross and squeeze costing specifically.

Cost values can range from 0 to 100. A value of -1 will reset the cost value. Predefined cost description values can be used:

Cost | Value
Forbidden | 100
High | 50
Medium | 25
Low | 8
Free | 0

The following costs can be set:

Option | Description
Cross | Crossing conflict
Squeeze | wire to wire clearance conflict
via | wire to via clearance conflict
way | cost of routing in non-preferred layer direction
off-grid | cost of routing off-grid if specified
off-center | cost of entering/exiting an SMD pad off center.
side exit | cost to exit SMD pads on long side
layer | If type is length it is the cost of using the layer; if type is way it is the cost of routing on non-preferred direction.

Basic Syntax:

cost <cost-type>

cost <cost_type> cost_descriptors>|[(type[length|way])] |-1]]

Examples:

cost layer TOP forbidden

cost layer I1 high (type way)

cost via high

The DIRECTION Command (Advanced)

Changes preferred routing direction by layer.

Basic Syntax :

direction <layer name> [horizontal|vertical|orthogonal|off]

The GRID Command (Advanced)

Specifies wire and via grid spacing.

Basic Syntax:

grid [via<positive_value>[<via_id>] | wire<positive_value>[<layer_name>]

Examples:

grid wire 8.333

grid wire 5 layer 1

The LIMIT Command (Advanced)

The limit command sets absolute limit values to be applied to each connection. Control is provided to limit maximum allowed number of intersecting wire, number of vias per connection, number of bends, and the maximum distance of non preferred (wrong-way) routing. The range of limit for <positive_integer> is 0 through 255. You can set limit values, perform some routing passes, and return to the default system values by executing a limit command with a value of –1. If you don’t supply limit values, computed default values are used by the autorouter.

Basic Syntax:

limit [cross [<positive_integer> | -1] |

via [<positive_integer> | -1] |

bend [<positive_integer> | -1] |

way [<positive_dimension> | -1]]

Examples:

limit via 2

limit way 200

limit way –1 (resets limit to default)

The LOCK Command (Advanced)

Prevents the router from changing or deleting locked wires. Note that the router is not allowed to connect to locked wires

Basic Syntax:

lock net <name>

The PROTECT Command (Advanced)

Prevents router from changing or deleting protected wiring. This option may be useful to protect pre-routed ground and power nets. Note that the router is still allowed to connect to protected wiring.

Basic Syntax:

protect all wires

The RULE Command (Advanced)

Rules can be set globally (PCB) or specifically to layers, net classes or nets. Note that in the general case this is handled by the design rule system in ARES so this command is only really applicable when working in scriptable execution mode.

There are two categories of rules type; clearances and wiring rules are as shown be the rule descriptor below:

Basic Syntax:

rule [pcb|layer<layer_name>|class <class_id>|

net<net_id>|]{<rule_descriptors>}

<rule_descriptor> ::=

[(clearance <positive_dimension>

[(type {<clearance_type>})])] |

[(junction_type [term_only | all])] |

[(limit_bends [<positive_integer | -1])] |

[(limit_crossing [<positive_integer | -1])] |

[(limit_vias [<positive_integer | -1])] |

[(limit_way [<positive_integer | -1])] |

[(max_total_vias [<positive_integer | -1])] |

[(reorder <positive_integer)] | [(tjunction [on | off])] |

[(via_at_smd [off | on [(grid [on | off])] [(fit [on | off])]] |

[(width <positive_dimension>)]

In ARES you should use the Design Rule Manager User Interface (Technology Menu) to specify rules and then let ARES communicate with the router to enforce them.

The SELECT Command (Advanced)

This command enables the autorouter to use specific layers and vias for routing. It will also allow for selecting a net for routing. Note that names are case sensitive.

Basic Syntax:

select[layer|via]{<id>}|[all[layers|vias] |comp{<comp_name>}|[net]{<net_name>}

The UNLOCK Command (Advanced)

Unlock existing tracks.

Basic Syntax :

unlock net <name> | [all {layers|vias}]

The UNPROTECT Command (Advanced)

Unprotect existing tracks and allows the router to reconsider them.

Basic Syntax :

unprotect all wires

The UNSELECT Command (Advanced)

Disallow the autorouter the usage of specific layers and vias for routing. This command can be used to reduce the number of layers from that originally specified. Note that names are case sensitive.

Basic Syntax :

unselect [layer|net|via]{<id>} | [all {layers|vias}]

Example :

unselect layer s1 s2


Hints and Tips

HINTS & TIPS

Overview

Most auto-routing exercises proceed along the following lines:

  • Load the netlist and place some or all of the components.
  • Set up design rules and configure net classes to define track and via styles for routing.
  • Organise Plane Layers where appropriate to enable routing to power planes.
  • Run the auto-router in fully automated (or scripted) mode.
  • Unless complete routing occurs, examine why/where the routing has become congested and move components around accordingly. To remove tracking placed by the router, you can use the Delete icon in Route Placement mode.
  • When you are satisfied with the component placement, either switch to interactive routing mode for complete control or repeat the fully automatic execution with a higher repeat count.

If you reach 95-99% completion and are struggling to fully complete routing you may want to investigate the problem connections. The easiest way to do this is to use the Connectivity Rules Checker on the Tools Menu in ARES. Double clicking on a list item will zoom the board to that connection, allowing you to easily investigate the problem area.

Apart from the above, the following sections form answers to commonly asked questions about using the auto-router.

Single Sided Boards

To route single sided boards, you need to configure the net classes so that all passes specify the single layer on which you want to route. This will force ARES to route both horizontal and vertical traces on the underside of the board.

Setting the POWER class to rout on a single layer

The number of iterations of the router for single sided boards will be considerably higher than that for boards with multiple signal layers (the removal of via capabilities vastly complicates the routing problem) but, with good component placement, completion of most boards can still be expected.

Routes which are not completed will be left displayed as ratsnest lines; some manual route editing will be required to convert them to be sensible wire links.

Avoiding Using Component Pads as Through Holes

For small scale prototype, hobby or educational production it can be useful to produce boards in which the pins of some components (e.g. ICs, electrolytic capacitors) are not used as through holes.

The way to achieve this is to redefine the component library parts to have pads on the Bottom Copper layer only. The router will then only route to these pads from the underside.

Surface Mount Components

Surface mount components, especially ICs, present something of a problem to a traditional grid based router because the pin spaces are rarely 25 or 50 thou. Thus tracks running on the grid cannot connect directly to the pads because the centres of the grid squares do not coincide with the pad centres.

Notice that the centre of some of the pads are not on a grid point, PIN1 is, PIN2 isn't

To overcome this, you should always run one or more fanout passes before routing to maker it easier for the router to make connections during the routing phase.

You should also be careful regarding placement of objects such as decoupling capacitors – if you ‘block the entrance’ to the pads (and particularly if you are routing single sided) then the router clearly cannot make the connection

Routing to Power Planes

It is important that all power planes to which you wish the auto-router to via to are placed on designated plane layers.

Setting a plane layer.

Despite costing the crossing of a split plane highly, it is possible that a zone is splintered during routing by a track on a different net. This can usually be resolved by adjusting the layer set of a net class or by routing interactively where you have more control. Failing all else it may be necessary to correct this after routing or to simply place the zones after routing in the area concerned is complete.


Introduction

INTRODUCTION & BACKGROUND

Overview

The way in which a PCB design program handles power planes has become much more important in recent years, mainly as a result of the new legislation on electromagnetic compatibility. There are at least three ways in which PCB software can implement power planes:

Grid Based Power Planes

Many mid-to-high end PCB design programs perform some kind of flood fill operation to produce power planes. Essentially, the target area is divided into squares and tests are made to see which squares can be filled with copper, and which are occupied by other objects.

This approach, although relatively straightforward to implement, suffers from a number of problems:

  • Because a rectangular grid is used, any diagonal boundaries invariably come out in a staircase pattern, which is non-ideal for RF boards in particular. In addition, the power plane cannot 'squeeze through' narrow or non-orthogonal gaps and so optimum connectivity is not always achieved.
  • If any of the pads to be connected to the ground plane are off grid, and if the ground plane is hatched, it is difficult to ensure that they are properly connected.
  • In order to maintain the connectivity database, it is usual to represent the ground plane hatching as ordinary tracks. Not only does this use large amounts of memory and slow down the software, but it also makes it difficult to edit or remove the ground plane after it has been generated.

The last two problems could probably be overcome by sufficient coding but the first point is very intractable.

Negative Image Power Planes

Another approach is simply to draw enlarged copies of all the pads and tracks which are not to connect to the ground plane, and say that the result is a negative image of the power plane. Although used in some quite expensive software, this approach is badly flawed:

  • The software cannot check if full connectivity is actually achieved - it only needs one track running right across the ground plane area to break it into two unconnected regions. If you are not allowed tracking on ground plane layers, then this usually forces the use of a multi-layer board.
  • Even if connectivity is achieved, it is possible for 'slivers' to exist where the enlarged obstacle images nearly touch - perhaps leaving just 1 thou of copper between them.

Polygonal Gridless Power Planes

Although by far the hardest approach to implement, this scheme has none of the disadvantages of the other two and, so far as we know, no significant ones of its own either.

In essence, the idea builds on the negative image approach:

  • The process starts by generating polygonal boundaries surrounding all the pads and tracks within the target area. We call these polygons Holes.
  • The holes are 'added' together in the sense that where two or more overlap they are replaced by a single hole which closes them both. This process continues until a much smaller number of many-edged holes remain.
  • These holes are subtracted from the original boundary of the target area. This boundary is also a polygon, so you can have any shape of area you like filled with copper. It is at this stage that the software can find out if the connectivity is complete or otherwise. If a hole cuts right across the boundary, then the boundary is split into two separate regions of copper.
  • Where holes are created by pads which are on the same net as the ground plane, the software checks to see if and how a thermal relief can be placed, and amends the connectivity database accordingly.

With this much implemented, there still remain two problems:

  • Where two holes nearly touch, 'slivers' of copper can exist which give theoretical but unmanufacturable or unsatisfactory connectivity.
  • If the power plane is to be drawn with a Gerber photoplotter or a pen-plotter, only a pen of some minimum thickness can be used to draw it. If such a pen is used to draw the boundary of a polygon, then it will actually end up enlarged by half a pen-width, and this could violate the design rules. In addition it is impossible to draw very pointed corners with a 'fat' pen.

Both these problems can be solved by starting out from the premise that all the boundaries will be drawn with a pen of specified thickness. Then, all the holes are computed as enlarged by half this pen width over the their nominal size. Thus the second point (above) is taken care of at the hole generation stage. But in addition, no polygon boundary can be less than a pen width in thickness and so no slivers are created either.

Ground Planes Without a Netlist

One issue that cropped up with annoying regularity in technical support for older versions of ARES was a requirement to produce a ground plane for a PCB which had been produced without a netlist. The problem with this is that of knowing which pads are actually connected to ground. In some older versions- which performed a flood fill from the pads on the specified net to generate a power plane - this problem appears more or less insurmountable.

Note that there is a selector checkbox on the Edit Pin dialogue form so that you can select individual pads to have thermal reliefs, or else connect solidly to the power plane.


USING POWER PLANES

Overview

There are two alternative ways of using the polygonal power plane functionality:

  • Using the Power Plane Generator command either directly on the Tools Menu or from the Layer Stack Manager.
  • Using the Zone icon you can place rectangular or polygonal regions of copper which can form arbitrarily shaped ground planes occupying any chosen region of the board. This option requires Proteus PCB Design Level2 or higher.

In both cases, the zones can be assigned to be hatched or solid, and computed with boundary tracks of specified thickness. There are however some differences between the two methods, explained in detail in the following topics and summarized in brief below:

Scenario | Power Plane Generator | Zone Icon - Manual Placement
Defining a plane that covers a plane layer |  |
Defining a partial/split plane on a plane layer |  |
Defining a plane that covers a signal layer |  |
Defining a plane that covers part of a signal layer |  |
Defining a plane that is 'locked' to the board edge |  |
Defining a keepout area inside an existing plane |  |

The Power Plane Generator Command

This command provides the simplest way to create a power plane and causes the generation of a single power plane object occupying the entire area of a given layer of the board.

To use the Power Plane Generator command:

  1. Choose a net for the power plane. If no net is specified, the power plane will connect to any pads which are marked for Thermal or Solid connection.
  2. Choose a layer for the power plane.
  3. Choose a boundary style for the power plane.

ARES will then generate the power plane, and update the ratsnest display to show the effect on connectivity.

The power plane will step away from the edge of the board by the amount specified in the design rule manager for edge clearance. Since this value is rule specific and you can create single layer design rules it follows that you can define different edge clearances for power planes on different layers.

Planes generated with the Power plane generator are considered locked to the board edge (stepped away by the clearance amount) and will automatically maintain their distance from the board edge if it is moved or adjusted.

See Also:

Power Planes and Slots (Tutorial)

Zone Placement Mode

The most flexible and powerful way to use the polygonal power plane functionality is to use the zone placement mode This option requires Proteus PCB Design Level 2 or higher.

To manually place a power plane:

  1. Select the Zone icon.

  2. Select the required layer using the Layer Selector.

  3. Select the boundary trace style for the zone from the Object Selector.

  4. Either:
    - Drag out a rectangular power plane by clicking and dragging from one corner to another with the left mouse button depressed.
    Or:
    - Mark a polygonal power plane by clicking left at each vertex. In this mode, you can also hold down the CTRL key to place curved sections of boundary.

  5. ARES will then pop up the Edit Zone dialogue enabling you to choose a net and fill style for the zone.

  6. When you click OK, ARES will generate the power plane and update the ratsnest display to show its effect on connectivity.

Regardless of the mode of zone creation you can increase the transparency of the zone (dimming) from the Edit Zone dialog as described below.

Plane Layers

A plane layer in Proteus is a copper layer that is not allowed to contain tracking. It is specified in the Layer Stackup manager on the Technology Menu or during project setup in the New Project Wizard.

Configuring a Plane Layer in Layer Stackup (1)

If you are in the New Project Wizard then the Create Power Plane button will be disabled. This is because the power plane generation requires the plane to be assigned to a net and to be placed inside a board edge, neither of which are available at this stage. Once the board edge has been created and the netlist transferred from the schematic you can add the power plane to the layer by revisiting the stackup manager or using the power plane generation tool described above.

Configuring a Plane Layer in Layer Stackup (2)

Users with PCB Level 2 and higher can also put split planes or partial planes on a plane layer.

Why Use Plane Layers ?

The main benefit of specifying plane layers is that during routing, Proteus understands how to make the connection to the plane. During manual routing, Proteus will compare the net of the track to the net of the planes on plane layers and automatically make a connection on double click. Similarly, the autorouter will via through to planes on the plane layer in order to form connections.

See Also:

Manual Routing Examples : Routing to a Plane Layer

Power Planes and Design Rules

The clearance between a power plane and an object is the largest of three values:

  • Currently enforced design rule for the object.
  • Clearance field in the zone dialogue.
  • Specific pad clearance in edit pin dialogue (pads only).

Since the clearance field in the zone dialogue defaults to 0th and the specific pad clearance is also 0th (intended for mounting holes) the normal behaviour for power planes is that they will step away from objects according to the design rules. This works because any border of the zone is treated as a trace for the purposes of design rule clearances.

Three clearance values are relevant:

  • Pad->Trace: The clearance around each pad / via and the zone.

  • Trace->Trace: The clearance between a trace and the zone.

  • Edge/Slot: The step off that the zone takes from the board edge.

If you really need the same clearances across the entire power plane and you have different design rules in force you can set a clearance for the zone via the edit zone dialogue form. This normally happens when you have a zone covering a layer and you then have a design room inside the layer, meaning different rules apply in different areas of the power plane. Bear in mind that the largest (safest) value will be applied wherever there is a duality so to ensure that the clearance field is the one used across the power plane you will need to set it's value higher than that used in the design rules.

The simplest and most verifiable method to handle clearances around places is to do it entirely withing the design rule system using the clearances described above. You can set up multiple rules for different layers, nets or even use design rooms for area based clearances. This will then feed into the live verification system as well as the pre-production check and the design rule report for design documentation.

See Also:

Setting Design Clearances

Design Rule Hierarchy

Editing a Power Plane

Power planes are held as zone objects which behave similarly to other objects in ARES.

To edit a zone:

  1. Select the Zone icon.
  2. Select the zone's layer using the Layer Selector.
  3. Click right then left somewhere on the zone boundary to tag then edit the zone.

Editing a Power plane

Context Sensitive Help is available for all the fields within the Edit Zone dialogue form.

You can also Edit Planes directly from the Zone Inspector dialogue form.

See Also:

Nesting and Islands (Tutorial)

Power Plane Examples

Deleting a Power Plane

This is very simple since the zone is a self contained object 'owning' all the copper regions within its boundary:

To delete a zone:

  1. Select the Zone icon.
  2. Select the zone's layer using the Layer Selector.
  3. Click right twice somewhere on the zone boundary to delete the zone.

Stitching two Power Planes Together

Via stitching is a technique used to tie together larger copper areas on different layers, helping keep return paths short and to reduce noise on the PCB. To stitch planes in Proteus right click on the border of the zone and select via stitch from the context menu. You then set the zone to stitch to and the spacing and offsets for the vias.

Once placed you can move and edit vias in the normal way. You can remove groups of vias with a selection box and the selection filter or you can remove all stitching vias with the remove stitching command on the zone context menu.

Stitching zones is something to be done towards the end of development because it will render the board almost un-routable.

If you receive an error message in the status bar then you have selected the wrong zone to remove the vias from. When the stitching vias or shield vias are placed, they are assigned to the zone stated in the left hand side of the form:

If you select the a zone that does not 'own' any stitching vias and select Remove Stitching Vias, you will receive the following error in the status bar:

The Zone Inspector will list the number of stitching (or shielding) vias associated with a plane.

See Also:

Example: Stitching two zones together

Exposing Solder Resist

Exposing resist plane to ensure good contact with custom Aluminium case with cavity for RF isolation purposes.

You can choose to open the solder resist (solder mask) around an entire power plane via the checkbox on the edit power plane dialogue form. This is unlikely to be used often but, given the complex polygons involved in most copper pours, is a huge timesaver when needed.

If you need to open the resist around a track you can do so with a graphic line of the correct thickness on the appropriate resist layer.

It's really helpful to use the 3D Viewer to visualise the solder resist openings on your board.

See Also:

Solder Resist on Pads

Solder Resist (Rule)

Automatic Regeneration of Power Planes

Use this to speed up work when zone regeneration is slow on complex boards. Full zone regen must then be turned back on before generating output files.

If you place, move or delete tracking or vias onto a board containing one or more power planes, ARES detects whether the power plane needs to be regenerated and then either:

  • Proceeds to recompute the internal boundaries of the zone immediately. On a fast PC (e.g. Pentium 4) and a board of low to medium complexity this real time update mode of working can be quite viable with regen times of the order of 1 or 2 seconds. On Windows 98 and Windows NT, the regeneration of complex zones is run in the background such that you can carry on editing; the zone will redraw as soon as the regen process completes. For long and complex regenerations, ARES draws the zone in hatched form whilst its regeneration is pending. The Background Regen Threshold field on the Set Zones dialogue form determines the number of holes required in a zone for it to be deemed complex and thus processed using background regens.

or:

  • Redraws the zone in hatched form to show that it is invalid. In this case, all such invalid zones can be regenerated by invoking the Regen command, key 'R'. This mode saves much frustration if the zone regen times are rather long, as will be the case on slower PCs or with complex boards.

You can toggle auto regeneration on and off using the Auto Zone Regen command on the Tools menu, default keyboard shortcut key 'Z'.

Quick Redraw Mode

When a zone is drawn 'properly', all the external and internal polygon boundaries are drawn in tracking of the specified style. However, this can be quite time consuming and so a Quick Redraw option is provided in which

  • The polygon boundaries are not drawn at all.
  • Thermal relief segments are drawn as single pixel lines.
  • If the zone is hatched, then the hatching lines are drawn as single pixel lines.

The quick redraw mode, and also the zone auto-regen feature are editable from the Set Zones command on the System menu. Both settings can be saved in the configuration file by invoking the Save Preferences command.

Quick redraw is disabled by default

Auto-Routing & Power Planes

In general, it is best to place power planes prior to auto-routing. There are two principal reasons:

  1. The power plane will make connections to any through hole pads within itself, and this will remove the need for the autorouter to do so.
  2. In the case of SMT components, the automatic via placement pass (PPGVIA) is activated by the presence of the zone(s), and so it is essential that they be placed prior to routing on plane layers if you wish the router to auto-via to them.

In cases where the power plane is on a layer shared with other tracking, the power plane may become split by tracking placed by the router. In this case, some ratsnest lines may be left at the end of the routing pass, and the best thing to do is to re-run the auto-router in order to complete these by conventional tracking.


ZONE INSPECTOR

Overview

The Zone Inspector is an essential dialogue based analysis tool for all the planes on your board. It also provides a really fast way to locate a zone (power plane) and a direct means to edit the zone properties. You launch the Zone Inspector from the Tools Menu in the layout package.

Zone Inspector in Board View. The data grid shows data about all planes on the layout.

For a lot of designers Zone Inspector will prove to be a commonly used tool and it will be useful to assign to a keyboard shortcut. You can do this via the Set Keyboard Mapping command on the System Menu.

Setting the Zone Inspector to launch on the 'CTRL+I' keyboard shortcut.

Locating Planes on the Layout

The layer stackup appears on the left hand side of the dialogue. Layers with no planes are disabled / greyed out and all other layers are selectable. The data grid on the right hand side then lists the planes on the current scope. By default this is the complete board but you can filter the results by clicking on one of the enabled layers. This will restrict the data grid to the planes on the selected layer and will also switch the editing window to show only the planes on that layer.

You can then locate a plane simply by selecting it in the data grid. If it hasn't done already the Editing Window will change to remove all other layers and the plane you have selected will be highlighted on screen.

The currently selected plane is highlighted and the other layers switched off for easier viewing.

If the plane is very small or you want to inspect in more detail you can use the zoom button underneath the data grid to step incrementally to higher magnification.

Inspecting Plane Configurations

The data grid contains lots of useful information about the planes on the board/layer:

Layer

The coloured square is a layer indicator and matches the colour used on the layout and as shown in the Layer Selector on the left. This is the default ordering column ensuring that planes are grouped by layer when in full board view.

Net

Lists the net that a given plane is assigned to.

Net Class

Lists the net class that a given plane is assigned to.

Type

Specifies the type of the plane. Options are Solid, Empty, Hatched, Diagonal Hatch or Compatible.

Area

The percentage area of the layer that is occupied by the plane. This will be an approximation - for example, relief spokes on thermal connections are not counted.

Full Board?

Indicates whether the plane has been set to cover the full board. This can either be done at the point of layer stackup by defining a plane layer or via the lock to board edge option on the Edit Zone dialogue after placement.

Pieces

Specifies the number of pieces that the zone has been splintered into following placement. For example, a track running through the plane will split it into two pieces and the routing to an IC may leave sliver pieces in between the pins. You can think of this column as an indication of how badly the zone integrity has been affected by the rest of the layout.

Islands

Specifies the number of islands on the plane. An island is a piece (as discussed above) that has no connectivity. Often they are therefore considered redundant and can be suppressed via the option on the zone dialogue form.

Stitching Vias

When a plane has been stitched automatically (via the zone stitching or zone shielding commands) this column will display the number of vias used the stitching or shielding.

Coverage

This column provides a percentage coverage for the copper area of the plane against the total area of the layer. It will be approximate and will not account for things like relief connection spokes.

Note that you can re-order the data according to any column you like by clicking on that column. For example, on board view you may choose to order by net instead of layer. That would then group all the GND and VCC planes beside each other on the data grid making for easier inspection.

You can also move up and down the data grid with the up and down arrow keys on the keyboard providing a really easy way to cycle through planes, viewing them on the layout.

Ordering the Data Grid by Net.

Similarly, some columns such as Pieces provide insight into the effect of placement and routing on the plane. Ordering by this column will quickly show which planes have degraded the most.

In addition to ordering the data by column you can also re-order the columns themselves to show the most interesting data to you on the visible dialogue form. This lets you control the size of the dialogue form and prioritise the most relevant information on the screen.

Changing column order to prioritise different data allows sizing down the dialogue.

Editing Plane Configuration

You can edit a plane at any time by

  1. Selecting the plane in the data grid.
  2. Clicking on the edit button at the bottom left.

This can sometimes be a faster and more convenient method to edit than via the zone edge as described above.

Editing Plane Configuration

Changing Plane Priority

This is a situation which occurs infrequently but is nonetheless quite important. Consider the highlighted plane below and notice in particular that it punches out part of an adjacent plane on a different net.

This plane punches out part of the adjacent plane.

The reason it does this - rather than the other plane punching out a part of this one - is draw order. The plane at the front punches out the one at the back. So, if we wanted this to work the other way around we could either move this one to the back or move the adjacent plane to the front. This is done via the two buttons underneath the data grid.

Move this plane to the back and now the adjacent plane punches out of this one.

An easy way to think of it is:

  • Bring to front = punch out of the other planes.
  • Move to back = walk around the other planes.


Examples

POWER PLANE EXAMPLES

See Also:

Power Planes and Slots (Tutorial)

Defining a Power Plane on Part of a Layer

This procedure requires PCB Design Level 2 or higher.

To define a partial power plane

  1. Select the Zone Icon
  2. Left click the mouse consecutively at each boundary corner of the area you wish the zone to cover (hold down the CTRL key to define a curved segment).
  3. When complete, assign the zone to a net and configure from the resulting dialogue form

Placing a Power plane

Defining a Keepout Area inside a Power Plane

This procedure requires PCB Design Level 2 or higher.

To specify a keepout area inside a power plane

  1. Select the Zone Icon
  2. Left click the mouse consecutively at each boundary corner of the area you wish the keepout to cover.
  3. When complete, set the zone type to be EMPTY from the resulting dialogue form

Setting the Zone type to be EMPTY

Controlling the Copper Flow on a Power Plane

The level of copper coverage is controllable via two options on the Edit Power Plane dialogue form, namely 'Allow Nesting' and 'Suppress Islands'.

Setting Supress Islands and Allowing Nesting of the zones

Allow Nesting

When selected the zone will 'jump' over obstacles such as tracks on other nets which would otherwise have prevented the copper flow from entering into an area.

Suppress Islands

When selected all distinct areas of copper which do not connect to a pad on the specified net will be removed.

It follows that maximum zone coverage can be obtained by de-selecting the Suppress Islands option and enable the Allow Nesting option. However, a more common configuration would be to have both Allow Nesting and Suppress Islands enabled.

Specifying a Plane Layer

Specifying a plane layer makes a big difference when it comes to routing the board. In particular, the autorouter will not attempt via connections to planes that are not on a plane layer.

To specify a plane layer

1) Enter the stackup manager on the Technology Menu.

2) Assuming the stackup is correct, change the layer(s) in question from signal to plane.

3) It is often a good idea to rename the layers at this stage to reflect their singular purpose.

Once created you can add planes to the layer directly from the 'Create Power Plane' button. 1) Select the layer you wish to add a power plane on. 2) Click on the Create Power Plane button. 3) Select the required net and click on OK.

See Also:

Plane Layers

About Layer Stacks

Creating a Hatched Zone

Ground and power planes are normally hatched where the resulting board needs to flex.

To create a hatched zone

  1. Edit the power plane.
  2. Set the type to be hatched.
  3. Select the diagonal checkbox for a cross-hatch or mesh topology.

Solid planes are the best return paths. Cross-hatch should only be used when the situation demands it. Trace alignment over cross hatch is then very important and traces should be placed over the cross-hatch intersections..

Finding a Power Plane on the board

On a standard 4 layer board with plane layers this isn't going to be hard. On an 8 layer board with IC specific planes, different grounds and split planes on the other hand it can actually become quite frustrating. The easy way to locate planes is using the Zone Inspector dialogue.

To locate a particular power plane.

  1. Launch the Zone Inspector dialogue from the Tools menu.
  2. Select the layer that the zone is on.
  3. Select the plane from the data grid - it will tag on the editing window.
  4. Zoom using the button underneath the grid to magnify your view.

Locating a Power Plane using Zone Inspector. The up and down arrows can be used to switch between planes in the dialogue form.

The zone inspector lists quite a lot of useful information about the plane but if you need to you can edit the plane directly via the button underneath the data grid on the zone inspector dialogue form.

More information on the Zone Inspector can be found here

Specifying the thickness of Thermal Relief used in Power Plane Connections

To define the thermal relief for a power plane

  1. Edit the power plane
  2. Change the relief style combo box to the track thickness you wish to be used for relief connections.

Setting the Relief of the zone to be of style 'Relief'

Note that if the relief style is thicker than the width of a SMT pad then no connection will be made; otherwise there is a danger for design rule violations between the relief track and the surrounding pads on the IC.

The relief style cannot be thicker than the boundary style otherwise the relief may 'stick out' and cause a short.

It is important to understand that this is the default relief which will be applied to all relevant pads on the zone. You can override this on a per pad basis via the Edit Pad dialogue form (see example below).

Changing the Topology of the Relief Stems on a Pad

It is sometimes useful to change the relief stems from '+' to 'x' in order to maximise connectivity to the zone.

To change the direction of the relief stems for a pad

  1. Edit the pad on the layout
  2. Change the relief field to 'Thermal X'.

Changing the Topology of the Hole Clearance on a Pad

Sometimes, particularly with hatched zones or flexi-boards, an octagonal hole is less suitable than a more circular approximation.

To define the hole shape on a power plane

  1. Edit the power plane
  2. Change the hole shape combo box to the either octagonal or circular.

Circular holes are still arc approximated and use the global curve tolerance parameter specified on the Design Rule Manager dialogue form.

Specifying the Clearance for the Power Plane

Key Point: Any border of the power plane is considered to be a trace for design rule purposes

To define the clearance for a power plane

  1. Go to the Design Rule Manager in the Technology Menu.
  2. Find or create the design rule that applies to the power plane. This could be the board rule if no other rules have been set up or a layer rule if one has been created for the layer on which the power plane is being placed.
  3. The Trace->Trace clearance will determine the distance between the power plane and any routes on other nets and the Pad->Trace clearance will determine the clearance between the power plane and any pads/vias on other nets.

See Also:

Power Planes and Design Rules

The clearance of the power plane to the board edge is defined by the Edge design Rule.

Note that you can also set design rules per layer, meaning that you can specify different clearances for different power planes.

Routing to a Power Plane

If the power plane has been placed on a plane layer then the autorouter will make via connections to the plane wherever possible. Double clicking to place a via during manual routing will also automatically complete the connection to the plane layer.

If the power plane is on a signal layer then the auto-router will not make connections to the plane. Manual connections can be made simply by double clicking the mouse to drop a via or by tracking to the edge of the plane.

See Also:

Plane Layers

Manual Routing Examples: Routing to a Plane Layer

Setting a Minimum Clearance for a Pad

Normally used for mounting holes, this allows you to set a minimum clearance between power planes and a single pad.

To set a minimum clearance for a pad

  1. Select pad mode and place a pad of the correct size.
  2. Right click on the pad, select edit properties and then set the minimum zone clearance field as desired.

Specifying a minimum 20th clearance from Power Planes on a mounting hole.

Notes:

  • The value set is the minimum zone clearance. Actual clearance will be the larger of the design rules, the zone clearance (zone dialogue) and this value.
  • If you set the relief style to be solid and the pad is assigned to the same net as a power plane then there will be no clearance between the power plane and the pad, irrespective of the value in the clearance field. The clearance will still apply to all other power planes which are on a different net from the pad.

Zone clearance applies to VCC zone on Top Copper but not to GND zone on Bottom because Relief style is set to solid.

Stitching two Power Planes together

Stitching zones is something to be done towards the end of development because it will render the board almost un-routable.

To stitch two power planes together

  1. Right click on the border of the power plane and select Via Stitch from the resulting context menu.

  2. If there are multiple planes on different layers select the destination plane for the stitching. Set the via style and the spacings for the via grid.

Context sensitive help is available on the dialogue form via the '?' at the top right. This contains more information on each field in the dialogue.

3. Exit the dialogue form with the OK button. It may take up to a minute for the zones to be stitched. You will see that vias will appear where they can:

You can remove stitching wholesale via the context menu command on the zone menu or in part by dragging a selection box and changing the selection filter so that only via's are selected. In the latter case be careful not to catch routed via's in the selection.

Via Shield on Power Planes

To place a via shield on power planes

1 To place a via shield around the perimeter of a zone start by right clicking on the zone border and then select via shield from the resulting context menu.

2. Specify the destination zone layer for the stitch (if more than one is available) and then set the spacing requirements for the via placement.

Note that you can use both imperial and / or metric units.

It may take a minute or so to place once you exit the dialogue form.

Shielding a Route with Stitching Vias

To shield a route (or routes) with stitching vias

1. Make sure you have power planes in the correct topology for the shielding vias to be placed. See Shielding Routes with Via's

2. Select the route or routes (holding CTRL key down for multiple selection if need be) and then invoke the via shield command from the track context menu. Do not select the zone.

3. You need to specify which two zones are being stitched together and then the spacing between vias and the spacing between the vias and the edge of the route.

You need to make sure that there are power planes in the right place for the shielding vias to go on.

Joining two Power Planes at a Specific Point

To bridge two power planes at a specific point

  1. Select track mode and then BRIDGE track style.
  2. Place a track between the two zones. There is a pop up box that will warn you thatr the BRIDGE style of track is not electronically connected within ARES.

Note that the BRIDGE track style is - of necessity - outside of the netlist and therefore ARES will not warn you if you make a mistake. Use with caution!

If you do not have a BRIDGE track style simply create your own trace style and name it BRIDGE.

Analysing Power Planes

By far the best way to analyse your use of planes on the board is by using Zone Inspector. You launch this from the Tools menu in the layout module.

The Zone Inspector Dialogue Form.

The layer info on the left includes number of planes and total coverage on the layer. The main data set on the right shows various plane properties, all of which are explained in more detail in the main help topic.

You can sort the data by column by clicking on a column header at the top. You can sort the columns themselves by dragging and dropping columns around on the data grid. This can be quite helpful if - for example - you want to check how badly your planes have been splintered by placement and routing (order by number of pieces).

You can also use the up and down keyboard arrows to move between the planes in the data grid. This is really helpful if you want to do a visual inspection of the planes on the layout since the editing window view will change to show the currently selected plane.

Finally, you can launch the edit zone dialogue form for the currently selected plane directly via the button underneath the data grid.


CONNECTIVITY RULES

Overview

The required connectivity of the board is determined by the connections made in the schematic and transmitted via the netlist to the PCB layout. The connectivity widget at the bottom of ARES provides live status on the board connectivity. This indicator displays the state of the netlist (locked, changes pending, netlist errors, etc.) if it is not synched or the number of missing connections if the netlist is synched. This makes sense as without a synched netlist the status of the connections is unknown !

See Also:

Netlists and Synchronization

Assuming the netlist is in synch and you do have missings you can click on the connectivity status widget to launch a dialogue with a list of the missing connections. Double clicking on an item in the dialogue will then both tag and navigate to the problem area.

Basic CRC Functions

The CRC check shows:

  • Each pair of pins joined by a ratsnest line is listed..
  • Any extra (non specified) connections to each net are highlighted.

If you click on the entries in the listing, ARES will tag the associated tracking in a similar fashion to the Connectivity Highlight function.

Advanced CRC Functions

The CRC check also:

  • Completely re-initializes the netlist management part of the layout database. Any floating tracking - that is tracking not connected to anything - is detached from netlist management whilst any detached tracking that has become connected to a net is brought under netlist management.
  • Traces and vias involved in any extra connections are assigned to the VOID net. Further information on VOID tracking is given in The Netlist Loader & Existing Tracking.


DESIGN RULES

Introduction

Proteus PCB Layout includes an in-built verification system for testing and warning you when the clearance between objects on the layout is less than required for your design. This lies at the heart of the layout system and is the single most important set of information that you can provide to make the software work for you. It is therefore highly recommended that configuring and setting this up is one of the first things you do when laying out a new PCB; not only is it invaluable in avoiding errors but it is also harnessed by both the auto-routing and the manual routing engines to honour trace widths and clearance specifications.

Design rules work in levels of priority so that you can override one rule with another one in a granular way. You can narrow the scope of a design rule physically by reducing the area in which it applies to a single layer or an area of PCB called a design room. You can also narrow the scope of a design rule electrically by making it apply to a set of connections called a net class. Finally, you can mix the two together to create really granular rules that apply to a set of connections in a particular area of the PCB.

There is quite a lot to understand here so this page will start by introducing the key concepts before showing you how to set up clearances between object and design rules. You'll find quite a few links to more information on this page, much of which will also be required reading if you plan to design PCB's of any complexity

Key Concepts

This topic introduces the following key concepts that are required to correctly set up a constraint driven layout with Proteus:

  • Net Classes
  • Design Rooms
  • Design Clearances
  • Design Rules
  • DRC Viewer
  • Violation Areas
  • Pairs

Net Classes

A net class is simply a net or group of nets that have common electrical characteristics (e.g. Mains Power). Once specified, you can control trace widths, via styles and layer sets for a net class as well as controlling clearances by creating net class specific design rules.

When you set the track width it will automatically be applied when routing a connection in the net class. So, for example, if the POWER net class was specified to have a 25th track you set it up here and then the software will select it for you when you are routing. If you have more than one supply and need different rules for each then just create another net class..

When you set the neck style you tell the software the minimum track width it can use to pass through dense areas. It also lets you take control during routing as holding the SHIFT key down will switch from track style to neck style.

Setting the via style has both economic and electrical consideration but, again, is worth setting up once and then letting the software do the work after that.

See Also:

Net Classes

Design Rooms

A design room is an area drawn out on the layout inside which specific clearances apply. Let's say for example that you have a BGA on your layout. This normally results in a routing challenge in escaping all of the tracks from the BGA where space is at a premium. To help with this you could draw a design room to encompass the BGA and the fanout area around it and then make the design clearances as small as possible in this fanout area. Design rooms can occupy multiple layers so that you could also via down and escape on inner layers.

More generally, you can think of a design room as the smallest physical area in which you can apply design rules. First, you can apply rules to the entire board, then you can apply rules to a single layer and then you can apply rules inside a room that you draw on the layer.

See Also:

Design Rooms

Design Clearances

There are a number of physical design clearances that can be configured to provide real-time checking during the board layout. Specifically, the following clearances are individually supported:

  • Pad-Pad Clearance.
  • Pad-Trace Clearance.
  • Trace-Trace Clearance.
  • Graphics-Net Clearance.
  • Edge-Net Clearance.
  • Resist-Trace Clearance

Whilst the first three are largely self-explanatory, the definition of a pad for design rule purposes is worthy of mention. All pads, vias and padstacks that have an annular ring anywhere on any layer are considered pads. For example, a depleted via (non-functional pad) is considered a pad on all layers for design rule purposes. The clearance measurement starts at the hole border on depleted layers and at the edge of the annular ring on normal layers. Padstacks with no copper on inner layers are treated in exactly the same way.

The only pad like entities not treated as pads for design rule purposes are mounting holes. Here, you place a pad, edit it and set to be a mounting hole. This will remove the annular ring from all layers and the design rule that then applies is the edge/cutout clearance.

Mounting Holes are treated as Edge/Cutout for Design Rule purposes.

See Also:

Mounting Holes

If it's not a mounting hole, the pad->pad and pad->trace rules apply to all pads, vias and padstacks.

The other point of note is how design rules interact with power planes. All borders of power planes are drawn with a trace and so pad->trace and trace->trace rules define the distance that the power plane should step away from other copper objects. The power plane will do this automatically according to the clearance rules in force on various areas of the board.

See Also:

Power Planes

Graphics-Net clearance allows you to set the minimum clearance between a silkscreen graphic and any other object on the board. This is useful as the silkscreen graphic approximates the dimensions of the physical package.

Edge-Net clearance allows you to set the clearance between the edge of the board and any other object on the board. Note that this applies to interior edges as well (cutouts etc.). For different clearances around different edges you should set up the default rule for the main board edge and then use design rooms around the smaller cutouts to change the clearances in those areas.

Global Clearances

Solder Resist Guard

The solder resist guard clearance is global to the board. This is a check for exposed copper features as a result of solder mask expansion around a pad. For example, if you edit a pad style to have a 10th guard gap (solder mask expansion) but you set your pad-trace design rule clearance to 6th then it is possible to end up with 4th of exposed copper trace should the trace hug the pad.

Often this is not a problem but, depending on the board topology, it can lead to solder bridges. It is generally good practise to have a pad-track design rule well in excess of the guard gap on the pads. This normally involves first checking with your board house on their recommended guard gap clearance and then adjusting pad style settings accordingly.

The Solder Resist Guard clearance defaults to 1th and will generate a DRC error wherever a copper object falls within 1th of the solder mask edge.

Minimum Solder Mask Dam

The minimum solder mask dam or the solder mask sliver refers to the size of the soldermask between pads. Having a solder mask dam can help prevent solder bridging during assembly. However, this depends on how the board is being constructed (e.g. reflow solder machine) and also with some fine pitch IC's the pins are so close together that there is no solder mask dam between pins.

For this reason the minimum solder mask dam is defaulted to OFF.

Technology Menu -> Design Rule Manager.

If your design warrants a minimum solder mask then you can change it via Design Rule Manager and that value will be enforced. Be prepared to see a lot of violations initially - you will need to edit pad styles and change solder mask openings (guard gap size) on most IC's.

Changing the Guard Gap on a pad style before applying the change to the design.

Interesting fact (or urban myth?). Apparently, for the best solder mask dam you should make your PCB colour green. For example, if you choose 0.1mm for the dam then green would be 0.1mm, red,yellow,blue boards would need 0.12mm and black would be 0.15mm.

See Also:

Routing Classes

Net Classes (Tutorial)

Design Rules

Design Rules can be thought of as providing the scope in which the clearances apply. The default scope for the rule is the whole board and you can then narrow this physically to a layer on the board or an area of the board (a design room). You can also narrow the scope of a design room electrically by making it apply only to a particular net class. Finally, you can use both techniques to restrict the scope to particular signals in a particular area.

The system provides you with a simple interface and a default rule applying clearances to the entire board but the scheme is extendable as required given the complexity of your design.

See Also:

Design Rule Hierarchy

Design Rules (Tutorial)

Design Rule Viewer

The Design Viewer is a live display (located by default towards the bottom right of the ARES application) that will monitor and display the number of violations of the current design rule and clearance set specified for the layout.

The Live Design Rules Checker

Clicking on the display will then launch a popup listing showing more detailed information, including the design rule in question, the layer, the violation type and the clearance information. If you click on an entry in the list, ARES will highlight the associated design rule flag on the layout, and if you double click an entry, ARES will both highlight it and zoom to its location on the board.

The Design Rule Checker form

Design Rule Viewer/Checker will operate in the units specified for the layout (metric/imperial)

You can manually suppress any given error by right clicking on the error and selecting the ignore option. This is intended for the unlikely but not impossible case where a designer override is required.

Violation Areas

When you click on an error in the design rule viewer the editing window will zoom around the offending area of the PCB and a highlighted violation area will appear. This area represents an area of violation of the rule specified in the design room viewer and provides useful guidance as to what objects can be moved to fix the problem.

Violation Area showing the problem area between pad / via and trace.

Be aware that the violation area does not take account of whether the rule is actually in force over it's entire area. For example, in the picture below the presence of the design room means that actually only the edges of the violation area (outside the room) are the cause of the design rule error. The trick is to first look at the rule that is being broken - since it is the default rule it should not apply in the room because any room rule would take precedence and therefore we should be looking outside the room boundaries to locate the actual infringement.

An example violation area which crosses a room boundary. The violation area shown is the area which breaks the currently selected rule. The presence of the design rule room here means in practice it is only the small area outside the room that is actually non-compliant with the rule set of the board.

Pairs

Pair information is used for differential pair routing and allows some more specific clearances to be included and stored. This information is specified on the diff pairs tab of design rule manager.

See Also:

Differential Pairs

Setting Design Clearances

Design clearances can be set in two places; you can set the global default clearances or you can set clearances within a specific design rule.

The global design clearances apply to all signals on the board on all layers of the board and form the basis for the Default Design Rule; you can change these numbers, launch the Design Rule Manager from the Technology menu and set the rules under the DEFAULT Rule on the Design Rules tab.

The Default Design Rules form

The Resist-Trace design rule is board global and has no user interface.

Often it is the case however, where your design requires different clearances based on location (design rules per layer), based on electrical considerations (design rules per net class) or a combination of both. ARES provides you with a method to specify any number of such design constraints via the Design Rule Manager command, located on the Technology menu.

Launch the DRM from the Technology menu

All such clearances are conditional and therefore form the basis of additional design rules. Put another way, you need to add a new design rule for each board requirement that differs from the manufacturing tolerances (the Default Design Rule). This is discussed in more detail in the next topic.

Design Clearances and Power Planes

For the purposes of design rules the border of a power plane is deemed to be a trace. The clearance between a power plane and a track is therefore the trace->trace clearance for the design rule currently being enforced and the clearance between a power plane and a pad/via is the pad->trace clearance of the design rule currently being enforced.

It's important to understand what this means. If you have a room on top copper and you have set clearances for both the room and the layer then a power plane on top copper will have different clearances to the pads and tracks depending on whether they are inside the room or not.

Should you need to have the same clearance everywhere on the power plane you can edit the zone and set the clearance field manually. As always with a duality the larger (safer) clearance will win. For example, a pad->trace design rule of 8th will be overridden by a zone dialogue clearance setting of 10th leaving the space between the pads and the zone at 10th. By contrast, if the clearance in the zone dialogue was set to 6th and the pad->trace design rule was 8th the clearance between the zone and the pad would be 8th.

A power plane will also step away from the edge of the board by the amount specified in the design rule manager for edge clearance. Since this value is rule specific and you can create single layer design rules it follows that you can define different edge clearances for power planes on different layers.

Setting Design Rules

Note: It's really important when you create a new design rule that you understand how the different types of rules will interact with each other. A rule with higher priority will have it's clearances applied in precedence to a lower priority rule. This is explained in full in the topic on design rule hierarchy.

Setting specific rules in the Design Rule Manager

The Design Rule Manager is the place where you can add additional rules specific to the current project. As can be seen from the screenshot above the dialogue has six areas for configuration.

Design Rules

This is where you create, rename and delete design rules or select an existing rule for editing. The Default rule is the global tolerance rule as discussed previously and is therefore permanent (cannot be deleted) and locked to all layers and all net classes.

Apply to Layer

After creating a new rule you can specify that the rule applies to all layers or to a specific layer of your choice.

Apply to Net Class

When creating a new rule you can specify that a design rule applies to a specific net class or to all net classes from this selector. Note that the default rule is locked to all net classes and that only named net classes will appear in this selector.

For more information on defining net classes click here.

With Respect To

If you have defined a rule which applies to a specific net class you can then further refine the rule by specifying whether the rule applies only within the same net class, whether it applies only with respect to other net classes or whether it applies to both same net class objects and other net class objects.

Note that if you select either Same Net Class or Other Net Classes the graphics clearance and edge/slot clearance fields will be disabled as these objects are not specific to a net class and their meaning in such a case is ambiguous. These clearances are ignored for the purposes of such a rule.

Enable Design Rule Checking

This checkbox allows you to turn of the live checking for the currently selected rule. We recommend however that you leave this option selected.

Clearances

This is where you specify the required minimum clearances for the rule you are creating. The Apply Defaults button simply resets these clearances to those specified in the Global Rule (Technology menu - Design Rules).

Design Rule Reporting

You can generate report of all the design rules in force on the PCB via the Project Notes module. First, open Project notes and choose the design rule report from the template selector

If you already have more than one report open you can create the new report from the New Note command on the File Menu in Project Notes. The module needs to be unlocked to enable the new note command

The report will automatically generate and will list rules and clearances along with the layer ranges that they apply to. Note that the report does not include any concept of hierarchy but rather is just a complete listing of all rules set up for the current project.

If you do want to browse hierarchy and see which rules are in effect in a particular area of scope of the board the best place to do that is in the design rule manager itself. You can use the tree on the LHS to choose the scope you want and the right hand view will show you both the specified and inherited (grey in colour) rules that apply in your chosen scope.


DESIGN RULE HIERARCHY

Introduction

Given that you can create several design rules that potentially ‘overlap’ each other, it is very important to understand how the design rule system works.

Proteus PCB Layout supports a hierarchy of rule types in increasing order of precedence. A rule in a higher priority level of the hierarchy will take priority over an overlapping rule that is in a lower priority level of the hierarchy. Where two rules are in the same level of the hierarchy and they overlap the rule with the highest specified clearance in a given situation will ‘win’.

The simplest way to understand this is that a more specific rule takes precedence over a more general rule; for example, a rule confined to a specific layer will take precedence on that layer over the default rule which governs the entire board.

The following is an explanation of the rule types, starting from the lowest priority level of the rule hierarchy and working up to the highest priority level of the hierarchy.

Design Rule Hierarchy

Board Rule

These are rules that apply to all layers on the board and to all electrical net classes. There is only one default rule (sometimes called the PCB rule) and that pre-supplied when you start a new project.

The default rule cannot be deleted for obvious reasons and cannot be changed to apply to specific layers or net classes.

This rule is at the lowest level of the design rule priority tree, meaning that any additional design rules will take precedence on the layer or net classes that they affect.

Layer Rule

A Layer Rule is a rule with clearances that apply to all routes and pads but is confined to a single layer of the PCB. Use this to reduce the physical scope of the rule while still applying it to all objects.

Per Layer rules take precedence over the PCB rule but are lower in precedence to all other rule types.

Class Rule (All Layers)

A Net Class Rule is a rule with clearances that apply to a given net class on all layers of the PCB. Use this to restrict the rule to specific signals (net class) wherever they might be on the PCB.

This rule will take precedence over both the PCB rule and any Per Layer Rules.

Class Layer Rule

This is a rule where the clearances apply to a specific net class only on a specific layer. This rule restricts both the scope (to the layer) and the signals (to the net class).

This type of rule will take precedence over all the aforementioned rule types and in particular will take precedence over a Per Net Class (All Layers) rule.

Class Class (All Layer)

A Class Class rule is one where the clearances apply to a specific net class but with respect to either itself or to all other net class. In other words, a rule such that the clearances apply only between traces and pads on the same net class or if you set up a rule where the clearances apply only between traces and pads on one net class against traces and pads on any other net class.

In this case, the Inter net class rule applies to all layers.

Class Class Layer

Exactly as above except that the inter net class rule applies to a specifically designated layer.

Room

A room is a user drawn and named area of the PCB. It is the smallest physical scope you can specify for a rule, even though it can occupy several layers in the Z-direction. The important thing to remember about a room is that it overwrites all of the above rules.

So, a room rule wins over any and all rules with a bigger physical scope (all layer rules and all board rules).

Class Room

A class room rule provides an electrical filter inside the room, allowing you to specify different clearances for a specific net class that apply inside the scope of the room. Use this kind of rule for example to set up clearances for sensitive nets in the fanout region of a BGA.

Class Class Room

A class class room rule is the highest priority rule available. It defines the clearances for a net class either with respect other objects on the same net class or with respect all other objects inside the scope of the room. It's exactly the same as the class class rule and the class class layer rule but this time the physical scope of the rule is the room.

While this may sound complicated it is in fact quite intuitive in use. We recommend you read through the examples provided in the section below to make sure you understand how the system works.

Summary

In terms of increasing priority design rules work as follows:

  • Default: Whole board.
  • Layer: E.g. A rule for Top Copper or for all inner layers.
  • Class: E.g. A rule to apply to the POWER net class.
  • Class-Layer: E.g. A rule that applies to the power net class on top copper.
  • Class-Class: E.g A rule that applies to the POWER net class with respect to itself.
  • Class-Class Layer: E.g. A rule that applies to the POWER net class with respect to itself on Top Copper.
  • Room: E.g A rule that applies inside a placed room called BGAFANOUT.
  • Class-Room: E.g. A rule that applies to class POWER inside the a placed room BGAFANOUT
  • Class-Class-Room: E.g. A rule that applies to class POWER with respect to all other classes inside a placed room BGAFANOUT.


DESIGN ROOMS

Introduction

There are often areas of circuitry on the PCB that require different clearances than the rest of the board. Sometimes we can cater for this by adding a design rule that applies to a specific layer on the board but in other cases what we need is to apply a design rule to a region of the board. In Proteus design rooms are the answer to this problem.

Normally, you place a design room by selecting the room tool and dragging out a box on the layout. You then use the edit room dialogue to specify the name of the room and which layers it covers. Finally, you set up a design rule that applies to the named room and you can then enter custom clearances that apply in this area.

Design rooms can be an extremely useful tool in many different situations, from BGA escape areas to high power areas to high speed channels.

Placing a Design Room

To Place a Design Rule Room

1) Select the room icon and drag out the room on the PCB. When you are finished you will see the edit room dialogue form.

Placing a Room

You can also place a room using consecutive left clicks, much like the manual placement of a power plane. This will allow you to place polygonal design rule rooms (e.g. L shaped).

2) Switch to the DRC Room tab and specify the name for the room and which layers it occupies.

Naming and Defining the Room

Once the room is placed and named you can configure design rules and clearances for the room.

Setting Up Design Rules for a Room

To create a Design Rule for a Room

1) Having first placed the room on the board, open the design rule manager from the Technology menu. The room will appear in the region tree under each layer that it is present on.

Opening the Design Rule Manager

Note that at first the rules that apply to the room region are inherited from a larger region. Inherited rules are drawn in a light grey to show that they are scoped to a larger region. In the picture above the rule that is in force is actually the board rule because neither a room rule nor a top copper layer rule has been created.

2) Click on the new button to create a new rule. From the resulting dialogue you need to scope the rule physically to the room region. You can also scope the rule electrically if required from the options at the bottom left. Finally, you set the required clearances.

Defining a rule for the Room.

Design Rule Considerations

Before creating design rules for rooms it's important to have a grasp of the design rule hierarchy. This is discussed in detail in the topic linked below and summarized here in brief.

List of Design Rule Types in order of priority.

See Also:

Design Rule Hierarchy

You can see immediately that the room rule is a high priority rule and the other rules that apply in a room are higher priority still. This means that before you create a rule the clearances that will apply in the room area will be inherited from higher up the rule priority chain. Here's an example.

The Room inherits rules from larger regions when no rules are defined.

Inherited rules are drawn in a light grey whereas rules that are defined with a scope of the currently selected region are drawn in black. In the example above, any rule created with a scope of the BGAESCAPE room would therefore appear in black but layer rules and board rules will appear in light grey. So, in our example we have inherited:

- a Top Copper rule that applies to objects on the SIGNAL net class with respect other objects on the SIGNAL net class.

- a Top Copper rule that applies to any objects belonging to the POWER net class.

- a board level rule that applies to any objects belonging to the HIGHPOWER net class.

- a board level rule that applies to anything else.

See Also:

Net Classes

Since we've create the design rule room to have different clearances we clearly want to make changes. There are two strategies and both are equally valid.

The Extreme Prejudice Approach

If we create a room rule that has no electrical filters then it will apply to all objects in the room. Since the room rule has higher priority than anything else and it applies to all objects it will nuke all of the inherited rules.

A room rule with no electrical filter will apply to all objects in the room and override all inherited rules.

This has the advantage of simplicity and can make things easier to understand. The downside is that if you do want to preserve some electrical rooms inside the room (e.g. the POWER clearances) you would have to set up a second rule (a CLASS ROOM rule) that used those clearances. The clone button is a relatively quick way to do this.

The Scalpel Approach

If we are only worried about certain connections then why throw away the rest of the rules framework ? Let's say for example that we want to give a bit more space to the SIGNAL net class inside the room. Here we could create a specific rule for the SIGNAL class in the room and everything else in the room would still use the inherited rules.

You can choose to create a room rule that applies only to certain signals. Other objects will then use inherited rules.

Which method you decide to use is largely a matter of personal preference but also depends on how much control you need over the objects inside the room. One benefit of starting with a room rule that applies to everything is that it really will apply to everything on the room, regardless of how many layers the room is on. Using a very specific rule in a multi-layer room can introduce subtleties because the rules that are inherited can differ on different layers of the room.

Rules in force on Inner 3 within the BGAESCAPE Room.

Notice in the screenshot above that we have one rule less applying on inner 3 within the room. This is because one of the rules was a layer rule and applied only to top copper (TCPWR). Of course, if the rules are defined with care from the outset this is probably exactly by design and not of concern. It is however something to be aware of and if you are concerned you might be better to take the 'start again' approach outlined above.

Deleting a Room

To delete a room you need to both remove it from the layout and remove any configured rules in Design Rule Manager. Deleting on the layout is simply via the right click context menu on the graphic object. Similarly, you can simply select and delete rules from the Design Rule Manager. Note that if you've removed the room from the layout first you will need to switch the selection radio buttons in design rule manager from Applicable to All in order to see and remove the room related design rules.

Switch to view All rules if you have deleted the room on the layout (since they are no longer applicable!).


Examples

DESIGN RULE EXAMPLES

Introduction

This section of the documentation provides some examples to re-inforce the contents of the previous topics. In the following discussion assume that we have drawn the schematic, netlisted the design, and now need to create some design rules to determine the design rule constraints of a 4 layer board.

Every board starts with a default rule which can be edited, however if you require more specific rules, follow the below information.

Setting up a Rule that Applies to a Layer

Lets say we would like to have a Rule that stops any object (Track, Pad or Via) on Top Copper from being closer than 5th away from any other object. In the Design Rule Manager, Select the Top Copper Layer and click 'New':

Next we need to give the rule a sensible name and assign the rule to the required area of the board. In this case it applies to TOP Copper.

As we want the rule top apply to all objects, we can leave Net classes set to 'All Classes' and 'With Respect to' also set to 'All Net Classes'.

This means that All objects on all Net Classes on TOP Copper will adhere to the rule. Next you set the distance that is the minimum distance allowed for all objects to get close to

Click OK to set the Rule. And you will see the following:

Setting up a Rule that Applies to a Net Class

In this example, we require a 12th rule that applies to the POWER net class which will apply to all layers and any net class including itself.

1. Open the Design Rule Manager from the Technology menu.

2. Click on the New button

3. Give the Rule a name. For this example we can call it POWER.

4. Make it apply to the BOARD

5. Apply to Net Class -> Drop the list down and select POWER

6. With Respect to ALL Net Classes and you should see something like the following:

Setting up a Rule that Applies to a Design Room

You can set constraints on a specific area of the board. These areas are call Design Rooms see here for more information. Assuming that you have placed a Room, open the DRC Manager and create your required rule that you need inside the room. Lets say that the rule we want is a 5th Top copper only on the Signal layer

1. Click on New

2. Create the Rule name

3. Set the Region to be the Design ROOM which will appear under the name that you gave the room

4. Set the Net class to be Signal

5. Set the 'With Respect to' to be Same net class

6. Set the clearances, and you should have the following:

Analysis

With the above there are four rules in place and a hierarchy of Rules.

  • The Room rules will take precedence over all other rules
  • The Net class rule over rules the Layer rule
  • The Layer rule is above the Default rule
  • The Default rule will cover anything that is not covered in the above rules.

The rules hierarchy is explained further here


SINGLE PIN NET REPORT

Introduction

With complex, multi-sheet schematics and large components which may span several elements and include multiple NC pins it's not at all easy to verify that each connection has been considered and correctly handled. It's surprisingly easy to miss a connection on the schematic and not realise until much later in the layout (if at all!). Worse still, since the connection is missing from the schematic there will be no rastnest lines on the layout and the connectivity report will have no knowledge of the problem.

The single pin net report in Project Notes is designed to help customers who want an auditable way to ensure that each connection or NC pin has received designer attention.

Generating the Report

To generate the single pin report:

  1. Open project notes and select the single pin report from the available templates. If Project Notes is open (and unlocked !) select new project note from the File menu and then the single pin report from the available templates.

  2. The report will be automatically generated with the data table listing all component pins which are not connected to anything but which also are not explicitly marked as NC pins.

The goal of the report is that either there are no entries in the table (all pins are accounted for) or that each entry in the report is explained textually underneath so that a recorded decision has been made for each case.

The Workflow

1) Generate the report as above.

2) Find the pins in the report via design explorer.

Dragging project notes module into separate space (split screen) is helpful here if you have multiple monitors

3) Attach an NC terminal to the pin to explicitly mark it as NC or wire it if it is mistakenly NC.

You can also mark pins as NC in the packaging tool but this of course is then not visible in a schematic printout

4) Rinse and repeat for other NC pins.

It's assumed of course that over time users needing to work with this level of verification will actually place NC terminals against NC pins at design time and so very little if any work will be required at this verification phase.


TESTPOINTS

Introduction

Testpoints can be used on the PCB in many different ways, ranging from sporadic coverage for calibration and monitoring where it's deemed necessary to more rigorous coverage for bed of nails or flying probe testing. Proteus allows you to work with testpoints in the way which best suits your design. You can simply place and designate testpoints as needed or set up a testpoint coverage strategy and the work to ensure compliance.

Creating Testpoints

A testpoint can be either a dedicated pad or it can be an existing pad/via already on the layout. Where it is a dedicated pad the process starts on the schematic with the placement of a testpoint terminal.

Placing a Testpoint Terminal

To place a testpoint terminal:

  1. Select terminal mode on the schematic and the testpoint terminal.
  2. Left click to start placement and use the + and - keys on the numeric keypad to rotate the terminal.
  3. Left click again to drop the terminal.
  4. Wire up in the normal way.

Placing a Testpoint Terminal on the Schematic

For each testpoint terminal there is a testpoint package on the layout. This must be also placed and connected up

Testpoint Pad needs placing and connecting on the layout.

Important: All testpoints placed this way will be packaged with the same pad footprint. You can change this (Design Rule Manager -> Defaults tab) but it applies to all testpoint terminals. If you need different pad sizes you can use the designate method below.

Designating a Testpoint on the Layout

To designate a testpoint on the layout:

  1. Enter selection mode
  2. Right click on the pad or via
  3. Select testpoint from the context menu.

Specify a pad as a testpoint from the context menu.

You can only create a testpoint where the pad size is larger than the specified minimum dimension of pad shape. This is set in Design Rule Manager -> Defaults tab and is intended to ensure that a probe can always connect.

Whether you choose to work with testpoint terminals on the schematic, designate testpoints on the layout or work with a mix or both probably depends on board density, required coverage (and maybe corporate policy).

Using testpoint terminals on the schematic has some advantages :

  1. They are visible on the schematic.
  2. They are automatically and uniquely annotated (e.g. TP1, TP2, etc.)
  3. They're obvious and easily located on the board.

There are also however a couple of disadvantages:

  1. Each terminal requires the placement of a new pad on the layout. Often the designation of an existing pad is more convenient and saves space.
  2. If you want large scale testpoint coverage it's a lot of terminals to place on the schematic.
  3. Each testpoint based on a schematic terminal will (must!) have the same footprint.

Testpoint Rules and Clearances

The location of testpoints on the layout - whether placed or designated - is governed by three basic rules found on the Defaults tab of the Design Rule Manager. These settings are global to the board.

Testpoint placement and clearance settings.

Testpoint Access

Determines whether testpoints must be on a particular side of the board (e.g bottom for bed of nails) or whether is access is possible from either side of the board.

Minimum Dimension of Pad Shape

Determines the minimum size of pad shape required for the testpoints. This is required of all dimensions of the pad (e.g. length and width for rectangular pads).

Minimum Distance between Test Points

This distance is governed by the pitch limitations of ICT probes and so should be set in consultation with testing to ensure access.

These constraints are designed to cover the basics and help with a successful testpoint strategy. They do not however guarantee a successful test point strategy. For example, no consideration is made of placement inside component bodies (rendering the testpoint inaccessible after assembly, component heights (which can obstruct access for probes) or pin length which can determine whether sufficient exposed pad is available for probes on designated testpoint pads.

Testpoint Coverage

If you decide to use testpoints formally in your project then ensuring adequate coverage is important. This could be as simple as making sure there are at least two testpoints per net for flying probes or it could be something like ensuring that each power net has testpoints (or both).

There are two ways to specify coverage, both of which take place in Design Rule Manager.

Global Coverage:

Specify that testpoints are required on all nets and also the minimum number required per net.

Set global testpoints requirements.

Net Class Coverage:

You can override the global settings per net class. Depending on what you need this allows you either:

  • Have no requirement for testpoints on all nets and simply set the testpoint requirements on the net class(es) you are interested in.
  • Set a global requirement for testpoints on all nets and then override for specific net class(es). Here for example you might set to zero for a net class not requiring testpoints or 3 for a net class requiring more testpoints.

Override any global coverage settings for the current net class.

If you choose to set testpoint requirements (and you don't need to) then both placed and designated testpoints will contribute to the required total for the net.

Testpoint Compliance Workflow

So, now you've set up your testpoint strategy and it turns out there's a couple dozen nets needing at least 2 testpoints each. The system now needs to help you:

  • See what testpoints are specified on the board.
  • Tells you which nets are compliant and which are not.
  • Helps you work through the nets to achieve compliance.

In Proteus we do this using the testpoints filter in connectivity highlights mode.

Testpoint Viewing Mode.

Depending on your configuration what you're likely to see here initially is a mass of red non compliant nets! Each net will show the required number of testpoints for that net (if any specification has been made) or just the number of testpoints placed if not.

If you set up minimum requirements then the testpoint filter will show you which nets need attention.

If you double click on a net in the parts bin two things will happen. First the net will be selected entirely, including all pads and tracks. Second, any existing testpoints will be tagged in yellow so you can see them.

Net highlight with the existing placed testpoint tagged yellow.

For arguments sake lets assume we want to designate a second pad to be a testpoint (rather than place one). All we need do is right click on a pad or via and select the Testpoint command from the context menu.

Second pad designated as testpoint on the net.

The parts bin at this point will update and the net will show as compliant since it is has the minimum required number of testpoints. We can continue by double clicking on the next non compliant net to tag it.

In summary, if you have set up minimum requirements for nets the workflow to make sure you have sufficient coverage is :

  1. Enter testpoint filter view via connectivity highlights.
  2. Tag the first non compliant net by double clicking on it.
  3. Right click on pads and select testpoint to designate them or place and connect the TP footprint if you are working with schematic terminals.
  4. When the net has the right number of testpoints move on to the next one.

Reporting and Output

It's important to understand that the testpoint filter in the parts bin checks only that the right number of testpoints are placed or designated. If the rest of the net is unrouted for example that's a separate problem which will be highlighted by missing connections in the CRC report. There are several additional reports and output files which can be generated.

Pre-Production Check

This is the most rigorous report (generated from the output menu in the layout module) as it checks the board in general as well as the testpoints. In our example above the pre-production check would fail with a connectivity error if the net was not properly routed.

Testpoint Report

The testpoint report is generated from the Project Notes documentation module. You can modify the information as needed but the template includes the following by default:

  • Data object containing location of each testpoint on the board
  • Data object containing compliance status of each net with specified constraints.
  • Graphic showing location of each testpoint on the board.

PDF output can be generated directly in the Project Notes module.

Example of location and compliance data objects in the testpoint report.

Gerber X2

Gerber X2 files identify testpoints using the TESTPAD attribute. This is included with the Proteus output for all specified testpoints. Note however that testpoints designated on component pads will instead have the COMPONENTPAD attribute as this is documented as higher priority in the specification.

Testpoint Information File

This simple CSV file lists pads which are designated as testpoints on the layout. The X, Y value is the centre of drill hole or pad origin relative to the Output Origin. Vias are only listed if they are exposed through the solder resist.

Print Mode

You can print a testpoint plot using the testpoint mode on the print dialogue form, with the option of including the appropriate silk and copper layers as well.


PRINTER OUTPUT

Overview

Output through standard Windows device drivers is performed using the Print command on the File menu whilst the device to print to may be selected using the Printer Setup command. Context sensitive help is available on all fields within these dialogue forms.

Specifying a Printer Device

You can specify the printer device in one of two ways :

  • Use the Printer Setup command from the Output Menu. All printer settings including the printer device specified will be remembered across ARES sessions and the printer device selected will be the default for future ARES sessions.
  • Use the Printer button from the Print command on the Output Menu. Under these circumstances no printer settings will be retained. This is useful if you want to print to a different printer for a specific design.

Choosing a Layer Set for Printing

The left hand side of the print dialogue allows you to configure the layer set for printing. There are three modes, one for artwork, one for assembly drawings and the third for drill plot. The selection defaults to layers in use but can be changed manually. If you are choosing many layers which will overlap on the paper it may be better to print one layer per page by selecting the checkbox to the right of the layer selector.

Choosing a Colour Profile for Printing

The combo box in the general options allows you to choose a colour profile for the print job. Three colour profiles are provided as standard corresponding to Monochrome (black and white printing), Black Paper and White Paper. You can easily create your own colour profiles through the Displayed Layers dialogue form on the View Menu and these will then be available both for screen usage and in this dialogue form for printing.

Print Preview

The Print Preview appears on the far right of the Print dialogue form and displays the position and size of the schematic relative to the specified paper size. It will ‘live update’ as you configure the dialogue (scaling,colour,etc..) to your requirements.

Print Preview in the Printer output dialogue for

You can adjust the position of the printed area by left depressing the mouse on the print preview and dragging to the desired position. Alternatively, you can choose a preconfigured position by right clicking the mouse on the preview pane and selecting the desired position from the context menu.

Configuring Margins

When not printing all sheets you can manually configure the position of the output within the printeable area. Right click on the Print Preview and select Position Output Numerically and enter the margins that you want between the edge of the printeable area and the edge of the output area. This is, in effect, an absolute method of positioning the output area within the printable area. In general, however, we would anticipate most users to position the output area via the mouse drag method detailed above. The graphical illustration below depicts the use of margins.

Setting the margins manually

If you turn off the option to Use Printer Margins on the context menu the margins you specify will be from the edge of the paper itself. In most cases this is not recommended as, depending on your printer driver, you are likely to lose part of your layout if you position it absolutely at the edge of the paper (outside of the printable area).

Printer Information

The Printer Information option on the Output Menu will dump a log of your printer details and capabilities. This is primarily for support purposes. Whilst our experience of printing support issues is that they are almost invariably the result of a defect in the printer driver we can make a better determination of the problem with the information detailed via this command.


PLOTTER OUTPUT

Overview

Windows support for Pen plotters is, unfortunately, very poor. Although drivers are supplied for HPGL and other plotters, the implementation of these drivers is very sketchy. Better drivers may be available for particular plotters, but we have not relied on this in designing the plotter support within ARES for Windows. Instead, we rely on the Windows plotter driver only to draw straight lines and then ARES itself does the rest. To do this, it uses the plotter driver module from the DOS version. This module allows control of the following options which are adjusted using the Set Plotter command on the System menu.

Plotter Pen Colours

The plotter drivers are able to generate a multi-coloured plot when ALL layers are selected on the Print dialogue form.

The Set Plotter command on the System menu is used to determine the colours for each layer. Where through hole pads are encountered, the pen number is determined by ORing the colours for the outer layers of the pad in the same way as is done for screen colours.

Note that this only applies to an ALL layers plot - single layer plots always use the black pen.

Unfortunately, the Windows plotter drivers do not (as far as we have been able to find out) support the direct selection of plotter pens by number. Therefore it is up to you to find out how your plotter driver maps colours onto pens and to select appropriate colours on the Set Plotter Pens dialogue.

Plotter Tips

On the Set Plotter command form are fields for Pen Width and Circle Step.

Pen width

This is a value in thou which should correspond (at least initially) to the width of pen you are using.

Circle step

This value is the size of step (in thou) that ARES will use when plotting the outer radius of a 1 inch diameter pad. A smaller number results in faster but more jagged circular pads whilst a value of 0 will instruct ARES to use the plotters internal circle drawing command. Whilst this is generally fast and smooth, it does mean that the pen is picked up and put down for each pass round the pad.

Getting high quality plots will require experiment with pens, film, ink, and the settings described above. You may also find it necessary to tweak the sizes of some of the pad, via and trace styles the problem is that there are too many variables outside our control to guarantee that the dimensions of plotted objects will accurately tie up with their nominal size. As a starting point, we recommend a 0.25mm or 0.30mm tungsten carbide tipped pen, professional drafting film (obtainable from a good stationers) and Marsplot 747 ink.

Finally, the Line Width command on the Text Style command form is ignored when plotting a single pass of the pen is used for all silk screen graphics for reasons of speed. If you need a different line thickness, use a thicker pen for your silk screen plots!


Graphics File Installation

GRAPHICS FILE GENERATION

Overview

As well as printing directly to Windows print devices, ARES for Windows can generate output for use by other graphics applications. You have the choice of generating this output as either a Bitmap or a Windows Metafile, and you can transfer the output to the other applications either through the clipboard, or by saving it to a disk file. Context Sensitive Help is provided for the fields on all dialogue forms.

Bitmap Generation

The Export Bitmap command on the Output menu will create a bitmap of the board and place it either on the clipboard or in a disk file.

Exporting a Bitmap

Metafile Generation

The Windows Metafile format has the advantage of being truly scalable where a bitmap is not. However, not all Windows applications (e.g. Paintbrush) can read a metafile.

The Export Metafile command on the Output menu will create a metafile of the board and place it either on the clipboard or in a disk file.

PDF Generation

PDF files are widely recognised and adopted as a standard format for file sharing. ARES can output a PDF of the layout via the Output Menu where you can select layers, specify overlay or separate pages per layer and either colour or monochrome output.

Exporting PDF format

SVG Generation

Scalable Vector Graphics (SVG) is an XML-based vector image format for two-dimensional graphics with support for interactivity and animation. The SVG specification is an open standard developed by the World Wide Web Consortium (W3C) since 1999.

SVG images and their behaviors are defined in XML text files. This means that they can be searched, indexed, scripted, and compressed. As XML files, SVG images can also be created and edited with any text editor.

Exporting SVG Format

DXF File Generation

The DXF format can be used to transfer output to DOS based mechanical CAD applications (it is better to use a clipboard metafile to transfer to Windows based CAD programs). The file is generated by a Labcenter output formatter, rather than by Windows.

Our current experience is of considerable incompatibility and disagreement between applications on what constitutes a valid DXF file. To put this another way, given 6 applications supporting DXF, only about 30% of file exchange pairings seem to work! For Windows work, the Clipboard provides a much more reliable transfer medium.

Exporting DXF format

Overlay Bitmap Generation

The Export Overlay command on the Output menu will create an overlay diagram and place it as a bitmap either on the clipboard or in a disk file.

The overlay image is created by first rendering the copper layers in a ‘tint’ and then superposing one or more silk screen layers on top of this. The effect is to show the positions of the components with the tracking faintly visible underneath.

Exporting Overlay Format


PRE-PRODUCTION CHECKLIST

Overview

The pre-production checklist is an automatic test of your layout for common errors which is normally launched prior to sending the board for manufacture (it can also be launched manually from the Output Menu). We strongly recommend that you resolve any errors that are reported in this check before production of any hardware.

You can disable specific checks for the current session by turning off the appropriate checkbox before running the checklist. This should be done with caution !

The pre-production check is an aid to and not a replacement for manual inspection of the layout and designer approval. Quality assurance responsibilities lie with the board designer – in particular Labcenter always recommend the creation and testing of a physical prototype prior to mass production.

You can copy the results of Pre-Production Check to clipboard using keyboard shortcuts (CTRL+A to select all and then CTRL+C to copy to clipboard).

The following is a list of the checks performed and suggested course of action when errors are reported:

Connectivity

This test automatically runs the CRC, checks and identifies that all connections specified in the netlist have been made.

If this fails, you should launch the Connectivity Checker and double click on entries to locate and then track the missing connections on the layout.

Object Validity Check

This check tests the integrity of the layout objects and should always pass.

If this fails you should contact Labcenter support.

DRC Check

This tests re-runs the Design Rule Checker on the layout.

If the Design Rule Checker is disabled you should enable it from the Design Rule Manager on the Technology Menu.

If you have Design Rule Errors they can be viewed by clicking on the DRC Error report on the status bar at the bottom of the application. Errors can be located by double clicking the mouse on the resulting dialogue form.

Design rules are configured via the Design Rule Manager on the Technology Menu.

You should resolve all DRC errors before moving to manufacture. This may involve setting appropriate design rule for your layout (if you have not already done so), adjusting the layout to conform with the specified design rules or –very rarely – acknowledging the error as an intentional design decision and suppressing it by right clicking and selecting ‘Ignore this Error’ from the resulting context menu.

Zone Overlap Check

This check tests all the power planes on the layout for overlap. Importantly it uses a completely separate algorithm (code path) from the zone placement code in general use and therefore forms a secondary verification on zone integrity.

This test should never fail. If a fail is reported please contact Labcenter support without changing the layout

This test can take some time (several minutes on a large board with many zones).

Duplicate Part ID's Check

Checks that no two parts have the same silkscreen identifier or part reference. If you get this error you should find the two or more parts with the same reference (Using Search & Tag - 'T' keyboard shortcut) and then change such that the part references are all unique. You can do this with the Automatic Annotator (Tools Menu) either globally or just for the selected items.

Unplaced Components Check

This simply checks that all the components specified in the netlist have been placed on the board. If it fails you need to place the components or change the schematic and re-netlist if they are superfluous.

Board Edge Check

This checks that the board edge is present and complete (no gaps). If this fails you should either place a board edge or rework the existing board edge so that it is complete.

Complex board edges in particular should always be drawn with the 2D Graphics Path tool as this guarantees a complete board edge. Curved segments can be drawn by holding down the CTRL key while placing the segment and the outline can be adjusted after placement via the drag handles. Please see the section on the board edge in the tutorial for more information.

Components Outputs Board Edge Check

This checks that components are all inside the board edge and not placed outside and then forgotten about.

Fixing this error involved re-working the layout such that all components are inside the board edge

Hatched Zone Connections

This checks that connecting pads aren't smaller than the gaps in the hatching. If they are you get a warning and are advised to manually inspect or change pad sizes because a poor connection is quite likely.

Length Match Check

This checks that tracks which have previously been length matched have not since been nudged or had their length changed.

When tracks are length matched they are considered internally to be part of a 'matchgroup'. The target length (length of the longest track) and the tolerance (from the length matching dialogue) are stored after a successful length matching operation. This information is then retrieved by the PPC and the target length plus tolerance is tested against the real length of each of the track in it's current state.

This also checks that differential pairs are compliant in terms of length and tolerances defined on the differential pair dialogue form.

The Length Matching report is a good place to review / audit / print length match data used in your project.

Differential Pairs Check

This checks for unrouted differential pairs and then checks whether routed diff pairs violate the max paired or max separation distances.

An error is also produced if the differential pair is deemed indecipherable (e.g. multiple routes, extra pads connected etc.).

You can use connectivity highlights mode filtered to diff pairs to quickly locate them on the layout.

The diff pair in question should then be inspected and corrected to be compliant.

A more rigorous report on Diff Pairs can be generated from Project Notes. This can be helpful in spotting errors.

Layer Stackup Warning

This checks whether a layer stack has been defined for the current board.

Many modern output formats make use of the layer stack and it allows the designer to specify more precisely the way in which they would like their PCB to be constructed. If a layer stack has not been specified the user should do so via the Layer stackup command on the Technology Menu.

See Also:

About Layer Stacks

Via Validation Check

This checks that valid and contiguous via ranges have been specified for the vias on the layout.

If you get an error here you need to edit your via styles and check the layer ranges.

Stitching Via Check

This checks that stitching vias are still connected to two zones. It is possible through routing or object placement to change the area of a flood fill which could 'orphan' a stitching via.

If you get an error here you need to either remove the stitching via or adjust the plane fill such that the location of the via is filled.

This check will only look at stitching/shielding vias placed automatically - it does not check vias placed manually.

Traces Check

Performs a series of checks on the board tracking. Warns if tracking found on unused or plane layers. Errors if zero length segments found or segments' coordinates are too large.

Via Overlaps & Drill Range Check

This checks that via drill ranges used do not cause problems with manufacture of the board. Typically, this happens when you use both blind-top and blind-bottom vias and the drill ranges overlap.

If you get an error here you need to either change the drill ranges to make the board manufacturable with standard processes or speak to your fab house to check if they can produce the board in it's current form.

Via overlaps just means that the normal way of drilling then sandwiching boards isn't going to work. It doesn't necessarily mean this is wrong if you and your manufacturer agree (e.g. laser drilling).

DRC Room Rules Check

DRC room rules checks that all design rule rooms have a rule associated and that all rules which point to a room point to an existing room (that is, the room hasn't been deleted).

Modifications

If you run the Pre-Production Checker (PPC), then close it and make some modifications to the board, next time you open the PPC it will display and Out of Date message to let you know that the PPC has not been run since modifications were made:


GERBER OUTPUT

Overview

The Gerber format, named after Gerber Scientific Instruments Inc., and now owned by Ucamco, remains one of the widely used in the PCB industry as regards specifying PCB artwork.

A photoplotter is essentially the same as a pen plotter except that it writes with a light beam on photographic film rather than with an ink pen on paper. The aperture through which the beam shines can be varied, allowing it to expose a pad in a single flash and a track with just one movement of the plotting head.

In order for a photoplot to be produced (usually by a bureau, as photoplotters are not cheap) it is first necessary to set the machine up with a set of apertures corresponding to the various pad shapes and track widths used on the board. Each different aperture is referenced by a so called D Code in the Gerber file and a table listing D Codes against aperture shape and size must thus be compiled. This table is compiled automatically and then written out as part of the tool information file.

Proteus will automatically dedupe if two pad styles result in the same aperture, and it will only use one D code in this situation. Also, styles which are present in the selectors but not used on the board do not waste table space.

A note on Gerber Versions:

  • The original RS274D Gerber format was deprecated many years ago and is no longer supported in Proteus as it cannot handle the demands of modern PCB design.
  • Extended Gerber, commonly known as RS274X is still widely used and remains supported in Proteus. However, there is only one drill file (layer ranges specified in readme file) generated and there is no netlist.
  • Gerber X2 is the latest output format from Ucamco and is the default option in Proteus. Amongst other benefits, it contains both a bare copper netlist (IPC-D-356A), separate drill files per drill range and plated status. It is also fully backward compatible with RS274X Gerber viewers and integrates with the Proteus manufacturing report.

Gerber RS274X Format

RS274X includes many high level commands and controls that let the creator of the Gerber data specify the photoplot very precisely and therefore represents a full image of the PCB. However, there are several points to bear in mind:

  • Truetype text and bitmaps will be rasterized in the resulting output files to ensure accuracy.
  • The origin for the Gerber co-ordinate system is defined by the Set Output Origin command on the Output menu.
  • Drilling information is exported as a single Excellon drill file with layer ranges identified in a human readable readme.txt file.

RS274X is now an old format and not really suitable where your board implements technologies that are more recent that the standard. In particular, if you work with blind, buried vias, via filling and panelization you should use the Gerber X2 format. Generally speaking, unless you've a good reason not to you should use the Gerber X2 format because it provides more information to your board manufacturer.

Gerber X2 Format

Gerber X2 is the recommended output format in Proteus.

The [image] Gerber X2 format basically adds the ability to attach attributes to the Gerber files. The attributes provide additional information about the image which is also known as “meta-information”. Examples of some of the attributes include:

  • File Function: Is the file the top soldermask or the bottom copper layer?
  • Part: Does the file represent a single PCB, an array, a coupon?
  • Pad Function: Is the flash an SMD pad, a via pad, a fiducial?

These attributes do not impact what the image looks like, however, they do provide the PCB manufacturer with useful information to aid in building the PCB to the correct specifications. Ucamco calls it “adding intelligence to the image”. Additional information such as which pads are via pads allow the CAM operator to properly setup the soldermask for the board. By contrast, in Gerber version 1 this type of information had to be provided in drawings or notes which are manually read and interpreted by the CAM operator. Any oversight or misinterpretation by the operator would ultimately cause errors and delays.

Advantages to Gerber X2 export include:

  • Bare copper netlist included (IPC-D-356A) format.
  • Top and Bottom Assembly Layer data can be included.
  • Improved handling of drilling information.
  • Attribute information included as metadata, providing additional information to manufacturers. For example, a fiducial is explictly defined as a fiducial.
  • Panelization in Proteus requires the Gerber X2 output format as it contains a superior dataset.

Drilling Information Files

Almost all numerically controlled drilling machines in PCB manufacture use the Excellon format, invented by Excellon Industries. The format is very simple, consisting of the (x,y) locations of the holes and T Codes specifying which tools to use. As with Gerber Format, a table is created within the Tool Information File that lists the hole diameter corresponding with each T Code. Proteus handles this in the same way as it handles each Gerber D Code it assigns a new T Code for each new hole size it encounters, and this information is also put in the tool information file.

The handling of drill file data is however significantly different in Proteus between the older RD274X format and the newer Gerber X2 format.

Drill Files

With RS274X there is only one drill file produced (Excellon drill file) and the drilling range is detailed in the accompanying readme.txt file.

With GerberX2 you get a separate drill file for each drill range in the layout. These files are standard X2 Gerber Files, not Excellon drill files. You also get separate drill files for plated and unplated holes.

Slots

With RS274X, In-Pad slots are exported in the drill file. Holes in the board from either the edge layer or the slot layer are output in the profile file alongside the board edge itself.

With GerberX2, In-Pad Slots (from padstacks) are output in the appropriate plated/unplated drill file with AperFunc of ComponentDrill or MechanicalDrill. Holes in the board from either the edge layer or the slot layer are output in the profile file alongside the board edge itself.

See Also:

Mechanical Routing and Slots

Handling of drill holes in RS274X has been left unchanged as a legacy format and is expected to be deprecated entirely in due course. We recommend use of the Gerber X2 format.

In both formats, the drill sizes used are taken from the Drill Hole attributes of the pad styles. Please make sure that the default sizes we have allocated are suitable for your application before having large numbers of boards manufactured.

README Text File

The readme file is exported with all CADCAM formats and provides summary information split into several categories.

The following screenshots are for Gerber X2 format. The exact contents will be output dependant as some features are supported only in certain formats.

File Listing

A checklist of the fileset that should accompany the readme file.

Photoplotter Setup

A summary of dcodes and parameters for photoplotter setup.

It is worth pointing out that if you have any Testpoints on your board that these will appear in the right hand column as TestPad as opposed to ComponentPad.

If a footprint / package pad is also marked as a Testpad, the rules state that it will be marked as a ComponentPad first and foremost. If it is a singular pad (Not part of a footprint) and marked as a testpoint pad in the layout, it will be listed as a Testpad.

Layer Stackup

A tabular listing of the specified layer stackup for the board:

IPC-D-356A Netlist Format

The IPC-D-356 format was designed to define a standard netlist format by which bare board test information can be represented. In the simplest of forms, this means it must be able to store netlist information along with XY coordinates, and even reference designators and pin numbers (if they exist). It is used by PCB manufacturers to bare board test the PCB before assembly and population with components.

In Proteus, the export of the IPC-D-356 netlist is automatically included with the Gerber X2 export fileset.

File Extensions

The file extensions used with Gerber export are:

  • .GBR : Gerber image file.
  • .DRL : Drill file (274X only).
  • .IPC : Netlist file (X2 Only).


CADCAM OUTPUT COMMAND

Overview

All CADCAM output - Gerber files, NC Drill and Tool Information is generated from a single command.

Launch the CADCAM form from the Output menu

The dialogue form allows you to select:

  • A common filestem and location for all files produced. This defaults to the layout filestem but a neat trick is to change it to something like C:\GERBER\MYBOARD such that all files produced will go directly into a location of your choice. You can, should you desire, set a default directory for CADCAM Output files via the System-Set Paths command.
  • Whether you want all the outputted files to be collated in a single zip archive or left as a collection of individual files in the folder of your choice. Depending on your choice you can then opt to automatically launch windows explorer or the zip archive on completion, allowing you to browse the CADCAM files.
  • Which layers you wish to output for the current design. This will be defaulted automatically based on an analysis of what is contained in the layout.
  • Whether the screen X co-ordinate is directed to the CADCAM x co-ordinate (X-Horizontal) or to the CADCAM y co-ordinate (X-Vertical).
  • Whether the newer Gerber X2 or the older RS274X Gerber format is used. Gerber X2 contains several major advantages and is the recommended output format.
  • The option (recommended) to export filled via's (NCVF) in a separate file.
  • What resolution is used for rastering truetype fonts, and bitmaps. A finer resolution will result in smoother edges but can result in the generation of very large files.
  • A Zip File comment. Zip archives allow a comment to be appended to them and this comment appears by default when you (or your board manufacturer) opens the zip archive. This is a useful way to ‘sign’ your archives or to provide special instructions etc. for your board manufacturer.
  • A Tool File comment. This comment, if specified, allows you to add contact information etc. to the readme file generated with the CADCAM output. This readme file also lists all files generated together with the tool settings for the photoplotter and the drilling machine.
  • A comment for manufacturing notes. This comment, if specified, allows you to add design specific manufacturing notes to the readme file generated with the CADCAM output.
  • Whether or not to launch the Gerber Viewer module automatically on production of the CADCAM files. This option will load the CADCAM files into the Gerber Viewer on completion, allowing you to view the resulting output prior to sending the files to your PCB manufacturer for prototyping.

Any files generated from a previous run but now corresponding to a disabled layer are deleted - the new tool information table may be wrong for them.

Finally, context sensitive help is available for all options on the dialogue form, providing detailed information on the functionality of each field..

If you have created a Project Notes document of type Manufacturing Notes you can choose to automatically include a PDF of the document in the CADCAM fileset by selecting the Project Manufacturing Notes option from the notes tab of this dialogue form. See the Project Notes help file for more information.

If you opt to view the resulting CADCAM you will open the Gerber module in View mode. To edit / panelize you must first close the current project and then open the gerber module. See the section on panelization for more information.


MECHANICAL ROUTING & SLOTS

Overview

There are two sets of circumstances in which it may be necessary to form make a non-circular hole within a board:

  • Some components have solder lugs rather than round pins, and these are best mounted on a pad which has a slotted rather than a drilled hole.

This can be achieved by defining a slotted pad-stack. See pad stacks for more information.

  • Sometimes there is a need to make a large cut-out in a board, usually for thermal protection or to accommodate some mechanical aspect of the product design.

This can be achieved by drawing 2D graphics on the slot layer.

It is important to understand how this data comes out and is sent to the manufacturer. The way this is handled depends on your chosen output format:

Gerber X2

- Slots in a padstack are included in the plated drill file of the appropriate drill range unless you specify the padstack to be unplated in which case slot data will appear in the unplated drill file.

- Slots or cutouts drawn manually on the slot layer and the board edge graphic itself are included in the profile file.

Gerber RS274X

- Slots in a padstack are included in the drill file of the appropriate drill range.

- Slots or cutouts drawn manually on the slot layer are included in the slot file.

ODB++

- Padstack slots are exported with other similar drill data.

- Board slots are exported into a slot file.

It is very important to ensure that your board manufacturer understands where the routing information is in the manufacturing fileset. You should tell them this explicitly and discuss with them in advance of manufacture.

See Also:

Slots


GERBER VIEWING

Overview

Since board manufacture and design iteration can be both time consuming and expensive, it is useful to be able to view Gerber files to ensure that all is well prior to sending them to the bureau.

To facilitate this, Proteus includes a Gerber View command which will load and display selected files produced by the CADCAM command.

To view Gerber output files

  1. The Gerber Viewer is part of the application icons. Click on the icon to open the Gerber Viewer in a separate tab.

  2. To open a gerber file, go to the File menu and select Open CADCAM File and load a <file name>-CADCAM READ-ME.TXT.

  3. ARES will then parse the file and display a dialogue form for selecting which layers to view. By default, all available layers are loaded.

The Gerber Viewer will accept both RS274X Gerber and also Gerber X2 filesets, although it will be of far more use with Gerber X2 as it can correctly identify blind/buried vias.

When you export Top and Bottom Assembly Layers with Gerber X2 they will import to the Gerber Viewer as Mech 5 and Mech 6 respectively. You can then control visibility from the View Menu - Layers command.

Editing Gerber Data

Although it is possible to perform editing operations on the Gerber View data, we do not recommend or support this mode of operation, aside for panelization which is discussed in the next section.

Although integrated with Proteus The Gerber module is not the place to make edits to your layout. If you spot something that needs altering or removing then you should do so inside the ARES Editor and then regenerate the Gerber/Excellon files.


Panelisation

PANELIZATION

Overview

Panelization refers to the processes of combining several board artworks onto one panel in order to reduce manufacturing costs. It is common practice to panelize both multiple copies of the same board and/or several different boards.

You cannot edit Gerber Files when you have a project open. You must close the current project, then open the CADCAM module and load the files.

You can only panelize with boards exported in the Gerber X2 output format. Panelization with RS274X is deprecated.

You should create your panel in a single Proteus session because some of the placement offset metrics are not stored in the panel file.

Proteus provides facilities to achieve this by using the Gerber module in Editor mode as follows.

To create a panelized artwork

  1. Use the CADCAM Output command to produce Gerber and Excellon files for each board to be included on the panel.
  2. Close the current project and then open the Gerber Editor.

  3. Set the work area in the editor to be the size of the panel via the Technology Menu - Set Board Properties command. This means the automatic placement and offset will correctly start new rows at the right time. It's important to do this before importing the first panel data !

  4. Go to: File > Open CADCAM File and select the relevant <Project name> - CADCAM READ-ME.TXT file.

    Note that the 'Open' icon will open a project and not a CADCAM file.
  5. Accept the default settings for the layers (these should correspond with the layers you chose to generate at step 1) and check the Panelization Mode checkbox.

  6. Perimeter spacing will be distance from edge of work area, spacing is difference between incoming boards and number of copies allows you to autoplace multiple copies of the same PCB.

    Click OK. The Gerber Editor will import the CADCAM data for the board and display it as a tagged set of objects.
  7. If the panel is to contain images of additional boards, you can import them into the panel by returning to step 2 above.
  8. When the panel is complete place a board edge graphic around all the boards. If you followed step 3 above you will simply be tracing over the blue work area.

  9. When the panel is complete, use the CADCAM Output command to generate final artwork files for the panel. It is these files that you need to send to your board manufacturer.
  10. If you want to, you can save the panel project to disk. It will save with a PDSPNL extension to keep it distinct from an actual design project which has a PDSPRJ extension.

The work area for a panelized design is initialized from the Panel template file. If you find your board manufacturer requires different panel dimension you can change the work area size in ARES and the use the Save As Template command to override the Panel template with the correct dimensions.

You cannot panelize a board while a project is open. A Proteus project is the representation of a single board (schematic, layout, 3D Visualisation, BOM, database, etc.) and a panel is clearly a representation of more than one board. Make sure you close the current project before you enter the gerber viewer module for panelization !

How it works

The auto-placement panelization works very simply by placing the next copy or board at the false origin marker position and then moving the false origin marker by the specified spacing parameter from the edge of the newly placed board. New rows are created automatically when a placed board will overlap the work area which is why it's a good idea to set your work area to the size of the panel.

What this means is that you can override the automatic placement if you need more control over placement. Simply import boards one at a time, positioning the false origin marker to the desired location.

1. Do this by going to the View menu > Goto Position.

2. Set your values and change it to be Output Origin.

3. Where the mouse is (do not move it), press 'O' on the keyboard to set a false origin. Note that a blue marker will appear.

This will ensure that the next board you bring it will be placed where you want. Note:

- The bottom left corner of the incoming board will always be positioned at the origin marker.

- The rotation of the incoming board will be the same as it was in the 2D Layout. Alternatively, you can specify the rotation while exporting the PCB board. It is better to organise rotation before bringing the board into the panel. You can select and rotate after placement in the panel design but at that stage of course you'll need to handle the positioning manually.

There are a number of points to note about the panelization process:

  • You can add additional text and graphics to the panel as required to designate board IDs and other manufacturing information.
  • When importing multiple board images, Proteus will assign new pad and track style codes (D-Codes) for each image. However, when the CADCAM files are re-generated, Proteus will re-combine styles that are actually the same, so that the total usage of aperture and tool codes will not be excessive.
  • The resulting set of files may be quite large - especially if the board contains bitmap logos or lots of true-type fonts (these are rasterized). Fortunately, the files are ASCII, and will compress quite well with WINZIP or similar, should you need to transmit them by email.


Assembly Drawings

ASSEMBLY LAYERS

Overview

Assembly layers contain block representations of the components on the board, along with their reference idents in the middle. They are often used for population of the PCB, particularly when the silkscreen references have been selectively removed due to space constraints.

The Assembly Data

Example of Assembly Drawing.

Assembly data is auto-generated by the Proteus software. The required information is simply:

  • Component Part References.
  • Component Occupancy Definitions.
  • Pin 1 Indicators.

Component Occupancy Definition

The occupancy definition for the part is generated based on the following, in order of decreasing priority:

  1. Contents of the relevant Assembly Layer in the footprint if present.
  2. Contents of the courtyard if present (occupancy layer)
  3. Simple geometric bounding box for the component.

Pin 1 Indicators are applied automatically in cases 2 and 3 above. Where Assembly Layer content is explicitly present it is deemed to be complete and correct and no additions (such as pin 1 indicators) are made by the software.

The occupancy definition is used as the courtyard for the part on the assembly drawing and the component part reference is then centred and oriented inside it.

It doesn't matter if you choose to hide the component part reference on the silkscreen layer.

Pin 1 Indicators

If the component has assembly graphics then no pin 1 indicator is drawn because it's assumed that it exists on the assembly graphic (often pin 1 indication is a chamfer/diagonal drawn on a box corner).

If the component has no assembly graphics then a pin 1 indicator is placed automatically as a small dot. For BGA's it is assumed that ball A1 is the equivalent.

Working with the Assembly Plot

There are two ways to manage and work with Assembly Plots.

  1. Automatic. Don't include assembly layer data in packages but do include an occupancy graphic. This is what happens by default with all imported parts.
  2. Manual. Draw assembly layer data and pin 1 indicator on a decomposed package and then re-make the package into your libraries.

If you draw assembly layer data, make sure to draw everything you want including the pin 1 indicator. If any assembly data exists for a component then Proteus assumes it is all present and correct.

In practise, it's far more likely that the automatic mode is fastest, most consistent and easiest to work with. Note that pin 1 indicators can be removed en-masse (e.g. for non-polarized passives) by adding the ASSEM_NO_MARK property in Design Explorer. This is discussed in more detail below.

However being able to draw custom assembly graphics gives you total control of size and style. You may choose to use this option for the odd part where a simple occupancy graphic is less suitable.

See Also:

Pin 1 Indicators

Drawing Assembly Graphics for a Package

Let's take an example. We have an electrolytic capacitor package for which there is no occupancy layer definition and no assembly layer content. The result is that a simple bounding rectangle is used for the assembly plot which is not ideal.

To override this behaviour we need to add content to the package.

It's a very common mistake to try and edit the component. Must be the package.

So, we switch to package mode as in the picture above, find the part we want and place one where there is space. Then:

  1. Right click on the package and select decompose from the context menu.
  2. Place the appropriate 2D graphic object (e.g. circle) on the assembly layer around the part.
  3. Add a pin 1 indicator if desired.
  4. Drag a selection box around everything, right click and select Make package.
  5. Choose to update all instances on the layout when prompted to reflect your change.

Adding Assembly Information to a part.

It is worth noting that it's extremely unlikely that you will have to do this. As far as we can tell almost all imported parts from our partners include occupancy layer definitions (courtyard) which will be used if no Assembly layer data is present.

While assembly data is included in the data set for most imported parts we have chosen to strip it from the parts in Proteus because:

  • It's inconsistent.
  • It's very often incomplete.
  • It's sometimes completely wrong.

Viewing the Assembly Plot in the Editor

The Assembly plot can be viewed by setting up a colour set in the view layer dialogue.

Open View Layers dialogue either from the View Menu command or, more easily, by clicking on main the status bar.

Press New Button beside the Colour Sets and give a sensible name (e.g. Top Assembly).

Select None to clear all the layers and then turn on Edge Layer, Top Assembly Layer (loose graphics) and also the Draw Component Assembly Checkbox (component Assembly). Assign to a keyboard shortcut (num 4 in our example).

Hit OK to exit the dialogue form and store your settings. The editing Window should now show your Assembly plot.

You will almost certainly want to open up view layers dialogue again and assign your main view (e.g. BLACK PAPER) to number 1 if you haven't already done so. Hit OK to exit the dialogue form again.

You should now be able to switch between views with a keypress. Note that this scheme is highly extendable and extremely useful generally. The reason for assigning number 4 to top assembly view is mostly as I have number 1 as full board view, number 2 assigned to TOP VIEW and number 3 assigned to BOT VIEW where I turn off one side of the board.

Switching back to Assembly view note that:

  • You can add graphics such as dimensions or text directly to the assembly layer.
  • You can add dimenstions, text, legends and so on to one or more mechanical layers and then include them in your Assembly view by checking the appropriate visibility checkbox.

Output of Assembly Layers

If a component is not present ('fitted') in the currently selected Assembly variant it will not appear in the Assembly Drawing.

Manufacturing Output

Assembly layers can be included as standard with both the Gerber X2 and the ODB++ Export formats. When using the Gerber X2 format, they will appear as two extra mech layers in the Gerber Viewer as shown below.

It follows that you can then either view only the required assembly layer by turning off all the other layers in the Gerber viewer or you can disable the Assembly layers while viewing other board data. Layer visibility in the Gerber viewer is controlled either by clicking on the main status bar or from the View menu.

It can be useful to first generate the Gerber X2 fileset and then - if required - output the print/pdf from the resulting Gerber view where you can visualize the output.

Example View of Top Assembly with Mech info in the Gerber Viewer.

Printed/Documentation Output

Assembly plot is a new mode in the output dialogue forms. You can therefore opt to include more data, such as board dimensions on a mechanical layer as well as additional copper features should you need to.

Generating a PDF for top assembly and mech data.

You can also export assembly drawings in the PCB manufacturing report in the Project Notes module.

A small pin 1 indicator is output with the assembly plot but will not be visible if the pads are included in the output because it is often situated under a pad. If you need to see pin 1 indicators you should turn off the relevant copper layer so that the pads don't obscure the indicators. Pin 1 indicators may still be difficult to spot on very small IC's and would be better viewed in a PDF where you can zoom in.

Pin 1 Indicators

First, a recap of how the assembly plot is constructed:

  1. If a component package has any data on the assembly layer then that data is used. The software does not attempt to add to it or take away from it.
  2. If a component package has no data on the assembly layer but has an occupancy definition on the Occupancy layer then that is used as the component courtyard boundary. Proteus will place a pin 1 indicator.
  3. If there is neither assembly data nor occupancy definition then a simple bounding box is used for the component boundary. Proteus will place a pin 1 indicator.

In summary, if you add assembly layer data to packages make sure you add the pin 1 indicator as well, because Proteus will not.

Removing Pin 1 Indicators

In the default situation a pin 1 indicator (or BGA ball A1 indicator) is provided for all components. In the case of non-polarized passives you may want to remove this for clarity. You do this by adding the following property to every relevant component:

ASSEM_NO_MARK=TRUE

Let's look at an example of how you might do it on a design. Start by opening Design Explorer, choosing the search tab and selecting resistors.

Generate a listing of all Resistors in Design Explorer.

This should give you a listing of all the resistors on the design in a grid. Next, view the property columns via the command on the View Menu in Design Explorer. Delete the text in the box and type in the property we want before hitting ENTER to add it.

Adding the property here makes it a column in the grid and therefore allows us to set it's value.

You will notice that an extra column appears in the grid with this property as the column title. All we need to do now is apply the property value. Type TRUE in the first box and then hold the left mouse button down inside the typed cell and drag it down the rest of the cells to copy the value.

Either type, copy and paste or just drag the mouse down to copy the cell results into other grid cells.

That's it. Rinse and repeat as needed. You can also add manually on the schematic by copying the property into the Edit Component text field:

When entering properties manually (i.e. not through Design Explorer) curly braces around the property hide the text on the schematic

Finally,if this is something that you will always want to happen it's worth setting up once in your libraries rather than applying to every design. To do this, open Library Manager, select the library you want and then click on the Edit Library button.

Edit the Library directly in Library Manager.

Now the procedure is very similar to design explorer. Create the property and select it for viewing which will add a column to the grid listing of components.

Then, set one cell value to be TRUE and click drag the mouse down to set the rest of the column values.


PICK AND PLACE FILE

Overview

Proteus incorporates the ability to produce a file for use as a starting point in setting up automatic insertion machines. Essentially this file lists the component layers, positions and rotations in standard CSV (comma delimited) file format.

A file configuration dialogue allows you to make changes specific to the insertion machine that you are using.

Pick and Place configuration dialogue form.

Data

This dialogue section lists the output data in tabular form and is read only.

Output Options

These options allow you to configure what data should be output and in what units.

Columns

You can switch the order of the columns here to match your machine spec. You can also change the names/titles of each column so that they can be identified by your insertion machine.

If you have default column names then they will change on the output as you switch the column order about. However, if you specify custom column names then you must arrange the order of the names manually after you change the order of the columns via the combo boxes. Check the preview at the bottom and make sure that the column names match the column data.

Output Preview

This section shows a live preview of the CSV output.

Generate

Use this button to generate the CSV file. Your configuration settings will be stored in the registry for future use (assuming you typically use the same type of assembly machine).

If a component is not present ('not fitted') in the currently selected Assembly variant it will not appear in the Pick and Place file..

There are a number of points that must be appreciated about this file:

  • The origin for the co-ordinates is the Output Origin - this is the same origin as is used for the Gerber and Excellon outputs.
  • The (x,y) coordinates are quantified in units of 1 thou and represent the centre of the component’s package. This position may or may not correspond to the origin of the component for auto-insertion, but it will be in approximately in the correct place. Our understanding is that this is helpful in that it provides a starting point for manual alignment of the placement head.
  • The rotations are in anti-clockwise values in degrees relative to the orientation of the package when it was defined. Since there is no standard for default orientations of packages these values may be of limited use unless they can be combined with a translation table that is specific to ARES packages including ones you have defined yourself. This is a matter between yourself and whoever is providing the auto-insertion facility.

As far as we are concerned, this remains an evolving and experimental area of the software; a number of users have requested an output file of this nature but there is as yet no industry standard for us to base it on. Any feedback on this issue will be greatly appreciated.


MCAD OUTPUT

Overview

It is increasingly common now to export a PCB fileset for import into mechanical cad software such as Solidworks or Autodesk. This enables case design and review of mounting and ventilation considerations.

Proteus includes full support for both AP203 and AP214 STEP formats as well as the older IGES and STL formats.

Generating MCAD data.

You can also elect to embed the MCAD files into the project file itself so that it can then be shared between computers.

Pre-Requisites

In order to export MCAD data for the PCB, we need to have mechanical models for the parts on the board. This is especially relevant for critical parts such as tall radial electrolytics or connectors. The process for adding mechanical data is covered in depth in the 3D Viewer chapter of this document but basically the requirement is to have an mechanical entry in the 3D Models dialogue form. This can be a STEP or IGES file downloaded from the internet (E.g. www.3dcontentcentral.com) and placed in the MCAD directory of your Proteus installation, or it can be a simple scripted model defining height and pin types for the part.

Specifying an MCAD model for a part.

Normally, you would add MCAD data via the Make Device command to ensure that it is then available for all future projects.

Rules for MCAD Export

Parts which are not present in the currently selected Assembly variant it will not appear in the MCAD output because they are not fitted in this configuration.

The board edge and all holes in the board will be exported.

If a 3D mechanical model exists for a component then that component will be exported.

3D Visual models are ignored completely for MCAD Export.

The board and feature thickness is taken from the Board Properties command on the Technology menu.

The log will warn of parts with no 3D model.

Exporting STEP/IGES Files.


ODB++ Output

Overview

The ODB++ format was developed by Valor Systems and combines the information contained in the Gerber, Excellon, Pick & Place and Testpoint Information outputs into one fileset. The ODB++ database also contains a high level representation of the board in terms of the components, packages and netlist.

There are various advantages in using ODB++ rather than the traditional RS274X Gerber formats:

  • ODB++ is a single, standard format, used throughout the PCB manufacturing industry.
  • All the information required to manufacture the bare board including the layer stackup, tool sizes and hole types is included in the database; there is no need for a human readable Tool Information File.
  • The package types, component placement and netlist information are also included so that pick and place and bare board test equipment can be driven from the ODB++ data.
  • Power planes are represented as polygons rather than being rastered; this results in smaller file sizes especially for boards of large physical size.
  • A free ODB++ viewer is available from Mentor enabling you to validate the output using an independent software package before sending your boards for manufacture.

ODB++ Output is part of the PCB Design Advanced Features Set and therefore requires a licence for PCB Design Level 2, PCB Design Level 2+ or PCB Design Level 3.

Using the ODB++ Output Command

The ODB++ command is similar to the CADCAM output command although there are slightly fewer options.

  • A common filestem and location for all files produced. This defaults to the layout filestem. Note that the ODB++ format is contained in a directory hierarchy, so the filestem determines the root folder of the ODB++ database.
  • Whether you want all the outputted files to be collated in a single zip archive or left as a collection of individual files in the folder of your choice. Depending on your choice you can then opt to automatically launch windows explorer or the zip archive on completion, allowing you to browse the CADCAM files. ZIP file generation is not implemented for ODB++ output at the time of writing (ARES 7.3 SP0). It will likely be released as part of a service pack. You can, of course, create a ZIP file of the database folder from within Windows Explorer.
  • Which layers you wish to output for the current design. This will be defaulted automatically based on an analysis of what is contained in the layout.
  • Which layer is used for mechanical routing data.
  • What resolution is used for rastering truetype fonts and bitmaps. Note that unlike CADCAM output, power planes are represented as polygons and are not subject to rastering.
  • Comment fields for manufacturing notes and contact details. This comment, if specified, allows you to add design specific manufacturing notes to the README.TXT generated within the ODB++ database folder.
  • A Zip File comment. Zip archives allow a comment to be appended to them and this comment appears by default when you or your board manufacturer) opens the zip archive. This is a useful way to ‘sign’ your archives or to provide special instructions etc. for your board manufacturer.
  • Whether or not to launch the Valor Viewer automatically on production of the CADCAM files. This option will load the ODB++ database into the Valor Universal Viewer on completion, allowing you to view the resulting output prior to sending the files to your PCB manufacturer for prototyping.

You will need to download and install the free Valor Universal Viewer before this option will work.


IDF OUTPUT

Overview

The Intermediate Data Format (IDF) is a specification designed to exchange printed circuit assembly (PCA) data between mechanical design and PCB layout. Initially developed in 1992, the IDF format has since become a de facto industry standard.

The format includes all information that is commonly shared among mechanical design, circuit board layout and physical analysis and is directly supported by most MCAD products including Solidworks, although it has now largely been superseded by the STEP/IGES file formats.

Export in this format from the IDF output command on the Output Menu.

Exporting to in IDF format

To generate an IDF fileset for the layout

  1. Select the IDF Output command from the Output Menu in ARES
  2. Specify the job name, directory and optional archive options.
  3. Select the layers to be included in the output - this will default to the layers used in the current project.
  4. Identify the mechanical layer used for slots if present on the layout.
  5. If you want a common solder resist expansion (guard gap) across the entire layout then check the box and set the clearance.
  6. Enter any notes in the log field; useful both to log design specific information and also to identify the slotting layer.
  7. Generate the IDF fileset.

Note that IDF output is fundamentally a 2D format that contains some 3D information. This information is taken from the 3D Visualisation parameters such as height specified for the footprint (right click on package, select make package and switch to the 3D tab). If no 3D information is supplied a default is passed.

The board and feature thickness is taken from the Board Properties command on the Technology menu.


MANUFACTURING REPORT

Introduction

As PCB design becomes more complex and board more intricate, the need to supply additional information to the board house has increased. Proteus has two template reports that can help, namely:

  1. PCB Manufacturing Report
  2. PCB Specification Report.

Both can be accessed via the Project Notes module. Either open the Project Notes module and select the report you want from the template list or, if you already have a note open, select the New Note command from the File Menu to add another one. The module needs to be unlocked to enable the new note command

The PCB specification report is a template for fabrication requirements ranging from materials used to silkscreen colour to testing, quality and packaging requirements. Typically, this would be updated or changed to reflect your corporate guidelines. Meanwhile, the PCB manufacturing document discussed below contains important information about your PCB that is not clear or explicit in the standard Gerber files.

You can include either or both of these reports automatically with the Gerber fileset by selecting Manufacturing and/or Specification Notes from the Notes tab on the CADCAMOutput dialogue form.

Content

The manufacturing report consists of several sections which in turn include data objects with information from the PCB. It's important to understand that these data objects can be inserted / removed as you please and it's perfectly possible therefore for you to create your own custom manufacturing report. With imagery such as artwork in particular you may wish multiple objects showing different views of the board.

Board Stackup

Board stackup is a table that contains material information and thicknesses for various layers and cores on the board. This information is configurable in Proteus via the layer stackup command in the PCB module. The table will generate using the current units (imperial / metric). You can regenerate the table after changes via the right click context menu command.

Layer Stackup

Layer stackup is a visual showing the drill ranges used in the PCB and is essentially the same graphic as you would see at the end of the layer stackup configuration process. Most helpful for multi-layer boards where the choice of construction methods (internal cores vs external cores) impacts on drill ranges. Can be removed for 2-layer PCB's or where no blind/buried vias are used.

See Also:

Layer Stackup

Drill Table

The drill table is a listing of all hole sizes and styles used on the board along with their layer ranges. Of particular interest in the count field which can help identify loose vias for example which may be changeable to a more prevalent via style to save manufacturing costs.

Assembly Drawings

These are artwork drawings for both top and bottom assembly. You can configure layer display for these via the right click context menu or remove altogether if for example placement is only on one side of the board.

See Also:

Assembly Drawings.

Fiducial Positions

The fiducials table contains the co-ordinate locations of all fiducials on the PCB. This information may be useful for your board house if they are commissioned to handle component placement and/or use automatic insertion machines.

Note that Proteus identifies fiducials as pad styles beginning with the word FIDUCIAL (e.g. FIDUCIAL20). If you haven't created fiducial styles or have imported library parts that don't make use of the fiducial styles then they will not appear in this table.

PCB Artwork

The PCB Artwork section of the report by default contains a single view of the board containing all the layers. You can edit the displayed layers as required for your project from the right click context menu command (re-configure project data). For example, a top view might contain only top silk, top copper and top resist.

You can add additional board views by inserting a new PCB artwork data object.

On large multi-layer PCB's a full render of all the layers can result in a very big file size and is unlikely to provide much detail for analysis. Better to have multiple, different views of the board each containing less information.

Customizing the Report

It is perfectly possible to customize the report both in terms of content and style. You can only edit when the note is unlocked - click on the padlock on the top menu.

Data objects can be added via the Insert Menu -> Project Data or directly from the data object icon on the toolbar.

Data objects can be deleted by right clicking on them and then selecting the delete option from the resulting context menu.

From a styling perspective all the colours and fonts are CSS styles. You can edit styles to configure as needed.

Paper size and orientation is configured via the file menu.

Once you've set up you need to identify the note as a manufacturing note so that it can be included with the Gerber files. To do this, edit the note title from the File Menu, change the name and make sure the note type is manufacturing report.

You can only have one manufacturing report and one PCB specification report per project. Other reports will typically be of type generic.

Now, save as template from the template menu to make your report available in future designs.


TESTPOINT INFORMATION FILE

Overview

A common method of testing both bare and assembled boards is to use a ‘bed of nails’ test unit. This device makes connections to a large number of the exposed pads on the underside of the board, and then - in conjunction with a netlist and other information - checks the connectivity between the test-points. If there are any missing components, short circuits or dry joints, these will likely be detected and the board can be pulled out of the production line for repair or rejection.

See Also:

Testpoints

Testpoint Reporting and Output

In order to set up the testing machine, information is required as to the location of component pads on the underside of the board and the electrical nets that they are one. Proteus provides a special output file containing this information.

An example file is shown below:

LABCENTER PROTEUS TESTPOINT INFORMATION FILE

==================--------==================

Testpoint positions for k:\prodev\ares\test.LYT

Fields: ID, Type, X, Y, Net

Units: X, Y - thou

Notes: This file lists pads which are accessible from the bottom

The X, Y value is the centre of drill hole or pad origin.

"Q1:B","THRU",6150,5400,"#00000"

"Q1:C","THRU",6050,5400,"UNREG"

"Q1:E","THRU",5950,5400,"VOUT"

"D1:A","THRU",6200,5250,"VOUT"

"D1:K","THRU",5900,5250,"#00004"

"R1:1","SURF",6350,5250,"VOUT"

"R1:2","SURF",6350,4850,"#00001"

"R2:1","SURF",6450,5250,"#00001"

"R2:2","SURF",6450,4850,"GND=POWER"

"Q2:E","THRU",5650,4950,"GND=POWER"

"Q2:C","THRU",5650,5050,"#00004"

"Q2:B","THRU",5650,5150,"#00005"

"R3:1","THRU",6000,4750,"DIGITAL"

"R3:2","THRU",5600,4750,"#00005"

"C1:1","SURF",6250,4750,"ANALOG"

"C1:2","SURF",6150,4750,"GND=POWER"

"C2:1","SURF",5600,5350,"#00003"

"C2:2","SURF",5700,5350,"#00004"

"VIA","THRU",4650,4550,"#00003"

"VIA","THRU",4550,5700,"#00004"

There are a number of points that must be appreciated about this file:

  • Pads are identified as either <PARTREF>:<PINNO> or “VIA”.
  • Pad types are either “THRU” where there is a drill hole, or “SURF” if not.
  • Only pads and which are accessible from the underside of the board, and which have exposed copper are listed. Pads which are entirely covered by the solder resist are not listed.
  • The (x,y) coordinates are quantified in units of 1 thou and represent the connection point of the pads. This is the point that you track to in ARES in order to achieve electrical connectivity.
  • The origin for the co-ordinates is the Output Origin - this is the same origin as is used for the Gerber and Excellon outputs.

As far as we are concerned, this is an evolving and experimental area of the software; a number of users have requested an output report of this nature but it isn’t entirely clear to us exactly what information is needed. Any feedback on this issue will be greatly appreciated.


Introduction

DXF IMPORT

Overview

The DXFCVT converter is fully integrated into ARES and is driven through the Import DXF tool on the File menu. It facilitates the import of mechanical data in DXF format, and we envisage it being used in situations where a board needs to be fitted into an existing mechanical design. It could also be used to import other graphics such as company logos.

The conversion process is as follows:

  • Generate the DXF file from your mechanical CAD application. This should, if possible, be a 2D drawing. ARES cannot handle 3D data and the converter thus ignores all z co-ordinates in the DXF file so 'flattening' 3D drawings to two dimensions.
  • Determine the mechanical layers in the DXF file that are to be combined and placed on particular ARES layers. The DXF Import dialogue form allows you to specify one or more layer assignments with each assignment specifying which of the mechanical layers in the DXF file are to be combined and placed on the specified ARES layer.

The DXF importer will automatically determine the correct units, provided that they are specified within the input file.

You should appreciate that Autocad (the application around which the DXF format was based) supports much more powerful mechanical drafting than that offered by ARES. Thus some entities in a DXF file are ignored by DXFCVT, and others are approximated. However, for the purpose of displaying simple cabinet internals and the like inside ARES, DXFCVT is quite adequate to the task.

Keep the imported DXF data to the minimum, essential information, particularly if you want to convert it to copper objects during import. Consider splitting into multiple imports if needed.

See the Limitations section for specific information on the limitations of the DXFCVT converter.


Importing

PERFORMING A DXF IMPORT

Generating the DXF File

The DXF file to be imported should be generated by the mechanical CAD application you use. Consult the documentation or on-line help associated with the CAD application to determine how best to do this.

As far our import converter is concerned, the only requirements are that:

  • The file exported by the application be in plain ASCII and not in the alternative binary (DXB) format.
  • AutoCAD is the preferred output version, although other versions should work as well (versions prior to R14 may not contain the dimension units).

Convert to Copper

The Convert to Copper option allows you to bring in graphic lines that will be translated into traces in the Proteus layout. You can also bring in a filled object which will be translated into a power plane object if this option is selected. This provides a really useful method to import antenna designs and other similar route topologies

You cannot bring in nested polygons with convert to copper selected.

Convert to Copper attempts to make traces or zones from imported graphics objects.

To import as copper:

  1. Select a copper layer as the target import layer
  2. Remove any un-necessary layers in the DXF. The simpler the imported data the more likely it is that we can convert.
  3. Select the Convert to Copper checkbox on the dialogue form and proceed with the import.
  4. Assign a net to the imported objects. For zones you simply edit them and assign to net. For traces you should place a pad/via on the end and then route to them from an object on the net.

Importing onto Solder Resist (soldermask) Layers

First, note that you can automatically expose power planes in their entirety via a checkbox on the edit Power Plane dialog form. This is both dynamic (updates as power plane flood changes) and precise and is therefore a much better solution when you want to expose the entire plane.

Exposing resist plane to ensure good contact with custom Aluminium case with cavity for RF isolation purposes.

However, it may be necessary to import a complex shape onto the resist layer to form a solder mask opening. You can do this with DXF import, although nested polygons are not selected.

To import as a resist opening:

  1. Select the appropriate resist layer as the target import layer.
  2. Remove any un-necessary layers in the DXF. The simpler the imported data the more likely it is that we can convert.
  3. Make sure detect closed paths is selected and also select the fill closed paths options. Only filled shapes constitute keepouts on the resist layer.
  4. Import as normal. You may need to change the closing tolerance should your DXF paths not be fully closed.

Layer Assignments

Having generated the DXF file you must now decide on what layer assignments you require. Each layer assignment tells the converter which layers in the DXF file are to be combined and placed on a single ARES layer. The controlling dialogue form is laid out in a fashion that should make this process fairly transparent and Dialogue Level Help is provided for all fields on the form should you encounter any problems.

Note that, for a given conversion, an ARES layer may only be assigned once. An attempt to assign a layer twice will result in an error.

Basic Conversions

To perform a DXF file conversion you need to load the converter with the name of the DXF file to be converted. This process is implicit with ARES in that immediately on selecting the Import DXF tool you will be asked to open the appropriate DXF file. A successful loading of the file will result in the appearance of the DXF Import dialogue form. All available options on the dialogue form are covered via Dialogue Level Help on the appropriate field.

Conversion Errors

With regard to DXF file parsing errors, the converter has been written to be as fault-tolerant as is consistent with reading a DXF file. Parsing errors are only generated when:

  1. The DXF file doesn't contain an ENTITIES section. A DXF file without entities is deemed 'empty', which makes conversion impossible.
  2. The DXF file contains a section (e.g. HEADER, ENTITIES) or an primitive (e.g. LINE, CIRCLE, etc.) that doesn't contain a single record. All sections should at least contain an end-of-section record and all primitives should contain at least one record. This implies the DXF file is corrupted.
  3. The end of a BLOCK entity in a non-BLOCKS section or the end of the BLOCKS section before the end of a BLOCK entity. This implies the DXF file is corrupted.
  4. The failure to extract (parse) data of a type consistent with the group record code. For example a record with a group code of 10 implies an integer value and a record with a group code of 41 implies a floating point value. An error is generated if (regardless of formatting) a value cannot be parsed.

Whenever an error occurs the converter reports the error in the form:

ERROR (000413): Entity Group Expected - EOF found?

and the conversion is aborted.

For file parsing errors, the number of the last line read from the DXF file is shown in brackets after the ERROR keyword (note that the converter reads whole groups - two lines - from the DXF file at a time, and so any error may be on the line indicated or the preceding line). For non-parsing errors, the line number is displayed as dashes.

Conversion Warnings

Apart from errors (described above) all other reports of unusual or possibly erroneous conversion behaviour are treated as warnings. Warnings are not fatal (they do not stop the operation and completion of the converter) but are useful if the resulting region file is not what was expected. In order to be complete, the converter issues warnings whenever it encounters a situation that may or may not lead to unusual region files and this includes any record it reads and discards as being either of unknown purpose or unconvertible. Warnings are only generated if requested (through the Generate Warnings checkbox on the dialogue form).

Warnings are displayed in a similar format to errors (described above) except that the DXF file line number line and message text is preceded by the word WARNING. Generated warnings are available for viewing in the DXFCVT.LOG and DXFINFO.LOG files placed in the current working directory. The DXFINFO.LOG file is generated even if import is aborted before the dialogue form is shown.


Limitations

DXF Limitations

DXF Limitations

The principle limitations of the DXFCVT converter are summarised as follows:

  • DXF files must be in plain ASCII. The converter does not support the DXB binary file format.
  • Three-dimensional DXF drawings are flattened to two-dimensions ('plan' view) by the converter as ARES only supports two dimensions.
  • The entities (alone or as part of a BLOCK entity) supported are the BLOCK, LINE, SPLINE, POLYLINE, LWPOLYLINE, ELLIPSE, CIRCLE, ARC, TEXT, SOLID, TRACE, and INSERT entities. All other entities are ignored and do not affect file conversion. The SOLID and TRACE entities are converted as polygons. In particular, the DIMENSION entity is not supported.
  • Only those attributes of an entity that can be honoured by ARES are converted. Thus text attributes such as font face, weight (boldness) and italic slope angle are discarded and do not affect the file conversion.

Other minor limitations include:

  • Quadratic Bezier curves (1 per quadrant) are used to represent ARCS and ELLIPSES, resulting in a small inaccuracy.
  • Line types (dots, dashes, thicknesses, etc.) are lost. All lines are converted to the standard graphics line width.
  • Colours are lost - all converted entities are displayed in a colour appropriate to the ARES layer they are on.
  • Text styles (from the DXF TABLES section) are ignored. The converter relies (for those attributes it converts, such as rotation, mirroring, etc.) on these attributes being specified as part of the TEXT entity - this is the norm.
  • The conversion of DXF TEXT entities drawn in a proportional text style will convert to a fixed-pitch font in ARES where the width of the characters may result in the overall length of the string in ARES being different to the overall length of the string in the DXF drawing. This may then lead to alignment problems unless the user has made judicious use of the DXF text alignment flags (e.g. text that is specified as fitting between two points).As the ARES text primitive is limited to fixed-pitch characters which only allows for the specification of a character height and character width for the text string, the only way around this problem would be to adjust the ARES character width such that the number of characters in the string multiplied by the adjusted character width is the same as the overall length of the string in the DXF file. Unfortunately, except for certain justifications, the DXF file does not contain the overall string length and so this isn't possible. The actual behaviour of the converter is to calculate the character height as being equal to the height of the DXF TEXT entity and the character width as being equal to the TEXT entity height scaled by the TEXT entity's x-scaling factor (the latter defaults to 1.0).
  • The following text attributes and properties are not converted:
  1. Obliquing angle (for italics).
  2. Styles - all text is in ARES's fixed-pitch vector font.
  3. Control characters. These occur in the DXF file as a caret followed by an ASCII character - all such characters in the string are preserved.
  • The following text attributes and properties are converted:
  1. Rotation.
  2. X and Y mirroring.
  3. Justification, except attribute '5' ("Text is fit [sic] between two points (width varies)") as it is ambiguous and hasn't been tested.
  • Only the following entities are converted as noted.:
  1. LINE and 3DLINE entities.
  2. CIRCLE entities.
  3. ARC entities (by default, by using bezier quadrant arcs).
  4. SOLID, TRACE and 3DFACE entities are converted to unfilled three/four sided polygons. The 'hidden' attributes of 3DFACEs is not honoured.
  5. TEXT entities are converted as described above.
  6. BLOCK entities.
  7. INSERT entities are converted but any associated ATTRIB entities are discarded - this leads to text declared in the INSERT via a ATTDEF entity being lost.
  8. LWPOLYLINE and POLYLINE with associated VERTEX entities. All polylines are assumed to be continuous (i.e. not a mesh) and all VERTEX entities are assumed to be single point or a bulge.
  9. ELLIPSE using bezier quadrant arcs.
  10. SPLINE entities are only supported if they are non-rational (weighting is 1) and or degree 3 or lower. Fit points are not supported.
  • In addition to the above some other omissions are:
  1. DIMENSION entities - these are usually also exported as LINE, SOLID and TEXT entities as well, so there should be no loss of visible information.
  2. ATTRIB and ATTDEF entities, as outlined above.
  3. SHAPE entities - these will (if a problem) be added in a future release.
  • If the DXF file does not specify the units it is the user's responsibility to specify the scaling parameters (via the appropriate options on the dialogue form) scale the dimensions to 1th. Positive angles are assumed to be measured in degrees counter-clockwise from an implied zero axis corresponding to the positive x-axis. The necessary DXF file header variables are checked and a warning issued if this is not the case.

Layer names are honoured throughout out the conversion, with the layer name "0" (the single character zero) being taken to have the layer name of it's parent. For example, for a BLOCK object with entities on layers 0, BLUE and GREEN and an INSERT of the BLOCK on layer RED, the BLOCK entities on layer 0 are deemed to be on layer RED.How the converter determines which entities with a BLOCK are to be output is determined by which layers are enabled and the settings chosen under the Symbols group on the dialogue form.


ICON REFERENCE CHART

Command Icon Chart

New Layout | Load Layout | Save Layout
Import Region File | Export Region File | Print Layout
Print Area | CADCAM Output | Gerber Viewer
Refresh | Flip Layout | Grid On/Off
Display Layers | Metric / Imperial Toggle | False Origin
Z-Theta | Pan | Zoom In
Zoom Out | Zoom to Layout | Zoom to Area
Undo | Redo | Block Copy
Block Move | Block Rotate | Block Delete
Pick Device from Library | Make Package | Decompose Package
Trace Angle Lock Toggle | Auto Trace Style Toggle | Auto Track Necking Toggle
Search & Tag | Auto Component Annotator | Autorouter
Connectivity Rules Checker | Design Rule Checker |

Mode Selection Icons

Selection Tool | Component Mode | Package Mode
Trace Mode | Differential Pair Mode | Via Mode
Zone Mode | Ratsnets Mode | Connectivity Highlight
TH Circular Pad Mode | TH Square Pad Mode | DIL Pad Mode
SMT Edge Connector Mode | SMT Circular Pad Mode | SMT Polygonal Pad Mode
Pad Stack Mode | 2D Line Mode | 2D Square Mode
2D Circle Mode | 2D Arch Mode | 2D Path Icon
2D Text Mode | 2D Symbols | 2D Marker Mode
Dimension Tool | Placement and DRC Rooms | Rotate Clockwise
Rotate Anti-clockwise | Mirror Object | Flip Object


3D Visualization Camera Settings

Overview

This dialogue form allows you to edit the camera settings for the 3D visualization viewer.

Options

Viewing Angle

Specify the angle for the camera against the board. For visibility purposes you are limited to a value between 30 and 60 degrees, although for the vast majority of boards the default value is optimal.

Brightness

Specify the brightness for the camera against the board. Brightness must be in the range of 1 to 99.


3D Visualization Colour Settings

Overview

This dialogue form allows you to edit the colour and transparency settings for the 3D visualization viewer.

Options

Board

Select the desired colour for the current board.

Copper

Specify the colour for the copper on the current board.

Silkscreen

Set or change the silk screen graphic colours for the current board.

Height Plane

Specify the colour for the height plane on the current board.

Resist

Specify the colour for the resist on the current board.

Solder

Specify the colour for the solder on the current board.

Through Holes

Set the colour for the through holes on the current board.

Blind Holes

Set the colour for any blind holes on the board.

Background

Specify the colour for the background on the current board.

Paste

Specify the colour for the paste on the current board.

Percentage Transparency

Specify the level of transparency that you wish for the resist plot.


3D Visualization Dimension Settings

Overview

This dialogue form allows you to edit the dimension settings within the 3D visualization allowing you to see if the components will fit comfortably within your height boundaries and customize the thickness of the board and tracks to your own values.

Options

Board Thickness

Specify the thickness of the board for display in the 3D Viewer. The dimensions of the board are controlled via the placement of a board edge graphic (on the EDGE layer) within the ARES layout package.

Feature Thickness

Specify the amount by which the tracks and silkscreen graphics are extruded from the copper on the board.

Height Clearance (Top)

Specify the height clearance above the board.

Height Clearance (Bottom)

Specify the height clearance below the board.


Align Component

ALIGN COMPONENTS

Overview

This command allows you to automatically align selected objects on the layout according to the set criteria. To select multiple objects for aligning either :

  • Drag a tagbox around the objects.
  • Left click to select an object and then hold the CTRL button down while left clicking to select additional objects.

Try using the Distribute command after the Align command to space out the aligned components (CTRL+D or block select context menu).

Options

Action

This determines what the reference point for the aligning operation should be. You can choose to align to any edge or to center either vertically or horizontally.

Align Point

This combo box allows you to choose between using the Object Bounds, the Pad Bounds or the Pad Centres. This determines which part of the object is considered when aligning in the manner specified through the Action options.


DISTRIBUTE COMPONENTS

Overview

This command allows you to automatically distribute selected objects on the layout according to the set criteria. To select multiple objects for aligning either :

  • Drag a tagbox around the objects.
  • Left click to select an object and then hold the CTRL button down while left clicking to select additional objects.

Use this command together with the Align command (CTRL+A) to neatly space out a set of components.

Options

Action

This determines what the reference point for the aligning operation should be. You can choose to align to any edge or to center either vertically or horizontally.

Distribution Point

This combo box allows you to choose between using the Object Bounds, the Pad Bounds or the Pad Centres. This determines which part of the object is considered when distributing in the manner specified through the Action options.

Snap Distributed Objects

When selected the objects will be distributed precisely and then snapped to the nearest grid point. This will inevitably result in different spacings between objects but, with a small grid, may help with subsequent routing. Generally we'd recommend leaving this option off and certainly the results will not be good with a large grid.


Create New Component

Overview

This dialogue form allows you to create a new component within the ARES library.

Options

Name

Specify the name of the new component.

Value

Specify the value of the new component.

Package

Specify the package to which you wish to assign the new component.


Duplicate Layer

Overview

This dialogue form allows you to duplicate a layer onto another layer, with the ability to duplicate certain sections of the layer.

Options

Source

Specify the layer from which you wish to duplicate objects.

Destination

Specify the layer to which you wish duplicated objects to be placed.

Object types to copy

Specify the object types that you want to duplicate between the given layers.


Mitre Settings

Overview

This command will globally mitre the tracks on the layout in order to avoid solder lugs and minimise track length. It can also be used locally via the right click context menu on a single track or selection of tracks.

See Also:

Mitring

Options

Minimum Distance

Specify the minimum distance from right angle which will be considered for mitring. This is shown graphically below.

Maximum Distance

Specify the maximum distance from right angle which will be considered for mitring. This is shown graphically below.

Graphical representation of the Minimum and Maximum mitre distances

Enforce Minimum Distance in Route Editing?

This command only available on the global version of the dialogue form , launched from the edit menu.

When selected all segment dragging and corner dragging will enforce a minimum corner distance as set by the minimum distance value here. This will apply to both curved route editing and linear route editing. When not selected a default minimum cornering distance applies to editing in order to prevent 90 degree corners.

It is recommended that if you turn this on the minimum distance is left as a value relative to track width.

Cornering Type

Allows you to set either linear corners at 45 degrees as in the picture above or curved corners.

Convert Existing Corners

When selected existing mitre corners will be converted to the specified corner type. When not selected only 90 degree corners will be affected and existing mitres will not be considered.

Not all 45 degree corners are mitres! More information is available in the general mitring topic.


Replicate

Overview

This dialogue form is used to duplicate pads with a specified pitch (or angle) when creating footprints and also to duplicate identical circuitry with an annotation offset. In either case, you must first highlight the object(s) you wish to replicate.

For the latter case, the procedure is basically :

  1. Create subcircuits in ISIS with identical circuit names, thus automatically duplicating the circuitry.
  2. In ARES lay out the first block of circuitry as required. Draw a selection box to tag the whole block.
  3. Use the replicate command and bind to one of the other sub-circuits. Select an annotation offset if you want to provide a new base annotation for the copy.

See Also:

Example: Design Re-use with Replication (Schematic Reference Manual)

Options

The options presented on the dialogue form will depend on whether you are working in cartesian or polar co-ords (View Menu)

Duplication (Cartesian Co-ords)

  • X-Step - Specify the x-offset of the replicated part.
  • Y-Step - Specify the y-offset of the replicated part.
  • Number of Copies - Specify the number of copies that you wish to make of the highlighted part(s).

Duplication (Polar Co-ords)

  • Angle - Specify the angle offset of the replicated part.
  • Relative To - Specify the origin that you want to refer the offset against (normally this is a false origin).
  • Number of Copies - Specify the number of copies that you wish to make of the highlighted part(s).

Example: Placing Circular Pads (Tutorial)

Bind To

This combo-box displays a list of sub-circuits with the same circuitry as the one you have selected. The idea is to select one of the sub-circuits, specify an x-y offset and then duplicate all the circuitry for that channel. If your selection is not entirely encapsulated by a sub-circuit on the schematic this option will be disabled. Not relevant to pad replication.

Re-Annotation

This field allows you to specify an annotation offset and is used only when replicating blocks of circuitry as detailed in the overview. Not applicable for pad replication.


Move To

Move To Command

Overview

This command allows you to move the currently selected object to a specified location and works in both cartesian and polar modes (as selected from the View Menu). You can move either footprints or graphics with this command.

Options

X/Y Co-ordinate

Specify the x/y co-ordinates of the target location to position the part. This will be based on the currently set board origin.

Radius / Angle

Specify the radius and angle to position the part. This will be based on the currently set board origin with +ve x-axis as zero and angle incrementing anti-clockwise.

These options become available in Polar mode as selectable from the View Menu.

Use Origin ?

When selected the component origin will be used as the point to be placed at the destination co-ordinates. This will normally be the center of pin 1 on the component but - where an origin marker has been used during part creation - will be the location of the origin marker. Some imported parts may also have the origin set to the center of the footprint for example. In the case of graphics the origin is the center of the occupancy box for the graphic (the dashed line box that appears when you hover the mouse overt the graphic).

When this option is not selected the location under the mouse at the point of right click will be moved to the specified target. This is meant to give user flexibility to choose a different origin point of a footprint if needed.

You can also edit and rotate the part at any time via the right click edit properties command.


Phase Match Breaks Length Matching

PHASE MATCHING BREAKS LENGTH MATCHING

Overview

This error message occurs when a length match operation has been completed on a differential pair and the subsequent phase matching pass then takes the length matching outside of specified tolerance.

Definitions

Phase matching is the process of matching the length of the two tracks in a differential pair to each other. The shorter track in the differential pair is lengthened to match the other track by the addition of a serpentine segment. The Proteus software will apply phase matching automatically when a diff pair is completed and after a length matching operation.

Length matching is the process of lengthening a differential pair to either a specified target length or to match the length of another differential pair. Both tracks in the differential pair are lengthened by the addition of serpentine segments. Length matching takes place via right click context menu commands on a differential pair track.

See Also:

Phase Matching

Length Matching

The Problem

The two tracks in the differential pair tend to drift in distance as they traverse a corner since the inner track has a shorter distance to travel around the corner than the outer track. Phase matching is then applied to the shorter track at the end of the corner to correct the discrepancy in length.

After length matching is complete phase matching is recalculated as necessary. It is possible that this different phase matching will take the length matching outside of tolerance. When this happens Proteus will apply the phase matching before issuing this error message

The length matching algorithm takes the average of the two track lengths as its value when matching to a target length or as a reference when matching against another differential pair.

Solutions

First, try dragging to reposition the length matching serpentines as this may prevent the issue.

Next, consider tolerances. It may be that either or both or the length match and phase match tolerances are too tight. You may need to prioritize phase matching or length matching by relaxing one of the tolerances but this decision depends on the protocol and the design.

Finally, don't forget about component placement and route topology. The simpler the path the route has to travel the easier any phase matching becomes.


Save Incompatible with Older Formats

SAVE INCOMPATIBLE WITH OLDER VERSIONS

The current release of the software includes feature requests and functionality which necessitate a change to the filing structure of the layout. Older versions of the software cannot therefore load files that have been saved in this version.

An example of this type of feature driven change is the introduction of rounded rectangular pads. This was introduced around V7.6 and involved ARES knowing how to render such geometries. Versions prior to this have no idea how to draw such pads so the loading of a newer design into them would lead to design rule violations and various other issues.

If you absolutely need to save changes for loading into an older version you can use the 'Save As V7.0' filter on the Save As dialogue form. However, you must understand that while such files will load in older versions we will in no way guarantee the integrity of the layout.

In particular, if your layout makes use of features which either did not exist or were implemented differently in Version 7.0 then the layout will be different when loaded into an older version of the software.

Labcenter do not recommend this process for production boards. Responsibility for design integrity lies entirely with the engineer.

Due to the impossibility of maintaining full backward compatibility with older versions of the software, Labcenter does not recommend the design of projects across multiple versions.


Board Statistics

Overview

This dialogue details information on the current layout such as details of entity counts, board dimensions and breakdown of drill hole sizes. You can also export a CSV file dump containing match length information for all routes that have been length matched.

Note that you must have a closed boundary board edge graphic in order for the software to provide dimension information.

See Also:

Length Match Dump


Import DXF

Import DXF File

Overview

This topic covers the import DXF dialogue form settings. For a procedural guide, limitations or troubleshooting information please refer to the DXF Import chapter in the reference manual.

Options

ARES Layer

Specify the import layer for the DXF graphics. This should be set to Board Edge if you are importing a board outline and typically to one of the mechanical layers for general import.

DXF Layers

This is a list of named layers detected in the DXF file being imported. Use the checkboxes beside the layer names to select those layers that you want to import. All selected layers will be brought into the layer specified by the ARES Layer combo box.

Scaling Multiplier

Where the DXF File does not specify units you can apply a scaling multiplier to reference back to 1th. Refer to the procedure guide for more information.

Most DXF files will contain units and therefore this field should not be used. In particular, this setting should not be used to resize data where units are present in the DXF file.

Symbol Mode

Specify what action is to be taken with regard to entities on multiple DXF layers when a conflict occurs with ARES. This happens when an entity is on several layers, some but not all of which are selected to be imported into ARES. The following options are available:

  • All Entities: When enabled all parts of an entity for which at least one part is on a layer selected for import will be imported.
  • Some Entities: When enabled only those parts of an entity which are on a layer to be imported will be imported.

Rotation Options

These options allow you to mirror the design in either X or Y and also to perform a n OCS correction. This applies to 2D DXF paths and surfaces that have been defined in relation to a local planar normal that is not along the z axis, allowing a standard 2-dimensional rotation to compensate for those entities which had a negative z-coordinate in the 3-dimensional mechanical CAD package.

Detect Closed Paths / Closing Tolerance

When selected the importer will detect closed (within tol) paths and import them as single closed paths. By changing the tolerance the importer will detect paths which are fractionally open (within specified tol) and close them.

Fill Closed Paths

Select this option to fill closed paths. This is relevant if, for example, you are importing a closed path onto the solder resist layers since only filled paths are counted as keepouts. This option is automatic when convert to copper is selected since closed paths come in as power planes.

Convert To Copper

This option allows DXF import onto copper layers. Lines are imported as traces and closed paths are imported as power planes. Note in both cases that no net is assigned. For power planes you therefore need to edit and assign the net. For traces you should place a pad/via on the end and then route to them from an object on the net.

General Options

Specify how you want to deal with arcs greater than 45 degrees.

  • Quadrant Arc: When enabled this option will split any arcs greater than 45 degrees into several arcs of 45 degrees or less according to the original angle.
  • Linerarise: When enabled this option will approximate the arc through a series of straight lines. The level of approximation can be determined through the Arc Tolerance field.
  • Tolerance: This field is only enabled when the Linearise Arcs option is checked and sets the level of accuracy for the linear approximation. The lower the tolerance set the higher the accuracy – a value of zero corresponds to the approximation that the midpoint of the straight line is not more than 1 pixel wide of the arc.

Debug Options

These fields control what debug and import information you want to save to file.

  • General Warnings: This option will force the converter to generate warning messages whenever it encounters a situation which may or may not lead to unusual imports. This includes any records that it reads and discards as being of unknown purpose or unconvertible. Enabling this option will slow down the conversion process but may help if problems or inconsistencies occur on the original import.
  • Dump Header: When enabled this option forces the converter to dump the values of a small number of HEADER variables it reads from the header section of the DXF file. The converter itself doesn’t use these values but they may be of use to the user wishing to check the DXF file.
  • Dump Symbol: When enabled this option forces the converter to dump the graphics primitives read for each BLOCK (symbol) entities. This can be useful for debugging block entities that aren’t being mapped or exported correctly.
  • Debug Level: Specifies how much debug information will be outputted.


Save As Template

Overview

This command allows you to save the current board structure and technology information as a tempate for future designs. The following information will be stored in the template file:

  • Board edge definition.
  • 2D Graphics data (e.g. company logo).
  • Single Pads (e.g. Mounting Holes).
  • Technology Data (Design Rules and all other information on the Technology Menu).

If you want the template you save to be the default loaded for new designs then name it DEFAULT when saving.


EDIT ROOM

Overview

A room definition is used to specify an area of the PCB for a particular task such as placement or design rules. This dialogue allows you to configure the room for a particular purpose.

Placement Room Options

Placement Mode

Select what components can be placed inside the room by the auto-placer.

  • Ignore - not used by the auto-placer.
  • Keepout - components not placed inside the room.
  • Any - any component can be placed inside the room.
  • Group - components belonging to a particular placement group can be placed inside the room.

If you select group then the combo box underneath will be enabled allowing you to specify which group you want to place in the area. The hidden checkbox will hide the group name on the layout.

See Also:

Placement Groups and Rooms

Layer

Specify whether the placement room is on top side, bottom side or both sides. This will determine where components are allowed to be placed.

Design Rule Room Options

Overview

First, a quick recap on how to use design rule rooms.:

1) Place the room, give it a name and a layer range.

2) Go to design rule manager (Technology menu) and create one or more design rules that apply to the room.

3) Review the design rules in the design rule manager to confirm that your changes are correct. What you do is select a region on the left hand side (E.g. the room) and the right hand side will show you the design rule or rules that apply inside that region. The following reference manual topics contain more information:

Design Rule Hierarchy (which rules have higher priority over other rules).

Design Rule Rooms

Options

DRC Name

Provide a name for the DRC room. This will appear in the Design Rule Manager dialogue so that you can apply design rules to the room.

Hidden

Choose whether the room name should be hidden on the layout.

Layer Range

Specify a start and stop layer for the room. In some case (e.g. escaping a BGA) setting a room to cover multiple layers is really useful. However, bear in mind that it might complicate the design rule hierarchy Check the room entry on each layer carefully in the design rule manager when you have created your rules.


Block Rotate

Overview

This dialogue form allows you to rotate highlighted items by a specific angle and mirror the highlighted items in the x or y axes.

Options

Angle

Choose the angle at which you wish the selected items to be rotated by.

Mirror X

Check this box if you wish the selected items to be mirrored in the x axis

Mirror Y

Check this box if you wish the selected items to be mirrored in the y axis


Edit 2D Graphics Text

Options

String

Enter the 2D graphics text here.

Justification

Specify what justification you want the text to appear on the layout with.

Graphics Style

  • Line Width - Specify the line width for the 2D Graphics Text. This option is only enabled if you uncheck the Follow Global checkbox. Note that changes made here will only affect the text being edited – you can change the global defaults via the Technology Menu – Text Style command.
  • Follow Global? - This checkbox determines whether the global default value for the line width is to be used for the text being edited. Unchecking this option allows you to configure the line width for the currently selected text.

Font Attributes

  • Height - Enter the height of the 2d Graphics Text.
  • Width - Enter the desired width of the 2d Graphics Text.


Edit Component

Overview

This dialogue form allows you to edit the properties of the component selected.

Options

Part ID

Select the part ID for the component being edited.

Value

Enter the value of the component being edited.

Package

Specify the package which you want to associate with the component.

Layer

Select a layer from the drop down list onto which the component will be placed.

Rotation

Specify a rotation for the component.

Lock Position?

Use this checkbox to lock the component on the layout such that it cannot be moved, rotated or deleted. This is useful if, for example, you have connectors that need to be in a specific position on the board and you wish to ensure that they are not inadvertently moved.

While no visible indication of a locked object is provided on the layout (to avoid clutter) you can find all the locked objects on the board tagging the entire board (right click and drag a box) and then attempt a block operation. From the resulting dialogue box select the option to tag only the locked objects on the board.

Hide Fiducials?

This applies to surface mount footprints which have been defined with fiducial pads and provides a means for suppressing the fiducials on the layout display.


Edit Dimension Object

Overview

This dialogue form allows you to edit the properties of the dimension object in ARES.

Options

Format String

Use this field to format the dimensions and appearance of the measurement. The following options are available:

  • %A - Automatic Mode. This is the default mode and will use the units currently specified in ARES.
  • %M - This syntax specifies that the units for the dimension graphic object are millimetres.
  • %C - Specifies units of centimetres for the dimension graphic object.
  • %T - Specifies units of thou for the dimension graphic object.
  • %I - Specifies units of Inches for the dimension graphic object.

Note that, with the exception of Automatic mode (which will use the units specified for the layout), you can append unit specifiers to the syntax. For example %M mm would designate the units as millimetres and suffix the measurement with the standard unit specifier.

Arrows

These fields are used to configure the appearance and size of the arrows at the end(s) of the dimension object.

Height - Specify the height of any arrows appearing at the end(s) of the dimension object.

Width - Specify the width of any arrows appearing at the end(s) of the dimension object.

Draw Arrow at Start - Specify whether an arrow is drawn at the start of the line representing the distance measured. The start of the line is defined as the position first clicked by the mouse prior to dragging out the dimension object.

Draw Arrow at End - Specify whether an arrow is drawn at the end of the line representing the distance measured. The end of the line is defined as the position clicked by the mouse to complete the drawing of the object.

Graphics Style

These options allow you to configure the graphic style in which the current Dimension Graphic Object is displayed.

  • Width - Specify the desired width of the dimension graphic object. This field is only enabled if the Follow Global checkbox is unchecked. In the default case where this option is checked the width will be as specified via Technology Menu – Text Style.
  • Follow Global? - When checked (the default case) the width will be as specified via Technology Menu – Text Style. If you want to change the width for this specific object uncheck this box and enter the desired width in the edit field above.


Edit Graphics

Overview

This dialogue form allows you to edit line/box/circle/beizer/path graphics.

Options

Width

Enter the desired width for the 2D Graphics object. This option is only enabled when the Follow Global checkbox is unchecked.

Follow Global?

Use this checkbox to determine whether you want to use the global settings for the width of the outline pen or whether you want to specify a distinct line width for the tagged graphics.

Fill Style

This option is used to specify a fill style for the 2D graphics object. Obviously, for things like 2D graphics lines a fill style is meaningless and this option will be disabled for such objects.

This Graphic Only

Exit the dialogue form and apply changes only to the current graphic.

All Tagged Graphics

Exit the dialogue form and apply changes to all currently tagged graphics.


Edit Single Pin

Overview

This dialogue form allows you to edit the properties of the single pin selected.

The Options available on the dialogue form are dependant on whether the pad is part of a footprint and also whether it is part of the netlist. For example, lock position is an option which is promoted to the footprint, not each pad on the footprint. It is however present when you place a loose pad so that - for example - you can lock mounting holes in position.

Options

Layers

Select the appropriate layer from the drop down list.

Style

Specify a pad style from the list provided. If you want to create a new pad style you can do this through the Create New Pad Style command on the Edit Menu.

Relief

Specify the relief type for the pad. This defines what level and topology of connection will be made between the pad and the zone. The default setting means that the relief type will follow that specified in the zone to which the pad will connect. Where one of the thermal relief styles is selected the thickness of the relief stems is defined in the edit zone dialogue (edit the zone to launch).

Drill Hole

Specify whether you would like the drill hole to be plated or unplated.

Minimum Zone Clearance

Specify the minimum clearance from the zone, should the pin not be assigned the same net as the zone.

Net

Use this option to attach a single pin to a particular net. This is intended for use in stitching planes together for RF purposes. Standard connectivity should be maintained through the netlist from ISIS.

Number

Use this field to enter a pin number for the single pin object.

Lock Position

Use this checkbox to lock the pin on the layout such that it cannot be moved, rotated or deleted. This is useful if, for example, you have mounting holes that need to be in a specific position on the board and you wish to ensure that they are not inadvertently moved.

While no visible indication of a locked object is provided on the layout (to avoid clutter) you can find all the locked objects on the board tagging the entire board (right click and drag a box) and then attempt a block operation. From the resulting dialogue box select the option to tag only the locked objects on the board.

See Also:

Example: Specifying the Default Clearance for the Power Plane

Example: Setting the Minimum Clearance for a Pad

Example: Changing the Topology of Relief Stems on a Pad

Example: Specifying the Thickness of Thermal Relief used in Power Plane Connections


Edit Zone

Overview

This dialogue form allows for configuration of a power plane on the layout.

Options

Net

Select the net to which the zone connects. Pads on this net will connect to the zone with short track segments in the style selected by the Relief field. Note that only named nets are listed here. If no net is selected, then the zone will connect to pads whose Relief checkboxes are set.

Layer/Colour

Specify the layer on which the zone is placed. This can be any copper layer.

Zone Type

This combo-box allows you to specify either a normal zone (default), an automatically dimmed zone or a custom dimmed zone (enables the custom colour configuration option below).

Boundary

Specify the trace style in which the inner and outer boundaries of the zone are drawn. This also determines the thinnest section of copper by which the power plane can make a connection. Setting this larger will prevent the copper flowing through small gaps (e.g. between pins) but making it smaller means that connectivity may be made only by thin sections of copper.

If the zone is hatched, the boundary style is also used for the internal hatching.

Custom

This option is only enabled when a ‘custom’ dimming selection has been specified above. This will launch a colour specification dialog which will allow you to choose a custom colour for the current zone.

Relief

Specify the trace style with which thermal relief connections to component pins are made. Connection to vias are by direct contact.

Do not use a relief track style that is larger than the boundary thickness or the reliefs may 'stick out' of the boundary.

Hole Shape

You can change the hole shape around circular pads from the default octagonal shape to more closely approximate a circle. The global curve tolerance will apply and you may still notice minor notches around small pad openings.

Type

Choose from either Solid, Hatched or Empty.

Solid and Hatched zones should be self-explanatory - the step for the latter being definable by the Step field. A diagonal hatch will result in a cross-hatch (sometimes called a mesh hatch).

Expose Solder Resist ?

The solder resist on the plane can be removed over the plane area to enable a good contact with an aluminium case with cavity for the purposes of RF isolation.

See Also:

Defining a power plane on part of a layer

Empty zones are intended to be used for creating holes or keepouts in other zones.

See Also:

Defining a keepout area inside a power plane

Compatible zones are simply dumb blocks of copper and will not step away from pads/tracks according to design rules. Zones of type compatible are typically only generated with the standard features packages (PCB Level 1+ or lower) as these packages do not allow multiple planes per layer. Compatible zones are not suitable for general use.

Step

When the zone type is set to be hatched this option allows you to specify the ‘heaviness’ of the hatching.

Clearance

Use this field to override the design rule clearances for the power plane. Any border of the power plane is deemed to be a track for the purposes of design rules and clearances. By default therefore, the clearance between a power plane and a pad is the pad->trace clearance for the currently enforced design rule and the clearance between a power plane and a track is the trace->trace clearance of the currently enforced design rule.

You can instead set a clearance value here to apply between the border of the power plane and other objects on the PCB. If you do so the actual clearance will be the largest (safest) of the two competing values, namely the one set in the field and the relevant design rule clearance.

We'd recommend that, unless you have good reason, you use the design rule system to manage the clearances for the power planes. Setting this field on a plane is a secondary option where you cannot easily achieve the clearances you want with design rules. Nothing in the software will tell you which clearance is in force so having a mix of zone clearances and design rule clearances can quickly become confusing for the unwary.

Relieve Pins

When checked pins on this zone will have thermal relief as specified in the Relief field. When unchecked no pins on this zone will have relief connections unless specifically set through the Edit Pin dialogue form.

Exclude Tracking

If checked, the zone will treat tracks on its own net as obstacles. Otherwise the zone flows over such tracking, effectively ignoring it. Tracks on other nets, or loose pieces of track on no net are always treated as obstacles.

Lock to Boundary

When checked, the zone will maintain it's pullback from the board edge (as set from the design rule manager -> Edge clearance rule) when the board edge is moved or adjusted.

If you select lock to boundary on a partial plane it will resize the plane in order to lock it to the board edge boundary !

Exclude Board Edge

When checked the board edge will be considered an obstacle and stepped away from by the Edge/Slot clearance in design rule manager.

You can create additional rules that apply on a single layer, meaning you can easily have different edge clearances for different power planes if required.

Suppress Islands

An island is defined as an area of copper in which no connection exist. Suppressing islands therefore ensures that power plane coverage is limited to areas where connections can be made on the layout.

Allow Nesting

This option allows for creation of inner zones in the case where the zone flow is blocked by objects on the layout (e.g. inside an SMT footprint). It follows that, together with the Suppress Islands checkbox, you can control the level of coverage of the power plane on the layout.

For the auto-router to connect to a zone it must be placed on a plane layer.

The clearance from a zone to the board edge is defined by the Edge design rule which can be set (per layer if need be) via the design rule manager in the Technology menu.

See Also:

Power Plane Examples: Specifying a Plane Layer

Manual Routing Examples: Routing to a Zone


Set NFP

Non-Functional Pads

Overview

A non-functional pad is a pad in a printed circuit board that is not connected to a track on the layer it is on. The copper annular ring is therefore redundant on that layer and can be removed to make space.

Options

Remove/Restore Unused Pads from Vias

Depending on the selection this will remove all unused pads (non connected annular rings) from the via, except for those at the extremities of the drill range.

Apply to Selected Vias Only

When unchecked the specified action will apply to all vias on the board.

See Also:

Non Functional Pads


Set Via Filling

Overview

This command allows you to control the filled status of vias on the board. It is normally launched from the context menu on a block selection to specify the vias as filled.

Filled vias in this case means category 7 (VII) of via protection in IPC-4761 - both filled with epoxy resin and capped.

See Also:

Via Tenting and Filling

Only through hole vias can be marked as filled.

Your board manufacturer will need to know the thickness of the board to accurately determine the amount of resin per hole. Make sure your stackup definitions are correct for things like core thicknesses or have a discussion with them before production begins.

Action

Set vias as Resin Filled

Marks all selected vias as filled. If the 'Apply to Selected Vias' is unchecked the action will apply to all PTH vias on the board.

Unset Via Filling

Removes the via filling attribute from all selected vias. If the 'Apply to Selected Vias' is unchecked this provides a quick way to reset the status of the entire board.

An individual via can have it's filled status enabled or disabled via the Edit Via Properties command on the context menu when right clicking on a via.


Stitch / Shield

STITCHING OR SHIELDING WITH VIAS

Overview

This dialogue allows you to configure the automatic stitching of two power planes with vias or the shielding of a plane or route with a line of vias. Shielding will place a 'perimeter row' of vias around the border of the power planes while stitching will populate wherever possible (according to current design rule configuration).

Options

Layers

Specify the source and destination plane to stitch. The source will be disabled (has been used to launch the dialogue form) and, unless you have a complex multi-layer board, the destination plane will be pre-loaded in the right hand combo box.

Via Style

Specify the via style to use for stitching. If you want a particular drill size, soldermask or annular ring for stitching vias then you will need to create a new via style.

Drill Range

You can specify the use of smart vias which will automatically set their drill range to be the smallest possible connecting the two planes and compliant with your drill pass setup. Alternatively, you can choose to use simple thru-hole vias.

See Also:

Smart Vias and Drill Passes.

Via - Via Spacing *

Set the spacing between the via's depending on how populous you want the stitching to be.

Via - Trace Spacing or Via - Zone Edge Spacing *

If you are shielding a route this defines the distance from the via to the route edge. If you are shielding a zone then this is the distance from the border of the power plane to the vias.

Note that with a thin plane (E.g. for shielding a microstrip route) you will need a small edge gap otherwise no vias can be placed.

Offset Rows

Offset each row against the previous one to make a staggered grid of vias. This option will be disabled for shielding where only a single perimeter row of vias is generated.

*Spacing Rules

The spacing situation for stitching zones is not immediately obvious.

The crucial point is that if there are n rows of vias with a fixed gap between them, then the distances from the vias to the boundary are not freely adjustable. Put another way, the via->edge spacing needs to be a minimum and not an absolute.

Example:

Let's say the vias are 1mm in diameter and the required distance between them is 1mm, then two rows will take up 3mm. If a zone is 4mm high and a 1mm gap between the zone boundary and the vias is specified then we have a problem: 2 rows won't fit (3mm + 1mm clearance (top) + 1mm clearance (bottom) = 5mm) meaning only one row can fit with a clearance of 1.5mm (4mm - 1mm (via diameter) / 2).

Summary

It is the Minimum distance from the zone edge. So if you set 1mm, it doesn't mean that it will be 1mm from zone edge to via edge, it means it will not place a via inside that distance.

Here 1 & 2 (hoz) are the same distance appart as are 3 & 4 (vert). 1 may not be the same as 3 but both will be at least 1mm


Compile to Library

Compile to Library Dialogue

Overview

Select the library into which all placed components will be stored. Note that components must be untracked for this operation to be successful.


Create New Padstack

Overview

Create a customised pad for use on the PCB. Padstacks give you greater control over typical pad characteristics such as resist/paste sizes, hole shape and copper size per layer.

Options

Name

Specify the name of the new padstack you are creating.

Initial Style

Select the initial style for the padstack from the drop down list.


Edit Edge Connector Pad Style

Edit Edge Connector Pad

Overview

This dialogue form allows you to edit the features of your edge connector pads.

Options

Name

Enter the name by which you want the pad style to be known.

Width

Specify the width for the pad style being edited.

Height

Specify the height for the pad style being edited.

Radius

Specify the radius for the pad style being edited.

Guard Gap

Specify the distance by which pad radii will be enlarged when output is produced in RESIST mode. If the value is less than 0 (e.g. -1) then you will end up with a negative soldermask for this pad style. For PTH pad styles and vias you can specify the guard gap as not present to remove the pad from the solder resist artwork entirely. You can create new pad styles using the New Pad Style command on the Edit menu. There is no way to delete pad styles once they have been created.

Changes

Specify whether you want the changes to be local to the design or persistent through all future designs.


Edit Circular Pad Style

Edit Circular Pads Dialogue

Overview

This dialogue form allows you to edit the features of your circular pads.

Options

Name

Enter the name by which you want the pad style to be known.

Diameter

Enter the diameter of the outside dimension of the circular pad. That is, the diameter of the pad itself and not the diameter of the drill hole.

Drill Mark (PTH Versions)

Specify the diameter of the hole produced in the pad when output is printer or plotted other than in DRILL mode. This will usually be smaller than the drill hole, as its purpose is to locate the drill bit.

Drill Hole (PTH Versions)

Specify the diameter of the drill tool that will be selected by the CADCAM output command. Also the diameter of the centre hole on artworks produced in DRILL mode.

Paste (SMD Versions)

Specify whether you want paste mask to be present or not. When defined the default is that the paste mask has the same size as the pad, although you can make is smaller by applying a shrink percentage. When not defined, there will be no paste mask at all. You can create your own paste definition for the pad by using solid 2D graphics objects on the appropriate paste layer. This allows you for example to define a stipled paste mask on a large thermal pad. This is shown in a tutorial movie on our website or Youtube Channel.

Guard Gap

Specify the distance by which pad radii will be enlarged (the annular ring) when output is produced in RESIST mode. If the value is less than 0 (e.g. -1) then you will end up with a negative soldermask for this pad style. You can specify the guard gap as not present to remove the pad from the solder resist artwork entirely. You can create new pad styles using the New Pad Style command on the Edit menu. There is no way to delete pad styles once they have been created.

Changes

Specify whether you want the changes to be local to the design or persistent through all future designs.


Edit DIL Pad Style

Edit DIL Pads Dialogue

Overview

This dialogue form allows you to edit the features of your DIL pads.

Options

Name

Enter the name by which you want the pad style to be known.

Width

Specify the width for the pad style being edited.

Height

Specify the height for the pad style being edited.

Corners

Specify either Rectangular, Chamfered or Rounded corners for the pad. When chamfered or rounded is selected, the radius field then defines the amount of clipping. Note that to output these objects for manufacture you need to use RS274X gerber format.

Drill Mark

Specify the diameter of the hole produced in the pad when output is printer or plotted other than in DRILL mode. This will usually be smaller than the drill hole, as its purpose is to locate the drill bit.

Drill Hole

Specify the diameter of the drill tool that will be selected by the CADCAM output command. Also the diameter of the centre hole on artworks produced in DRILL mode.

Guard Gap

Specify the distance by which pad radii will be enlarged when output is produced in RESIST mode. If the value is less than 0 (e.g. -1) then you will end up with a negative soldermask for this pad style. For PTH pad styles and vias you can specify the guard gap as not present to remove the pad from the solder resist artwork entirely. You can create new pad styles using the New Pad Style command on the Edit menu. There is no way to delete pad styles once they have been created.

Changes

Specify whether you want the changes to be local to the design or persistent through all future designs.


Edit Padstack

Overview

This dialogue form allows you to edit the features of your padstack.

Options

Name and Type

Specify the name of the padstack and the padstack type. Enter the name of the padstack in the textbox field and check the box for the desired padstack type.

  • A padstack cannot have the same name as a pad style used within the padstack.
  • Using an SMT padstack will allow you to control the paste mask dimensions for the SMT pad.

Top Side

These options allow you to configure the Copper, Resist and Paste for the top side of the board. When creating SMT padstacks you must use these options regardless of whether you wish to use the top or bottom copper.

  • Copper - Specify the pad style for the copper layer.
  • Resist - Specify the pad style for the resist plot.
  • Mask - Specify the paste mask size for the pad.

The mask option is only available for SMT padstacks.

Bottom Side

These options allow you to configure the Copper, and Resist for the bottom side of the board. These options are not available for SMT padstacks where you must create the padstack on the top side.

  • Copper - Specify the pad style for the copper layer.
  • Resist - Specify the pad style for the resist plot.

Drill Hole

Specify the drill hole and drill mark in these fields (only enabled when Drilled is selected):

  • The Drill Mark specifies the diameter of the hole produced in the pad when output is printer or plotted other that in DRILL mode. This is normally smaller than the Drill Hole as it’s purpose is to locate the drill bit.
  • The Drill Hole specifies the diameter of the drill tool that will be selected by the CADCAM output command. This is also the diameter of the center hole in artworks produced in DRILL mode.

Slot

Specify the Height, Width and Tool to be used for the slot.(Only enabled when Slotted is selected).

Inner Layers

Specify the pad styles for those layers for which you require pad clearances.

Changes

These options allow you to specify the scope of the changes you have made to the padstack. A local change is not persistent outside the current design but a global change (Update all Instances) will persist in all future designs.


Edit Square Pad Style

Edit Square Pads Dialogue

Overview

This dialogue form allows you to edit the features of your square pads.

Options

Name

Enter the name by which you want the pad style to be known.

Square

Specify the size of the square pad being edited.

Drill Mark

Specify the diameter of the hole produced in the pad when output is printer or plotted other than in DRILL mode. This will usually be smaller than the drill hole, as its purpose is to locate the drill bit.

Drill Hole

Specify the diameter of the drill tool that will be selected by the CADCAM output command. Also the diameter of the centre hole on artworks produced in DRILL mode.

Guard Gap

Specify the distance by which pad radii will be enlarged when output is produced in RESIST mode. If the value is less than 0 (e.g. -1) then you will end up with a negative soldermask for this pad style. For PTH pad styles and vias you can specify the guard gap as not present to remove the pad from the solder resist artwork entirely. You can create new pad styles using the New Pad Style command on the Edit menu. There is no way to delete pad styles once they have been created.

Changes

Specify whether you want the changes to be local to the design or persistent through all future designs.


Library Manager

Library Manager Dialogue

Overview

This tool is used to manage your own user libraries, enabling you to create libraries and copy footprints between different libraries. It is important that you do not copy your own parts into the Labcenter system libraries as they will be overwritten on installation of a new version (to enable library updates). System libraries are read only by default to prevent this from happening.

Options

Source and Destination Libraries

The Source or Primary Library and the Destination or Secondary Library are the libraries used as the source and destination of objects in operations such as Copy, Delete, etc., and as the library for operations such as Pack Library, Delete Library, etc.

The Source or Primary Library is the library that last received the input focus; clicking on one of the two library list boxes causes that list box to become the Source (Primary) Library and the other list box to become the Destination (Secondary) Library. The text at the top of the list box indicates which list box is which, and the large black arrow between the two gives the sense of direction to the Copy and Move commands.

The library list boxes allow for multiple-selection of items: clicking the left mouse button on an item to select it, clicking on a selected item un-selects it.

The text at the top of a library list box indicates whether the specified library is read-only. Read-only libraries can only be used as a Source or Primary Library - you can still select a read-only library as a Destination (Secondary) Library, but the buttons that affect the library (e.g. Copy) will not be enabled. The text at the bottom of a library list box indicates the number of items in the library and the number of remaining entries in the library index.

Order

This button will launch a separate dialogue box which will allow you to specify the ordering of the available libraries.

Select All

This button is used to select all of the objects in the source library for copying moving or deleting.

Unselect All

This button is used to clear any objects that may have previously been highlighted for copying moving or deleting.

Copy Items

The Copy Items button copies the selected objects from the Source Library to the Destination Library. A percentage indicator on the right of the window indicates progress. The copy process stops once all the selected objects have been copied or when the destination library becomes full.

You can only copy objects to a writable (i.e. non read-only) Destination Library that is different to the Source Library

Move Items

The Move Items button moves the selected objects from the Source Library to the Destination Library. A percentage indicator on the right of the window indicates progress. The move operation is done in two stages: an object is first copied to the destination library and then it is deleted from the source library. The process stops once all the selected objects have been moved or when the destination library becomes full. Objects are only deleted from the source library after being successfully copied to the destination library - so if the destination library becomes full, those objects not yet moved are left in the source library.

You can only move objects from a writable (i.e. non read-only) Source Library to a writable Destination Library that is different to the Source Library.

Delete Items

The Delete Items button deletes all the selected objects in the Source Library. Note that deleted items cannot be recovered. You can only delete objects from a writable (i.e. non read-only) library.

Rename Item

The Rename Item button allows you to change the name of the last selected item in the Source Library. You can only rename objects in a writable (i.e. non read-only) library.

Information

Provides information about the current library and highlighted object, including date at which the object was last modified.

Dump Library

The Dump Library button displays a form containing the library information as well as the headers and properties for any selected library objects.

ADI Library

ASCII Data Import allows you to assign given properties to particular objects according to whether their existing properties match certain test conditions. In ISIS III ADI can be applied directly to libraries as well as design files. Selecting ADI Library asks for the name of an ADI file to apply to the selected components in the source library.

Backup Libraries

Create a backup copy of the source library.

Create Library

The Create Library button allows you to create a new library. You are prompted to enter the maximum number of objects the new library will be able to hold. These values cannot be changed after the library has been created and there is no (reasonable) limit to the values you enter. The new library is initialized empty and writable (that is, with its MS-DOS or network read-only file attribute not set).

Delete Library

The Delete Library button allows you to delete the current Source Library from disk. Note that you cannot undelete a deleted library! You can only delete a writable (i.e. non read-only) library.

Pack Library

The Pack Library button packs the current Source (Primary) Library. The existing library is renamed to a .BAK file. You can only pack a writable (i.e. non read-only) library.

File Attribute

Change the read/write status of the current library.


Make Package

Make Package Dialogue

Overview

This dialogue form allows you to create your own packages from the selected objects within the ARES viewer if the packages are not currently available within the library.

Options

New Package Name

Enter the name for the package being created.

Package Category

Specify a category for the package being created. You can select an existing category via this drop down list or create a new category for your package via the button to the right. An entry in this field is mandatory as it enables the package to be indexed such that it can be easily picked via the Browse Libraries command.

Package Type

Specify a type for the package being created. You can select an existing type via this drop down list or create a new type for your package via the button to the right.

Package Sub-Category

Specify a subcategory for the package being created. You can select an existing category via this drop down list or create a new category for your package via the button to the right. While not required, taking a little time at this stage to specify a relevant subcategory will save you time later when searching/browsing the libraries for the part.

Package Description

Enter a description of the package being created. It is important here to think of search terms that you might use to describe and find this part – the better the entry here the faster and easier it will be to locate the part by simply typing in a search term in the Browse Libraries dialogue form.

Advanced Mode (Edit Manually)

This option switches the dialogue into advanced mode, allowing you to simply type in the relevant fields by hand. While experienced users may find this more convenient it is more prone to typing errors and we recommend that this option be disabled by default.

Save Package to Library

Specify the library into which you want the package to be stored. Note that only libraries with write access will appear in this selector. You can change the attributes of a library via the Library Manager, although you should never make any system libraries (those shipped with the software) writeable.

3D Mechanical Model

This dialogue lets you specify and position an MCAD model for your footprint. Both STEP and IGES formats are supported. Alternatively, you can create your own geometric model using the simple Labcenter scripting language. This is discussed in the 3D Viewer section of the reference manual.

See Also:

Importing STEP or IGES Models

Writing Geometric Models

A live preview on the right hand side aids positioning of the MCAD file and serves as a guide during creation of geometric models.

3D Visual Model

This dialogue form allows you to create your own 3D components for the 3D real world visualisation from the dimensions of your component in ARES and model parameters entered into the model parameters window.

  • Model Parameters - This pane is where you enter the syntax to create your 3D component e.g. TYPE, MAXHEIGHT, LENGTH, COLOUR, RADIUS, etc. Please see the manual for more information on the syntax and how to build 3D components.
  • Angle of View - There are five different camera angles you can view your 3D component from choose from front, back, left, right or have the component spinning.
  • Live 3D Preview - This pane shows you a preview of what your 3D component will look like from the model parameters you have entered, please note that it has a live update feature, therefore the shape and dimensions will change as you enter your model parameters.

See Also:

Geometric vs Mechanical Models


Make Symbol

Make Symbol Dialogue

Overview

This dialogue form allows you to create your own symbols from the selected objects within the ARES viewer if the symbols are not currently available within the library.

Options

New Symbol Name

Enter a name for the new symbol being created.

Library

Select the library into which you want to store the new symbol.


Create New Pad Style

Create New Pad Dialogue

Overview

This dialogue form allows you to create your own pad styles from the selected pad shape within the ARES viewer if the pad styles are not currently available within the library.

Options

Name

Enter a name for the pad style being created.

Normal

Select one of the provided options to determine the type of through hole pad style being created.

SMT

Select one of the provided options to determine the type of surface mount pad style being created.


Create New Trace Style

Overview

Create a new track for use in the layout. Track styles can be assigned to net classes via the Design Rule Manager (Technology Menu) for auto-selection during routing or simply selected manually by the user when in track mode.

Options

Name

Enter the name for the trace style you want to edit.

Width

Specify the width for the trace style being edited.

Changes

Specify whether you want the alterations made to be local to the current design or persistent through all future designs.


Pick Packages

Pick Packages Dialogue

Overview

This dialogue form allows you to search the ARES library for prebuilt packages and add them to your package list on the left of the ARES viewer.

Options

Keywords

Search for library part(s) by keyword. This method is ideal if you want one (or more) components of a specific type. Examples of possible searches include ‘QFP’, ‘Perimeter Matrix BGA’, ‘right angled connector’, ‘Electrolytic Capacitor’ etc. Search results can then be refined by using the Category, Type and Subcategory fields below.

Alternatively, you can use keywords to refine a search in which you have already specified categories. For example, if you select the SMTCHIP category and the ‘Ceramic Flat Pack’ subcategory you could then refine the search by entering ’28 pin’ in the keywords field.

Note that you can use the TAB key to move from the keywords field to the list of the results, the UP/DOWN arrow keys will navigate through the results, and the ENTER key will select the currently highlighted result into the schematic and exit the form.

Match Whole Words?

This option enforces a full word match on the description field. For example, a search for ‘QFP’ may yield results for ‘SQFP’, ‘CQFP’ etc. (the ‘QFP’ being contained within the word collector) but a whole word only search will eliminate such matches from the results list.

Category

This field displays a list of categories according to the following rules:

  • If a keyword search has been entered then the category list will contain all categories containing results from the search. You can then select a category to refine your search.
  • If no keywords have been entered the category list displays all available categories. Selecting a category in this case will display all results for that category. Typically you would use this mode (together with the subcategory listbox) for non-specific browsing.

The unspecified category contains all library parts for which no indexing information has been provided. For example, if you have created your own library parts and they have not been indexed they can be found by selecting this category.

Type

This field allows you to refine a search to a specific type of footprint (typically SMT or PTH). Where a category has already been selected (or a search term has been typed in) only those types contained within the search results will be displayed in this listbox.

Sub-Category

This field displays a list of subcategories pertaining to the currently selected category. This works in one of two ways :

  • If you have entered a keyword search then the listbox will display all subcategories for the currently selected category where the subcategory contains results matching the textual search term entered.
  • If no keywords are entered the listbox will display all available sub-categories under the currently selected category.

In either case if no category is currently selected then the subcategory listbox will be empty.

Package Preview

This field displays a preview of the currently selected footprint. The previews field will be blank until a part is selected within the results list.

Results

This is the main display window for search results. The names and textual description of parts matching the search criteria are displayed here - additional information can be added or removed from the display by clicking right to display a context menu. To select a part(s) into your just design double-click on the part(s) within the results list.

The results can be ordered by column information by clicking on the column names at the top of the list view.


Edit Polygonal SMT Pad Style

Edit Polygonal Pad Style

Overview

This dialogue form allows you to edit the features of your rectangular or polygonal surface mount pads.

Options

Name

Enter the name by which you want the pad style to be known.

Width

Specify the width for the pad style being edited.

Height

Specify the height for the pad style being edited.

Radius

Specify the radius for the pad style being edited.

Guard Gap

Specify the distance by which pad radii will be enlarged when output is produced in RESIST mode. If the value is less than 0 (e.g. -1) then you will end up with a negative soldermask for this pad style. For PTH pad styles and vias you can specify the guard gap as not present to remove the pad from the solder resist artwork entirely. You can create new pad styles using the New Pad Style command on the Edit menu. There is no way to delete pad styles once they have been created.

Paste

Specify whether you want paste mask to be present or not. When defined the default is that the paste mask has the same size as the pad, although you can make is smaller by applying a shrink percentage. When not defined, there will be no paste mask at all. You can create your own paste definition for the pad by using solid 2D graphics objects on the appropriate paste layer. This allows you for example to define a stipled paste mask on a large thermal pad. This is shown in a tutorial movie on our website or Youtube Channel.

Changes

Specify whether you want the changes to be local to the design or persistent through all future designs.


Create New Via Style

Overview

Create a new style of via for use on the layout. This will allow you to customise the resist plot for the via as well as the drill hole and pad diameter. Via styles can be assigned to net classes from the Design Rule Manager on the Technology Menu. Assignment of via type (PTH, blind, buried) is either defined in the net class or manually edited on a per via basis.

The Layer Pairs command on the Technology Menu defines the behaviour of the software when you place a via during routing ; please see the help for more information.

Options

Name

Specify a name for the new via style.

Type

Select the type of via style that you wish to create.


Export Bitmap

Overview

This dialogue form allows you to export the current layout in bitmap format.

Options

Mode

Select one of two possible output modes. Choose from:

  • Artwork: This mode produces a normal PCB artwork with pads, tracking and graphics drawn to specific dimensions. The thickness of silk screen graphics lines is configured through the Text Style command on the Technology Menu. If selected, resist layers will be negative image of the solder resist by drawing pads, without drill mark holes and enlarged in size by the guard band value associated with each pad and via style. Similarly, if paste mask is selected, a negative image of the SMT paste mask will be drawn
  • Drill: This mode produces a special plot with each size of drill hole indicated by a different symbol. 15 such sizes are provided by default with names $DR00 up to $DR14. If you manage to create a board with more than 15 hole sizes, ARES will draw the extra holes as circles of actual size.

Layers

Specify which layers of the board you wish to output. Many people dispense with the solder side silk screen – it is only really useful if a board has components on both sides or must be tested or maintained solely from underneath.

Be aware that selecting a combination of several layers which occupy the same vertical space on the PCB can result in an obfuscated printout when layers are flattened onto a piece of paper. Use the Separate Pages option or multiple prints if this proves to be an issue.

Resolution

The resolutions available range from 100 to 600 DPI. Memory usage increases in proportion to the square of the resolution, so a 600 DPI bitmap needs 36 times as much memory as a 100 DPI bitmap. A 100 DPI bitmap in 256 colours needs 10k bytes per square inch (5kB if in 16 colours).

Colours

Select the colour format most appropriate for your design.

Rotation

Specify the desired x-rotation for output.

Our Virtual Graphics subsystem can produce output with the x-dimension either vertical or horizontal on your peripheral. This lets you orient your work most naturally within the Layout Editor and still be able to make the best use of the size of your peripheral when producing artwork.

The terms x-horizontal and x-vertical will depend also on the whether you have selected portrait or landscape mode for the print device itself. On a portrait page we define horizontal to mean parallel to the short edge.

Reflection

Specify whether you wish normal (i.e. as seen on screen) or mirrored output.

Compensation

The compensation parameters scale the absolute co-ordinates of the graphic leaving the relative size(s) unaffected. For example, if you have a line of length 10 units drawn at co-ordinates (5, 5) and you set the x-compensation = 0.6 and the y-compensation = 0.5, then the line would actually be outputed at co-ordinates (3, 2). The length ( 10 units ) remains unaffected. The purpose of these parameters is therefore to allow dimensionally critical designs to be of sufficient accuracy. They are particularly relevant to older non-linear printers such as the Dot Matrix and need not be altered for most modern printers. It is recommended that only advanced users attempt this functionality.

Output To File?

Browse your hard disk to select a directory and file into which to save the output.


Export DXF/EPS

Overview

This dialogue form allows you to export the current layout in DXF/EPS format.

Options

Mode

Select one of two possible output modes. Choose from:

  • Artwork: This mode produces a normal PCB artwork with pads, tracking and graphics drawn to specific dimensions. The thickness of silk screen graphics lines is configured through the Text Style command on the Technology Menu. If selected, resist layers will be negative image of the solder resist by drawing pads, without drill mark holes and enlarged in size by the guard band value associated with each pad and via style. Similarly, if paste mask is selected, a negative image of the SMT paste mask will be drawn
  • Drill: This mode produces a special plot with each size of drill hole indicated by a different symbol. 15 such sizes are provided by default with names $DR00 up to $DR14. If you manage to create a board with more than 15 hole sizes, ARES will draw the extra holes as circles of actual size.
  • Assembly Plot: Exports an assembly plot of the board according to the selection of Top Assembly / Bot Assembly from the Layers below.
  • Testpoint Plot: Exports a view of the board with the locations of all designated testpoints illustrated. This includes both on component testpoints as well as designated vias and dedicated testpoint objects.
See Also:

Testpoints

Assembly Drawings

Layers

Specify which layers of the board you wish to output. Many people dispense with the solder side silk screen – it is only really useful if a board has components on both sides or must be tested or maintained solely from underneath.

Be aware that selecting a combination of several layers which occupy the same vertical space on the PCB can result in an obfuscated printout when layers are flattened onto a piece of paper. Use the Separate Pages option or multiple prints if this proves to be an issue.

Filename

Browse your hard disk to select a directory and file into which to save the output.

Scale

Select the appropriate scale from the options given. Obviously there is a trade off between the final board quality and the maximum size of board you can handle for a given size peripheral.

Rotation

Specify the desired x-rotation for output.

Our Virtual Graphics subsystem can produce output with the x-dimension either vertical or horizontal on your peripheral. This lets you orient your work most naturally within the Layout Editor and still be able to make the best use of the size of your peripheral when producing artwork.

The terms x-horizontal and x-vertical will depend also on the whether you have selected portrait or landscape mode for the print device itself. On a portrait page we define horizontal to mean parallel to the short edge.

Fill Mode

  • Outlines Only. Exports zones as just the boundary.
  • Tiled. Uses tristrip polygons to produce a set of DXF hatches without holes to represent the zone. Whilst we cannot currently import the hatches for each polygon we can import the boundaries which are also produced Note that this is strictly a feature from a newer version of DXF so the produced file is not fully compliant.
  • Solid. Uses DXF hatches to produce a single solid polygon with holes for the zone. Caveat as above. Note also that hatches with holes/additional paths may be less well supported by some DXF libraries.
  • Raster. Does not use DXF hatches, instead attempts to simulate filled polygons with a set of lines. Large files but more compatible with third party tools.


EXPORT SVG

Overview

This dialogue form allows you to export the current layout in Scalable Vector Graphics (SVG) format.

Options

Mode

Select one of two possible output modes. Choose from:

  • Artwork: This mode produces a normal PCB artwork with pads, tracking and graphics drawn to specific dimensions. The thickness of silk screen graphics lines is configured through the Text Style command on the Technology Menu. If selected, resist layers will be negative image of the solder resist by drawing pads, without drill mark holes and enlarged in size by the guard band value associated with each pad and via style. Similarly, if paste mask is selected, a negative image of the SMT paste mask will be drawn
  • Drill: This mode produces a special plot with each size of drill hole indicated by a different symbol. 15 such sizes are provided by default with names $DR00 up to $DR14. If you manage to create a board with more than 15 hole sizes, ARES will draw the extra holes as circles of actual size.

Layers

Specify which layers of the board you wish to output. Many people dispense with the solder side silk screen – it is only really useful if a board has components on both sides or must be tested or maintained solely from underneath.

Be aware that selecting a combination of several layers which occupy the same vertical space on the PCB can result in an obfuscated printout when layers are flattened onto a piece of paper. Use the Separate Pages option or multiple prints if this proves to be an issue.

Options

Specify any particular options for the dialogue form.

  • Colour Output? - Specify whether or not the output will be in colour or monochrome.
  • Invert Colours? - Choose whether or not to invert the colours when outputting.
  • Background Colour - Select a background colour for the exported layer set. Some caution is required to ensure sufficient contrast and visibility of the output.
  • Separate Pages? - Export each layer of the PCB on a different page.
  • Launch Viewer? - View the exported SVG file in your system viewer on completion.

Rotation

Specify the desired x-rotation for output.

Our Virtual Graphics subsystem can produce output with the x-dimension either vertical or horizontal on your peripheral. This lets you orient your work most naturally within the Layout Editor and still be able to make the best use of the size of your peripheral when producing artwork.

The terms x-horizontal and x-vertical will depend also on the whether you have selected portrait or landscape mode for the print device itself. On a portrait page we define horizontal to mean parallel to the short edge.

Reflection

Specify whether you wish normal (i.e. as seen on screen) or mirrored output.

Output To File?

Browse your hard disk to select a directory and file into which to save the output.


Export Metafile

Overview

This dialogue form allows you to export the current layout in metafile format.

Options

Mode

Select one of two possible output modes. Choose from:

  • Artwork: This mode produces a normal PCB artwork with pads, tracking and graphics drawn to specific dimensions. The thickness of silk screen graphics lines is configured through the Text Style command on the Technology Menu. If selected, resist layers will be negative image of the solder resist by drawing pads, without drill mark holes and enlarged in size by the guard band value associated with each pad and via style. Similarly, if paste mask is selected, a negative image of the SMT paste mask will be drawn
  • Drill: This mode produces a special plot with each size of drill hole indicated by a different symbol. 15 such sizes are provided by default with names $DR00 up to $DR14. If you manage to create a board with more than 15 hole sizes, ARES will draw the extra holes as circles of actual size.

Layers

Specify which layers of the board you wish to output. Many people dispense with the solder side silk screen – it is only really useful if a board has components on both sides or must be tested or maintained solely from underneath.

Be aware that selecting a combination of several layers which occupy the same vertical space on the PCB can result in an obfuscated printout when layers are flattened onto a piece of paper. Use the Separate Pages option or multiple prints if this proves to be an issue.

Options

Specify any particular options for the dialogue form.

  • Colour Output? - Specify whether or not the output will be in colour or monochrome.
  • Invert Colours? - Choose whether or not to invert the colours when outputting.
  • Erase Background? - When checked, this option causes ARES to draw a black rectangle before drawing anything else. When this option is unchecked the output is transparent and may not therefore be visible.

Rotation

Specify the desired x-rotation for output.

Our Virtual Graphics subsystem can produce output with the x-dimension either vertical or horizontal on your peripheral. This lets you orient your work most naturally within the Layout Editor and still be able to make the best use of the size of your peripheral when producing artwork.

The terms x-horizontal and x-vertical will depend also on the whether you have selected portrait or landscape mode for the print device itself. On a portrait page we define horizontal to mean parallel to the short edge.

Reflection

Specify whether you wish normal (i.e. as seen on screen) or mirrored output.

Compensation

The compensation parameters scale the absolute co-ordinates of the graphic leaving the relative size(s) unaffected. For example, if you have a line of length 10 units drawn at co-ordinates (5, 5) and you set the x-compensation = 0.6 and the y-compensation = 0.5, then the line would actually be outputed at co-ordinates (3, 2). The length ( 10 units ) remains unaffected. The purpose of these parameters is therefore to allow dimensionally critical designs to be of sufficient accuracy. They are particularly relevant to older non-linear printers such as the Dot Matrix and need not be altered for most modern printers. It is recommended that only advanced users attempt this functionality.

Output To File?

Browse your hard disk to select a directory and file into which to save the output.


CADCAM Notes

Overview

This dialogue form provides space for you to give information to the manufacturer.

Options

Project Manufacturing Notes

When selected this option will create a PDF from the Manufacturing Notes document in the Project Notes module and will include it in the CADCAM fileset. If you do not have a Project Notes document of type Manufacturing Notes then this will fail with an error.

For more information on Project Notes and Manufacturing Notes types please refer to the Project Notes help file or the tutorial video on the website.

Legacy Notes

When selected this option will allow to type short notes in the edit field below to accompany the CADCAM fileset. This will be superceded by the Project Notes option and we therefore recommend that you use Project Notes for this purpose.

Contact Details

Use this field to enter your contact details. These notes are included within the readme.txt file created during the CADCAM Output process.


Manufacturing Outputs

Manufacturing Outputs (Gerber/ODB++/IDF)

Overview

These dialogue forms provide configuration options for exporting the layout for manufacture.

Options

Output Generation

These options allow you to configure the destination and format of the CADCAM output files and also to automatically perform actions immediately after generation of the files.

  • Filestem - Specify the filestem for your output files. This is useful if you want to prefix all your CADCAM files with a filestem different from the name of the ARES file (to indicate revisions for example).
  • Folder - Specify the output folder for your CADCAM files. By default all files will be written to the project directory (the same directory as the layout file). You can specify a new default location via the Set Paths command in the System Menu.
  • Output to Individual TXT files? - Check this box if you want all files to be exported individually. The files will be placed in the folder specified above (you can set the default folder via System –Set Paths). You may want to use the Automatically open output folder option in tandem with this selection.
  • Output to ODB++ database folder? - Check this box if you want all files to be exported individually. The files will be placed in the folder specified above (you can set the default folder via System –Set Paths). You may want to use the Automatically open output folder option in tandem with this selection.
  • Output to single ZIP file? - Check this box if you want all the CADCAM files to be exported into a single zip archive. The zip archive will be placed in the folder specified above (you can set the default folder via System –Set Paths). You may want to use the Automatically open zip file option in tandem with this selection.
  • Automatically open output folder? - Check this box if you want to automatically open the folder containing the CADCAM files in Windows Explorer following the CADCAM operation. Typically this option is useful if you have specified the Output to individual text files option on the left.
  • Automatically open ZIP file? - Check this box if you want to automatically open the zip file containing the CADCAM files following the CADCAM operation. Obviously this option is only useful if you have specified the Output to a single zip file option on the left.

Layers/Artworks

Specify which layers of the board you wish to output. Many people for example dispense with the solder side silk screen – it is only really useful if a board has components on both sides or must be tested or maintained solely from underneath.

Note that you can include top assembly and/or bottom assembly with both ODB++ and Gerber X2 output formats.

Apply Global Gap Guard? - When checked this option will allow you to specify a global value for the guard gap on the resist layers. This should be used only where a global value for resist (pads and vias) is required as a local change is applied to all the styles in the layout.

Rotation (Gerber/Excellon Only)

Specify the desired x-rotation for output.

Our Virtual Graphics subsystem can produce output with the x-dimension either vertical or horizontal on your peripheral. This lets you orient your work most naturally within the Layout Editor and still be able to make the best use of the size of your peripheral when producing artwork.

The terms x-horizontal and x-vertical will depend also on the whether you have selected portrait or landscape mode for the print device itself. On a portrait page we define horizontal to mean parallel to the short edge.

Reflection (Gerber/Excellon Only)

Specify whether you wish normal (i.e. as seen on screen) or mirrored output.

File Units (Gerber/Excellon Only)

Specify which type of file units you wish to use for the aperture information. Metric is the default as it will have the highest precision.

Gerber Format (Gerber/Excellon Only)

Specify whether the newer Gerber X2 or the older RS274X format. Gerber X2 has the major advantages of including the IPC-D-356 netlist, having separated drill files and included automatic attribute data.

Slotting/Routing Layer

Unfortunately, there is no widely accepted mechanism within the industry for specifying the location of slots and cut-outs within the CADCAM data. Therefore, the best we can do is to output the coordinates of each routing stroke in Gerber format, and then leave it to individual board manufacturers to convert the data for their own particular routing machines.

To do this, we make use of one of the MECH layers within ARES. Use this option to specify which MECH layer is to be used. 2D graphics placed on that layer will then also be interpreted as defining routing strokes.

Please refer to the topic on slotting and mechanical data for more information as the location of the routing data may vary between output formats.

It is important to ensure that your board manufacturer understands that the specified MECH layer contains routing co-ordinates in Gerber format. You will need to tell them this explicitly.

Bitmap/Font Rasterizer

Use this combo box to specify the output resolution of any bitmaps and fonts on the layout. The rasterization process converts these ‘objects’ into bitmaps. Bitmap images form lines (rows) of adjacent pixels (such rows being referred to as 'rasters'). It follows then that the higher the resolution setting the better the tonality of the resulting bitmap(s) but the larger the files. In general this option can be left at the default setting.

Run Gerber view when done? (Gerber/Excellon Only)

When checked this option will automatically launch the Gerber Viewer and load in the CADCAM files after completing the CADCAM generation.

Run Valor ODB++ Viewer When Done?

When checked this option will automatically launch the Valor ODB++ Viewer and load in the CADCAM files after completing the CADCAM generation.

Note that since the takeover by Mentor the Valor viewer is not easily sourced on the net. The replacement Mentor Viewer is also free of charge but does not integrate directly with Proteus.


Print Layout

Overview

This dialogue form allows you to edit your print layout.

Options

Printer

Specify the printer that you wish to output to. The currently selected printer is displayed in text.

Colour Options

These options allow you to specify which colour profile you want to use for printing. The combo box has three pre-supplied colour sets (Monochrome, Black Paper, White Paper) and will also include any colour sets you have created yourself.

Colour sets are created on the Displayed Layers dialogue form on the View Menu.

Labcenter Plotter Driver?

This option is enabled only when you have a pen plotter device selected. The Labcenter plotter driver relies on the Windows drivers only to draw straight lines – ARES itself will do the rest.

Mode

Select one of two possible output modes. Choose from:

  • Artwork: This mode produces a normal PCB artwork with pads, tracking and graphics drawn to specific dimensions. The thickness of silk screen graphics lines is configured through the Text Style command on the Technology Menu. If selected, resist layers will be negative image of the solder resist by drawing pads, without drill mark holes and enlarged in size by the guard band value associated with each pad and via style. Similarly, if paste mask is selected, a negative image of the SMT paste mask will be drawn
  • Drill: This mode produces a special plot with each size of drill hole indicated by a different symbol. 15 such sizes are provided by default with names $DR00 up to $DR14. If you manage to create a board with more than 15 hole sizes, Proteus will draw the extra holes as circles of actual size.
  • Assembly: This produces an assembly plot of the board according to the selected layers. It follows therefore that you may choose to print two for top assembly and bottom assembly for example. Refer to the topic on assembly drawings for more information.
  • Testpoint Plot: This produces a plot showing the location of all designated testpoints on the board plus additional information based on the selected layers. Refer to the topic on testpoints for more information.

Layers

Specify which layers of the board you wish to output. Many people dispense with the solder side silk screen – it is only really useful if a board has components on both sides or must be tested or maintained solely from underneath.

Be aware that selecting a combination of several layers which occupy the same vertical space on the PCB can result in an obfuscated printout when layers are flattened onto a piece of paper. Use the Separate Pages option or multiple prints if this proves to be an issue.

Separate Pages?

Export each layer of the PCB on a different page.

Scale

Select the appropriate scale from the options given. Obviously there is a trade off between the final board quality and the maximum size of board you can handle for a given size peripheral.

Rotation

Specify the desired x-rotation for output.

Our Virtual Graphics subsystem can produce output with the x-dimension either vertical or horizontal on your peripheral. This lets you orient your work most naturally within the Layout Editor and still be able to make the best use of the size of your peripheral when producing artwork.

The terms x-horizontal and x-vertical will depend also on the whether you have selected portrait or landscape mode for the print device itself. On a portrait page we define horizontal to mean parallel to the short edge.

Reflection

Specify whether you wish normal (i.e. as seen on screen) or mirrored output.

Compensation

The compensation parameters scale the absolute co-ordinates of the graphic leaving the relative size(s) unaffected. For example, if you have a line of length 10 units drawn at co-ordinates (5, 5) and you set the x-compensation = 0.6 and the y-compensation = 0.5, then the line would actually be outputed at co-ordinates (3, 2). The length ( 10 units ) remains unaffected. The purpose of these parameters is therefore to allow dimensionally critical designs to be of sufficient accuracy. They are particularly relevant to older non-linear printers such as the Dot Matrix and need not be altered for most modern printers. It is recommended that only advanced users attempt this functionality.

Print to file?

Confirm your selection of saving the artwork to the specified file.

Filename - Browse your hard disk to select a directory and file into which to save the output.


Export Overlay

Overview

This dialogue form allows you to export the current overlay.

Options

Copper Layers

Select which copper layers to include the overlay bitmap.

Silk Screens

Select which silkscreen layers you are going to superimpose on the copper layers for output.

Resolution

The resolutions available range from 100 to 600 DPI. Memory usage increases in proportion to the square of the resolution, so a 600 DPI bitmap needs 36 times as much memory as a 100 DPI bitmap. A 100 DPI bitmap in 256 colours needs 10k bytes per square inch (5kB if in 16 colours).

Colours

Select the colour format most appropriate for your design.

Rotation

Specify the desired x-rotation for output.

Our Virtual Graphics subsystem can produce output with the x-dimension either vertical or horizontal on your peripheral. This lets you orient your work most naturally within the Layout Editor and still be able to make the best use of the size of your peripheral when producing artwork.

The terms x-horizontal and x-vertical will depend also on the whether you have selected portrait or landscape mode for the print device itself. On a portrait page we define horizontal to mean parallel to the short edge.

Reflection

Specify whether you wish normal (i.e. as seen on screen) or mirrored output.

Compensation

The compensation parameters scale the absolute co-ordinates of the graphic leaving the relative size(s) unaffected. For example, if you have a line of length 10 units drawn at co-ordinates (5, 5) and you set the x-compensation = 0.6 and the y-compensation = 0.5, then the line would actually be outputed at co-ordinates (3, 2). The length ( 10 units ) remains unaffected. The purpose of these parameters is therefore to allow dimensionally critical designs to be of sufficient accuracy. They are particularly relevant to older non-linear printers such as the Dot Matrix and need not be altered for most modern printers. It is recommended that only advanced users attempt this functionality.

Output To File?

Browse your hard disk to select a directory and file into which to save the output.


Export PDF

Overview

This dialogue form allows you to export the current layout in PDF format.

Options

Mode

Select one of two possible output modes. Choose from:

  • Artwork: This mode produces a normal PCB artwork with pads, tracking and graphics drawn to specific dimensions. The thickness of silk screen graphics lines is configured through the Text Style command on the Technology Menu. If selected, resist layers will be negative image of the solder resist by drawing pads, without drill mark holes and enlarged in size by the guard band value associated with each pad and via style. Similarly, if paste mask is selected, a negative image of the SMT paste mask will be drawn
  • Drill: This mode produces a special plot with each size of drill hole indicated by a different symbol. 15 such sizes are provided by default with names $DR00 up to $DR14. If you manage to create a board with more than 15 hole sizes, ARES will draw the extra holes as circles of actual size.

Layers

Specify which layers of the board you wish to output. Many people dispense with the solder side silk screen – it is only really useful if a board has components on both sides or must be tested or maintained solely from underneath.

Be aware that selecting a combination of several layers which occupy the same vertical space on the PCB can result in an obfuscated printout when layers are flattened onto a piece of paper. Use the Separate Pages option or multiple prints if this proves to be an issue.

Options

Specify any particular options for the dialogue form.

  • Colour Output? - Specify whether or not the output will be in colour or monochrome.
  • Invert Colours? - Choose whether or not to invert the colours when outputting.
  • Background Colour - Select a background colour for the exported layer set. Some caution is required to ensure sufficient contrast and visibility of the output.
  • Separate Pages? - Export each layer of the PCB on a different page.
  • Launch Viewer? - View the exported PDF file in your installed PDF Viewer on completion.

Rotation

Specify the desired x-rotation for output.

Our Virtual Graphics subsystem can produce output with the x-dimension either vertical or horizontal on your peripheral. This lets you orient your work most naturally within the Layout Editor and still be able to make the best use of the size of your peripheral when producing artwork.

The terms x-horizontal and x-vertical will depend also on the whether you have selected portrait or landscape mode for the print device itself. On a portrait page we define horizontal to mean parallel to the short edge.

Reflection

Specify whether you wish normal (i.e. as seen on screen) or mirrored output.

Output To File?

Browse your hard disk to select a directory and file into which to save the output.


Export Vector

Overview

This dialogue form allows you to export the current layout in vector format.

Options

Filename

Browse your hard disk to select a directory and file into which to save the output.

Mode

Select one of two possible output modes. Choose from:

  • Artwork: This mode produces a normal PCB artwork with pads, tracking and graphics drawn to specific dimensions. The thickness of silk screen graphics lines is configured through the Text Style command on the Technology Menu. If selected, resist layers will be negative image of the solder resist by drawing pads, without drill mark holes and enlarged in size by the guard band value associated with each pad and via style. Similarly, if paste mask is selected, a negative image of the SMT paste mask will be drawn
  • Drill: This mode produces a special plot with each size of drill hole indicated by a different symbol. 15 such sizes are provided by default with names $DR00 up to $DR14. If you manage to create a board with more than 15 hole sizes, ARES will draw the extra holes as circles of actual size.

Layers

Specify which layers of the board you wish to output. Many people dispense with the solder side silk screen – it is only really useful if a board has components on both sides or must be tested or maintained solely from underneath.

Be aware that selecting a combination of several layers which occupy the same vertical space on the PCB can result in an obfuscated printout when layers are flattened onto a piece of paper. Use the Separate Pages option or multiple prints if this proves to be an issue.

Device

Export the vector file in one of the given formats. Note that HPGL standard assumes a top left origin whereas HPGL (CTO) has a center origin. The Hi-80 format is compatible with most Epson plotters and the DPML format is compatible with the Houston plotter series.

Scale

Select the appropriate scale from the options given. Obviously there is a trade off between the final board quality and the maximum size of board you can handle for a given size peripheral.

Rotation

Specify the desired x-rotation for output.

Our Virtual Graphics subsystem can produce output with the x-dimension either vertical or horizontal on your peripheral. This lets you orient your work most naturally within the Layout Editor and still be able to make the best use of the size of your peripheral when producing artwork.

The terms x-horizontal and x-vertical will depend also on the whether you have selected portrait or landscape mode for the print device itself. On a portrait page we define horizontal to mean parallel to the short edge.

Reflection

Specify whether you wish normal (i.e. as seen on screen) or mirrored output.


Diff Pair Length Tuning

Diff Pair Length Matching

Introduction

The settings on this dialogue form allow you to configure the shape and constrain the size of any serpentine segments used in diff pair length matching. This is used where the length of the differential pair is matched either against another differential pair or to a target length.

It is not the same as the serpentines used to match the length of the two tracks that make up the differential pair. These serpentines are a result of phase matching (sometimes called skew correction) and can be controlled on the third tab of the Length Tuning dialogue form.

While you can specify the topology of any length matching serpentine segments here the tolerances are set in the differential pair tab of the design rule manager. This is because the tolerance is most often part of the protocol specification and so more properly belongs with the net class.

Serpentine Configuration

These options allow you to specify a minimum, maximum and preferred height for the serpentine tracks, as well as a width between tracks in the serpentine.

Differential Pair Serpentines of different heights as a result of lengthening the diff pair

Like the height parameters this is the width between length matched serpentine segments. It is not the width between the two tracks in the differential pair (which is set in the design rule manager) !

The width specifies the distance between serpentine segments.

Cap Style

The cap style defines the topology of the end-cap's on the serpentine route. Both rounded and mitred caps are very common but the sharp cornered rectangular cap is not widely seen as it can cause signal reflections; it is included partly for completeness and also to allow the designer the full range of options.

Uniform Height

There are three options for controlling the shape of the serpentine route along the track. The default is off, which corresponds to an irregular serpentine which may be higher in some places than others and may be offset from the centre in some places as well. Needless to say, this option provides the greatest flexibility and therefore the greatest chance of success. It can also help minimise coupling between traces as there may be no defined pattern.

Switching uniform height on will clamp the serpentine into a single height (the preferred height) across it's entirety. The complete serpentine is allowed to be offset from the centre of the track but is not allowed to vary as this would involve one section with a different height. To achieve completion with this type of setup you will almost always have to relax the tolerance since only equally sized serpentines are permitted.

Switching to centred mode will force the serpentine to a single size (the preferred height), centred on the original track line. This is the most predictable of the options, but the least flexible and therefore the least likely to succeed if obstacles are encountered.

Minimum and maximum height are ignored and disabled with a uniform height setting. The uniform height will be the preferred height.

Restrictions on height and offsetting will severely limit the ability of the length matching algorithm to successfully complete. As you can see from the pictures above, any obstacle will result in failure because the serpentine is not allowed to change shape to work around it.


Diff Pair Phase Matching

Introduction

This dialogue allows the configuration of serpentine segments that correct the length of one track in the diff pair to the other track in the diff pair. This is known as phase matching or skew correction and is discussed in some detail in the reference manual.

While you can configure the shape and size of the phase matching segments here the tolerance is set in the diff pairs tab of the design rule manager dialogue.

The process of phase matching in Proteus is automatic when the route is completed in differential pair routing mode or can be invoked manually at any time via the context menu command on either of the diff pair tracks.

Serpentine Configuration

These options allow you to specify a minimum, maximum and preferred height for the serpentine segments.

Phase Match serpentine segments with a chamfered cap style.

Cap Style

The cap style defines the topology of the end-cap's on the serpentine route. Both rounded and mitred caps are very common but the sharp cornered rectangular cap is not widely seen as it can cause signal reflections; it is included partly for completeness and also to allow the designer the full range of options.

Uniform Height

There are three options for controlling the shape of the serpentine route along the track. The default is off, which corresponds to an irregular serpentine which may be higher in some places than others and may be offset from the centre in some places as well. Needless to say, this option provides the greatest flexibility and therefore the greatest chance of success. It can also help minimise coupling between traces as there may be no defined pattern.

Switching uniform height on will clamp the serpentine into a single height (the preferred height) across it's entirety. The complete serpentine is allowed to be offset from the centre of the track but is not allowed to vary as this would involve one section with a different height.

You will need a much higher tolerance to achieve completion if you restrict the length matching to uniform height as only a complete serpentine will be allowed.

Switching to centred mode will force the serpentine to a single size (the preferred height), centred on the original track line. This is the most predictable of the options, but the least flexible and therefore the least likely to succeed if obstacles are encountered. Minimum and maximum height are ignored and disabled with a uniform height setting. The uniform height will be the preferred height.


Set Length Tuning

Length Tuning Configuration

Overview

Length tuning or length matching is often used with higher speed or longer distance signal runs on the PCB to improve signal timing or signal integrity. The basic idea is that the shorter trace follows a detour or meander in order to lengthen it to match the length of the longer trace. This dialogue enables various configurations of serpentine pattern which will then be used when you length match traces on the board.

To length match traces, simply hold the CTRL button down, make successive left clicks on the traces you want to match and then use the right click context menu to invoke the length match command.

Serpentine Size

These options allow you to specify a minimum, maximum and preferred height for the serpentine tracks, as well as a width between tracks in the serpentine.

Internally, the tuning algorithm will first attempt to route with the preferred height unless an obstruction forces a lesser height. In this case, the height may vary between the preferred height and the minimum height to navigate the obstacle.

If the length match fails because routing with the preferred height is not sufficient then a secondary pass will be made to grow the preferred height towards the maximum height. Be aware that the larger the maximum height, the greater the change of a long parallel run..

Note that specifying uniform height in this dialogue will impact on these settings because a variation for obstacle avoidance will not be permitted.

The width is the distance between two sections of the serpentine track in a single switchback. This can also be thought of as the horizontal distance between peak and trough in the direction of travel of the trace.

This value needs to be set quite carefully; if the outbound and returning traces pass too close to each other, crosstalk coupling between the two traces may distort the output.

If possible, you should try to set serpentine sizes relative to track width. Not only is this consistent with a lot of SI guidance but it will allow you to set up a single configuration for multiple different tuning operations where the tracks have different widths.

See Also:

External Website: A Summary of Serpentine Routing & Signal Integrity

Cap Style

The cap style defines the topology of the end-cap's on the serpentine route. Both rounded and mitred caps are very common but the sharp cornered rectangular cap is not widely seen as it can cause signal reflections; it is included partly for completeness and also to allow the designer the full range of options.

Length Tolerance

Length tolerance is the amount by which a serpentine route is allowed to deviate from the target route it is being length matched against.

If there is a lot of net tuning to be done and it is possible to do so, we recommend specifying this as a percentage of the target length in order that the same configuration will hold for all of the tuning operations. If absolute maximum tolerances are needed then you will have to enter the dialogue multiple times as nets are tuned across the board.

When a successful length match is made, you will find the delta between the traces displayed on the status bar.

The length matched in Proteus is from center pad to center pad. It is not the etched copper length from pad edge to pad edge. Almost all of the time this will either cancel out (similar pad shapes on both sides) or be insignificant. We have chosen this metric because the center of the pad is the earliest available point at which to start length matching (the route and distance of the signal from the connection point on the PCB to the physical component is unknown).

Uniform Height

There are three options for controlling the shape of the serpentine route along the track. The default is off, which corresponds to an irregular serpentine which may be higher in some places than others and may be offset from the centre in some places as well. Needless to say, this option provides the greatest flexibility and therefore the greatest chance of success. It can also help minimise coupling between traces as there may be no defined pattern.

Switching uniform height on will clamp the serpentine into a single height (the preferred height) across it's entirety. The complete serpentine is allowed to be offset from the centre of the track but is not allowed to vary as this would involve one section with a different height.

You will need a much higher tolerance to achieve completion if you restrict the length matching to uniform height as only a complete serpentine will be allowed.

Switching to centred mode will force the serpentine to a single size (the preferred height), centred on the original track line. This is the most predictable of the options, but the least flexible and therefore the least likely to succeed if obstacles are encountered.

Minimum and maximum height are ignored and disabled with a uniform height setting. The uniform height will be the preferred height.

Restrictions on height and offsetting will severely limit the ability of the length matching algorithm to successfully complete. As you can see from the pictures above, any obstacle will result in failure because the serpentine is not allowed to change shape to work around it.


Set Teardrop

Teardrop & Tapers

Overview

Teardrops are small tapers that are added at the junction of pad to the connecting track. They are typically added to defend against drill breakout during the drilling process. Some engineers will also use them by default to ensure a solid connection to the pad or in an attempt to add mechanical strength to sensitive parts of the board (e.g. balls on a BGA or connector contact pads).

Track tapers are exactly the same except they bridge the thicker and thinner track. The goal is to avoid the sudden change in width seen with a track necking. The tapered trace adds an angled piece of copper to taper the track thickness improving the mechanical structure of the change in thickness. Trace thickness changes can be there for mechanical reasons (like routing from a flexi area to a rigid area) or for signal integrity reasons where a high speed line needs thinner tracking to connect to a terminating pin/ball.

The management of both teardrops and track tapers is fairly automatic in Proteus. After enabling and specifying sizes Proteus can automatically add teardrops to your pad/trace connections and will then maintain them for you. For example, moving the route after placement will re-generate the teardrop in the correct position.

This dialogue explains the various teardrop configuration options available.

Teardrops

Enable

This checkbox is a global switch to enable/disable teardrops on the board.

The edit single pin dialogue allows you to control the teardrop connection to a single pad. The default is the global configuration settings as described above but you can either force enable or force disable if necessary.

Include Undrilled Pads

When selected, teardrops can be added to SMT pads as well as drilled PTH pads and vias.

Maximum Annular Ring

The annular ring setting gates the creation of the teardrop on the copper thickness between the edge of the hole and the edge of the pad. This makes sense as the primary use of the teardrop is to guard against drill breakout. You can specify a maximum annular ring size below which a teardrop connection will be made. If you have selected to teardrop undrilled pads as well the distance considered here is centre pad to nearest pad edge.

Teardrop Length

The teardrop length setting controls the depth from the pad onto the track with which to form the teardrop. The option is a percentage of the width of the pad to ensure that a consistent ratio (fixed slope) applies regardless of the pad size.

For circular holes the width is the diameter of the pad. For rectangular holes it's the largest of the two dimensions.

Track Tapers

Enable

This checkbox is a global switch to enable/disable track tapers on the board.

Tapering Length

Sets the preferred length for the track taper based on a percentage of the width of the thickest track (to ensure consistency across the board).

Teardrop/Taper Sizes

Teardrop and Taper sizes can be thought of as maximum sizes. Proteus will automatically reduce them if there is segment length incompatibility (the track segment the teardrop should go on is too small). Specifically, DRC compliance is a yes or no - Proteus will not reduce teardrops or tapers to make DRC compliant, it will simply not render them at all.


Stackup Wizard

Layer Stackup Wizard

Overview

This dialogue enables the configuration of the stackup for the PCB. The information provided here is then used in the Proteus software in various places.

  • The number of layers and the board style together provide a legal set of drill passes for the PCB. This is used when vias are placed during manual and auto-routing.
  • The number of layers determines the set of layers available in tracking mode.
  • The thickness parameters specified here are used when length matching to add via length to the routes.
  • The entire stackup information is dumped in the CADCAM readme file so that your board manufacturer is aware of your intended design.

A quick way to construct a stackup for a standard 1.6mm board is to choose from one of our generic templates in the New Project wizard. If you do so, make sure you understand about plane layers as you may need to change the layer types to accomodate your particular pcb.

Generic 1.6mm (+/- 10%) PCB Templates for different numbers of copper layers.

Options

Number of Copper Layers

Specify the number of copper layers on the PCB. This includes plane layers.

Board Style

For multi-layer boards this choice determines whether the stackup is build from external pairs of cores inwards or from internal cores outwards. In turn, this determines what kind of vias you can have and what drill ranges are manufacturable using standard techniques. It's important to understand the effect of this setting and it is discussed in some detail in the topic linked below.

About Layer Stacks

Material

The material used is basically the constitution of the core. Under normal conditions this is almost always FR4 laminate, but this can change at high speed. There are two basic types of circuits that fall under the heading of high frequency, RF / Analog (aka- RF/Microwave) and High Speed digital. Each of these has their own unique requirements, which have spawned two distinct classes of materials. The excellent article linked below discusses this in some detail.

External Link : Speeding Edge.com - PCB Material Considerations.pdf

Specifying a change of material is likely to also affect your dielectric values.

This information is not used by Proteus at the time of writing, but is exported in the CADCAM readme file for the board manufacturer. You can therefore safely leave the default values in if it is not relevant to your project.

Thickness Fields

There are three thickness fields, for surface, copper and core respectively. This information is used by Proteus only to calculate via depth for length matching. It is also exported in the CADCAM readme file for the board manufacturer. You can therefore safely leave the default values in if this is not relevant to your project.

Dielectric Fields

There are two fields for dielectric constants, one for surface and the other for prepreg. This information is not used by Proteus at the time of writing, but is exported in the CADCAM readme file for the board manufacturer. You can therefore safely leave the default values in if it is not relevant to your project.


Set Default Rules

Overview

This tab allows you to specify some default styles to be applied to connections not otherwise configured. Once a layout is started use the Design Rule Manager option to change/edit the layout's design rules, or use the Apply to Default button to update the DEFAULT rule in the layout.

Options

Default Styles

Specify the default styles for the board. These can be altered on a per net class basis via the Design Rule Manager command on the Technology menu.

  • Neck Style - Specify the neck style for the board. Setting this to none will disable the Auto Neck Tracking feature.
  • Relief Style - Specify the relief style for the board. Setting this to none will disable thermal relief power planes.

Tolerances

  • Curve Tolerance - In several places within ARES it is necessary to linearly approximate curves and arcs. This option allows you to specify how accurate the linear approximation will be (the smaller the curve tolerance the more accurate the approximation).
  • Rule Check Tolerance - This is the amount of tolerance between a design rule violation and the maximum permitted clearance in a given situation.
  • Solder Resist Guard - This is the amount of clearance between the solder mask and copper. It is intended to prevent solder bridging during manufacture and we'd therefore recommend consulting your board manufacturer before adjusting this value.

If the solder mask expansion of the pad is bigger than the pad->trace clearance of the DRC the solder mask can impinge on the copper. A resist DRC error will occur if the solder mask is within 1th of the copper.

  • Minimum Solder Dam - When set this enforces a minimum feature width for the solder dam between pads. For example, if the guard gap is too big on component pads then there won't be enough copper between the pad fingers (the solder dam). This is turned off by default and when enabled essentially performs a resist->resist check with the specified clearance.

Testpoints

Required on all nets

This checkbox allows you to set a global minimum for testpoints on every net on the board. Alternatively, you can leave this off and set per net class.

The minimum number of testpoints field will enable when this option is selected.

Access Required on what side(s)

Specify whether testpoints should be placed on top, bottom or either side of the board.

Min Dimension

Specify the minimum dimension for a testpoint. Consult board manufacturer if needed for automated testing probes.

All dimensions of the pad (e.g. length and width) must meet the minimum dimension value.

Min Distance

Set the minimum distance between testpoints. This is intended largely for flying probe testing where enough space to get the probes in is required. Consult with fab house if needed.

Min Number

Set the minimum number of testpoints to apply to all nets of the board (unless overridden by a net class setting).

This field is only enabled when you say testpoints are required on all nets.

Default Packaging

Set the default packaging for testpoint terminals. This can be changed but all testpoint terminals will use the same package.

If you need multiple testpoint sizes or shapes then you can simply place pads/vias of the appropriate dimension and designate them as testpoints (right click ctx menu).

However, you can only ever have one testpoint package that applies to all testpoints that are created on the schematic with testpoint terminals.


Layer Stackup

Layer Stackup and Drill Spans

Overview

This dialogue form provides a list of all of the different layers, enter the name by which you want the specified layer to be referenced for each layer in use. It also allows you to choose which layers you would like to be visible in the track/graphic layer combobox at the bottom left of ARES. Therefore you are able to refine this list to only the required layers making it much more efficient to navigate around ARES.

Layers

The layers tab allows you to define how many copper layers your PCB will have, how many of them will be signal layers vs plane layers and the construction or stackup of the board with cores and pre-preg. The majority of the dialogue is an editable grid listing the current stackup. This is populated automatically after running the stackup wizard from the button underneath the grid. Entries can then be customized if necessary by double clicking in any of the editable fields and then making a change.

The create power plane button allows you specify a net and a layer for a power plane. The plane will then flood the designated layer and will be auto-drawn and maintained by Proteus. This button is disabled when there are no nets will therefore often be disabled (e.g. in the New Project Wizard).

There is a readout of the total board thickness underneath the layer grid. This is the sum of the thicknesses specified in the various layer entries. These values are used in the software to calculate the length of a via during length matching operations.

See Also:

About Layer Stacks

Defining Layer Stacks

Drill Spans

The drill spans tab build on the layer stack and enables the creation of a set of drill passes that are manufacturable using standard techniques. For all intents and purposes a drill span can be thought of as a pass of the CNC drilling machine. For a two layer board it is extremely simple and consists of a single pass through the board from top copper to bottom copper. However, as the number of layers (and number of cores) increases there are several different possible combinations of drilling passes.

The main grid is a view of the currently specified drill spans (the default will be thru-hole only). The 'Create from Cores' button underneath the grid will auto-create valid drill spans based on the layer stackup specified in the previous tab while the create from vias button caters for legacy designs and will create drill spans based on the vias already placed on the board. Finally, there are two buttons to add and delete drill spans manually.

The normal working pattern here is to create a set of drill spans by pressing the create from cores button because this will generate a full set of legal drill passes. Drill spans that are not needed are then deleted.

The software will warn you if you manually create a drill span that is not manufacturable given standard techniques. This is almost always where there is a partial drill span overlap (e.g. top->inner3 + bot->inner2). You can override this if you choose but please check carefully with your fab house for both feasibility and cost.

The Proteus software will make use of all specified drill spans automatically during via placement so make sure to remove any that you don't want.

See Also:

About Drill Spans

Defining Drill Spans

Board View

The board view tab provides a simple pictorial cross section of the board to illustrate the configuration specified in the layer and drilling tabs. Use this screen to inspect and verify visually that your configuration is correct.


Set Plotter Pens

Overview

This dialogue form allows you to set the pen colours and configure the Labcenter Plotter Driver for when using a plotter.

Options

Pen Colours

These options allow you to specify colours for each layer when using pen plotters. The plotter drivers are able to generate a multi-coloured plot only when ALL layers are selected on the Print dialogue form.

Where through hole pads are encountered, the pen number is determined by ORing the colours for the outer layers of the pad in the same way as is done for screen colours.

Note that this only applies to an ALL layers plot - single layer plots always use the black pen.

Unfortunately, the Windows plotter drivers do not (as far as we have been able to find out) support the direct selection of plotter pens by number. Therefore it is up to you to find out how your plotter driver maps colours onto pens and to select appropriate colours.

To select a colour for a particular layer left click the mouse over the coloured area corresponding to that layer and select a colour from the resulting options.

Labcenter Plotter Driver

These options allow you to configure the Labcenter Plotter Driver. Help is available on each one via the normal methods with the mouse over the option in question.

  • Pen Width - Specify the width of the pen nib being used on the plotter. The setting determines the proximity of hatching strokes used when filling solid objects.
  • Circle Step - This value determines the smoothness of circles drawn by the Labcenter plotter driver. The larger the number, the coarser the circles. A value of zero causes the driver to use the Windows GDI to draw circles.


Grids

Overview

This dialogue form allows you to set the grid options for the ARES viewer, units can be set in imperial or metric.

Options

Imperial

These options allow you to set snap settings for use when operating in imperial units.

  • Fine Snap - Enter a value in imperial units corresponding to the fine snap setting.
  • F2 Snap - Enter a value in imperial units corresponding to the F2 Key setting.
  • F3 Snap - Enter a value in imperial units corresponding to the F3 Key setting.
  • F4 Snap - Enter a value in imperial units corresponding to the F4 Key setting.

Metric

These options allow you to set up snap settings for use when operating in metric units. Metric mode is toggled on and off with the Metric command on the View menu.

  • Fine Snap - Enter a value in metric units corresponding to the fine snap setting.
  • F2 Snap - Enter a value in metric units corresponding to the F2 Key setting.
  • F3 Snap - Enter a value in metric units corresponding to the F3 Key setting.
  • F4 Snap - Enter a value in metric corresponding to the F4 Key setting.

Minimum dot spacing (pixels)

Specify the minimum distance apart in for dots on the grid.

Use Snap Setting for Route Editing

By default, route editing takes place without snap. This allows fine adjustment (e.g. via nudging) without large jumps to the next snap point. It therefore provides a smoother editing experience with more solutions. However, if you prefer (or need) to edit at a particular snap setting then you can enable this option to do so.

We don't recommend having this setting on as it will in future be incompatible with design rule aware route editing.

Saving Your Snap and Grid Settings

Like everything else on the Technology Menu the configuration set on this dialogue forms part of the Technology data block. So, while you can make changes persist for the current project it's best to set them and save them in a template so that your preferences are then set for all future projects as well.

To store or update settings in a template:

§. Start a new project via New Project Wizard on the home page.

§. Initialise the PCB from the template you want to change

§. Change the settings in the dialog (or dialogues - anything in Technology Menu is fair game).

§. Save as template via command at bottom of template.


Set Keyboard Mapping

Overview

This dialogue allows you to assign all commands in ARES to keyboard shortcuts of your choice.

Please note that the documentation refers to keyboard shortcuts in their default assignation.

Options

Command Groups

Use this selector to filter the command sets according to which command(s) you want to assign a keyboard shortcut for. All mappable commands are logically sorted into groups and each group is selectable from this combobox.

Available Commands

This view will list all commands available for mapping within the command set specified by the selector above. To specify a command for mapping left click once on the appropriate command (to highlight the command) and then click the mouse in the keyboard assignation box below.

Key Sequence for Selected Command

Specify the keyboard shortcut for the command highlighted in the above viewer. This field is disabled if no command is highlighted. More information on keyboard shortcuts can be found here.

  • Assign - Confirm that the specified keyboard shortcut is to be assigned to the highlighted command.
  • Unassign - This command will unbind the currently assigned keyboard shortcut (as displayed in the text to the right of the highlighted command) from the highlighted command.


Layer Pairs

Overview

The idea behind layer pairs is to allow you to create associations between layers This is useful for example when laying tracks – double clicking the mouse will automatically create a via from the current layer to it’s associated layer and continue tracking on that layer.

To change a layer pair select a layer from the drop down list that you wish to associate with the layer specified by the text on the left.

It is not uncommon for much of this dialogue to be greyed out; you cannot create associations between layers not in the stackup. Also, only signal layers are shown here because you cannot place tracks on plane layers.

See Also:

Smart Vias & Layer Pairs


Set Paths

Overview

This dialogue form allows easier navigation through folders while saving and loading layouts, keeping track of libraries and creating paths to the directory where CADCAM files will be placed.

Options

Initial Folder for Layouts

This is the location to which the explorer tab will automatically open to each time you save or load a layout. Changing this to your own preference can save hassle and make the work process more efficient so you can save and load instantly instead of searching through folders for a layout.

Library Folders

This pane contains the list of folders which your component libraries are contained within.

Default Path for CADCAM output

Specify the default path to the directory where you want your CADCAM files to be placed. By default this should be the project directory but, should you wish to enter a custom path, you can do so. Note that to enter a directory of your choice you must change the radio options to Use Path Specified Above. The path specified here will appear as the default path within the CADCAM output dialogue.

  • Use Project Directory? - When this option is checked the filepath field above will be disabled and the CADCAM output files will by default be exported to the directory containing the current project. Note that you can still change the directory on a per design basis via the CADCAM output dialogue.
  • Use Path Specified Above? - When this option is checked the filepath field will become enabled and you can manually specify a default path for CADCAM output files. This path will appear as the default destination when you launch the CADCAM Output dialogue for the current and future designs. Note that you can still change the directory to one of your preference on a per design basis via the CADCAM dialogue.


Default Text Style

Overview

This dialogue form allows you to configure the default appearances of the part references, values and 2D graphics text in ARES.

Options

Part Reference

These options allow you to configure the default appearance of the part references in ARES.

  • Label Font - Choose the desired font for the text from the drop down menu.
  • Label Height - Enter a value corresponding to the desired height of the text.
  • Label Width - Enter a value corresponding to the desired width of the text.
  • Show - When checked the label will be visible on the layout by default.

Part Value

These options allow you to configure the default appearance of the part values in ARES.

  • Label Font - Choose the desired font for the text from the drop down menu.
  • Label Height - Enter a value corresponding to the desired height of the text.
  • Label Width - Enter a value corresponding to the desired width of the text.
  • Show - When checked the label will be visible on the layout by default.

Graphics

These options allow you to configure the default appearance of 2D graphics text in ARES.

  • Text Font - Choose the desired font for the text from the drop down menu.
  • Text Height - Enter a value corresponding to the desired height of the text.
  • Text Width - Enter a value corresponding to the desired width of the text.
  • Line Width - Enter a value corresponding to the desired line width for 2D graphics text strings.


Board Properties

Overview

This dialogue form allows you to set the work area within ARES up to a maximum of 10 metres squared. Visually, this is the dark blue bounding box on the Editing Window.

It also allows you to specify a board thickness and feature thickness which are used in the 3D Viewer and also in the IDF Output fileset.

Options

Width

Enter a value for the width of the work area.

Height

Enter a value for the height of the work area.

Board Thickness

Enter a value for the thickness of the board.

Feature Thickness

Enter a value for the copper thickness.

Note that the Board thickness and Feature thickness is automated from the Layer Stackup wizard when you create a new project. The Layer Stack up will take precedence over the Board thickness property in this form.


Set Zones

Overview

This dialogue form allows you to set the speed and refresh rate of the zones within ARES, the default values should be fine unless PROTEUS is performing very slowly and struggling with the refresh rate.

Options

Auto Regenerate Zones?

When enabled this option hands control of zone regeneration to ARES which will regenerate zones according to the rules for the Background Regen. Threshold.

Quick Draw Zones

When enabled this option will draw zones with a very light hatching for speed.

Background Regen. Threshold

When you place, move or delete tracking or vias onto a board containing one or more power planes, ARES detects whether the power plane needs to be regenerated and then proceeds by either:

Recomputing the internal boundaries of the zone immediately. On a fast PC (e.g. Pentium 3) and a board of low to medium complexity this real time update mode of working can be quite viable with regen times of the order of 1 or 2 seconds.

The regeneration of complex zones is run in the background such that you can carry on editing; the zone will redraw as soon as the regen process completes. For long and complex regenerations, ARES draws the zone in hatched form whilst its regeneration is pending.

This option determines the number of holes required in a zone for it to be deemed complex and thus processed using background regens.


Set Selection Filter

Overview

Due to is its object oriented design, all objects in ARES are treated in much the same way and we can discuss generally their dragging, copying, movement, rotation, deletion and editing. You should note that traces and vias are not regarded as objects for this purpose; their editing is dealt with further under Manual Routing. However, there are operations where traces attached to objects are affected by operations performed on the object - such cases are discussed here.

The Selection Filter

Board design by it’s very nature consists of several layers (silkscreen, copper layers, edge layer, mechanical layers etc.). Despite this, ARES provides a modeless selection mechanism where the object under the mouse is identified regardless of whether it is on the current layer. This works extremely smoothly in most cases but the selection filter provides the means by which you can override the default behaviour in a given situation.

The selection filter can be found at the bottom left of the ARES application window.

The Selection Filter

The purpose of the selection filter is simply to determine which object types are considered ‘hot’ in any given mode. Additionally, the icon directly to the right of the layer selector determines whether all layers or only the current layer are considered to be ‘hot’. By toggling these icons you can therefore have complete control over both which objects and which layers are hot at any given time.

When the mouse is over a ‘hot’ object a light dashed line will appear to provide instant feedback telling you what exactly the mouse is considered to be pointing at.

The mouse over a component in ARES

Sophisticated algorithms are in place to cater for the cases where, for example, two tracks on different layers are placed in parallel. Whilst the obvious solution is to look for a point on the desired track which is visible on it’s own, the behaviour in such a case is prejudiced by the layer currently selected in the Layer Selector. You could therefore switch the layer selector onto the layer of the trace you want to select and then click on the track.

It is extremely important to realise that this object ‘twitching’ indicates only the object that will be acted upon when you click the mouse. It does not indicate what the action will be (selection, placement, etc.) – indication of action is provided by the mouse cursor and is summarised below :

Standard Cursor

Placement Cursor - a left click will place an object according to mode.

Selection Cursor - a left click will select the object under the mouse

Movement Cursor - a left drag will move the object(s) selected.

Using these two visual indicators together provides an extremely intuitive method for both knowing what object the mouse is over and also what action will be performed when you left click the mouse on that object.

Finally, while considerable time has been given to choosing a sensible default selection set for each mode in ARES you can override it if you decide that you prefer to operate in a different way.

Options

Mode Selection

Select the mode in which you want to configure the default selection rules from this combo-box.

Default Filter State

These options allow you to configure which object types are available for selection by default when the specified mode (as selected from the combo-box above) is enabled. It is important to realize that these options will be the defaults when you switch into the specified mode – you can change these live as required on a case by case basis by toggling the buttons on the selection filter itself.


Set Environment

Overview

This dialogue enables configuration of several application environment preferences.

Options

Pin Tip (tooltip) Delay

Enter the delay time for tooltips to appear when the mouse is hovering over an icon.

Pin Tips

These options allow you to configure when and how pin tips are displayed within ARES.

  • Pin Tip Delay - Set the time after which the pin details will appear as a tooltip when the mouse is hovering over the pin. Entering a zero in this field will disable this feature. If the Display Long Pin Tips option is checked then full pin information will appear otherwise only the pin number will be shown in the tooltip ( with other pertinent information shown on the status bar.
  • Display Long Pin Tips? - When checked full information on the pin will be shown as a tooltip when the feature is enabled. To enable pin tooltips enter a Pin Tip Delay Time which is greater than zero.
  • Display Pin Tip if Shift Key is Down? - When checked pin tooltips will only be visible when the Shift Key is depressed.
  • Display Pin Tip if CTRL Key is Down? - When checked pin tooltips will only be visible when the Ctrl Key is depressed.

Component Pads can be moved ?

When checked this allows the movement of a single component pad when in appropriate pad mode is selected. This can be quite useful but is also potentially dangerous and is therefore disabled by default.

Enable Device -> Package Look up

When checked package lookup is enabled from the Device.xlt file. This option has no effect where projects are created with Proteus 8.x and is included primarily for legacy purposes.


System Info

System Information

Overview

This dialogue provides information on the version of the software you currently have, your customer details and some general information on the layout. You should always have the Labcenter Version number and your customer number to hand should you need to get in touch with us for support or upgrade purposes.


Differential Pairs

Overview

This tab allows you to create and configure named differential pairs.

You need the advanced feature set to route differential pairs in Proteus.

Diff Pair Selection

The top area lets you choose a differential pair which you can then configure in the rest of the dialogue form. It also allows you to create a new differential pair when accessed through the place wire label command on the schematic.

When a differential pair is selected in the combo you can rename or delete it via the buttons on the right hand side.

The linked topic below provides more detailed explanation on how to set up and route differential pairs in Proteus.

Differential Pairs

Net Class

Here you can select a net class to associate with the differential pair. If you haven't already done so you should switch back to the net class tab and create one before assigning it here. Creating a net class for the differential pairs is important as it will allow you to:

  1. Specify trace width for routing.
  2. Scope design rules and set clearances to other objects.

Unlike normal net classes you do not need to place a wire label on the schematic to assign the net class. Instead, you assign the net class to the differential pair in this dialogue form. The differential pair itself has a label on the schematic so Proteus already knows which signals to apply the net class to.

See Also:

Differential Pairs - Net Classes

Clearances

This section allows you to specify additional clearances specific to the differential pair itself. Standard clearances (e.g. to other objects) are determined by design rules in the normal way.

Min Paired Separation

This is the distance between the two tracks used in diff pair routing mode. Any increase from this distance would be considered to be unpaired and can happen either due to cornering, phase match serpentine segments or at the start and end of the routes while making connections to the pads.

Max Unpaired Separation

This is the maximum distance between the two tracks that you consider legal at any time. While the specified value will be enforced for corrective serpentine segments (during automatic phase matching) note that the actual reported maximum in the differential pair report may well be due to an unavoidable fanout or termination routing which you have placed manually.

Violations of the max unpaired length and max unpaired separation will be logged by the Pre-production checker as part of it's differential pair compliance check .

We strongly recommend that you generate a differential pair report from the Project Notes module. This provides more information and clarity about whether your differential pair(s) are compliant with your specified values.

Tolerances

This section allows you to specify tolerances for length matching and phase matching of the differential pair.

Max Phase Shift

Differential pair lengths are matched against each other. However, to ensure that the differential signal is as close to opposite as possible the track lengths need to be matched after each corner or unpaired section.

Max Phase Shift is therefore defined as the allowable difference in track length due to a diversion or corner before serpentine routing is applied to one track to equalise their lengths.

Note that the start and end of corners depend on the direction that you route the track. Since corrective action is taken at the end of a corner the result will be different depending on where you start and finish the route..

You should therefore always check that the differential pair direction is correct after routing. This is noted in the differential pairs report or can normally be worked out from the position of the corrective serpentines. If need be you can change the direction (and therefore the phase matching) via the 'Reverse Route Direction' command on the track context menu.

See Also:

Phase Matching

Length Match Tolerance

If you match the diff pair against a target length this is the allowable difference between the length of the differential pair and the specified target length.

If you match the diff pair against another diff pair then this is the allowable difference in length between the two after matching is complete.

See Also:

Length Matching vs Phase Matching

Max Unpaired Length

This is the maximum distance that you consider legal for any deviation from the paired separation. It is not specifically enforced by the system but it is reported along with the actual maximum in the differential pair report.

Unpaired length generally results from serpentine segments used to equalize the track lengths. To correct an overly large unpaired length you need therefore to look at the corners during routing (causing the length mismatches) and/or the max unpaired separation specification (influencing the distance that the tracks are unpaired for). It can also result from fanout from the source/receiver pins, covering the etched track distance used to get from the two pins into a paired state. Generally this is routed manually by the user and is unavoidable.

The longer of the two distances is used/reported.


Edit Rules

Options

Name

The name of the rule being created / edited.

Apply to Region

Select the desired region if you want to configure the currently selected design rule to apply only in a specified area. The region can be a layer, a layer goup or a design rule room that you have placed on the board.

Apply to Net Class

Select the desired net class if you want to configure the currently selected design rule to apply only to that net class. Note that only named net classes are listed in this selector – see the help manual under Netlist Management – Routing Classes for more information on creating net classes

With Respect to

These options allow you to further configure the currently selected design rule by applying a filter to the net class selected above such that the rule is enforced either only against objects on the same net class or only against objects on another net class. Note that these options are disabled when the currently selected rule applies to all net classes.

Clearances

These options allow you to specify various design clearances for the currently selected rule. Note that when a rule is restricted to a particular net class there the Graphics Clearance and the Edge/Slot clearance options are disabled as their meaning is ambiguous.

  • Pad-Pad Clearance - Specify the minimum pad-pad clearance for the currently selected design rule.
  • Pad-Trace Clearance - Specify the minimum pad-trace clearance for the currently selected design rule.
  • Trace-Trace Clearance - Specify the minimum trace-trace clearance for the currently selected design rule.
  • Graphics Clearance - Specify the minimum clearance between sikscreen graphics objects and other objects for the currently selected design rule. This rule is disabled if the current design rule is for a specific net class with respect to either the same net class or to all other net classes.
  • Edge/Slot Clearance - Specify the minimum clearance between the edge layer graphic and other objects for the currently selected design rule. This rule is disabled if the current design rule is for a specific net class with respect to either the same net class or to all other net classes.

You can set this rule to zero for a design rule room which will disable the edge/slot clearance in this rule. This can be useful where you have slots near pads or edge connectors.

  • Apply Defaults - Use this option to apply the clearances for the Default Rule (as specified in System Menu-Set Default Rule) to the currently selected design rule.


ROUTE COMMAND CENTRE

Overview

Route Command Centre

The route command centre (keyboard shortcut 'R') is the place to adjust your route placement and editing configuration. It can be launched from the keyboard shortcut at any time. This includes during actual route placement which allows you to change route widths or change routing options while in the middle of placing a route.

Push and Shove Options

These commands toggle push mode on and off and apply to both route placement and route editing.

Push Shove Mode (SHIFT+P)

This is the main behavioural toggle, switching Push mode on and off.

  • When push mode is on the track being placed or edited will move other tracks (and vias where selected) out of the way while maintaining design rule clearances.
  • When push mode is off, route placement happens in FMR mode where you can hug other objects but not move them. Route editing is similarly unable to move other objects on the board.

Allow Via Pushing (SHIFT+V)

This allows the route being placed (or edited) to not only move tracks but also vias as well.

It's very useful but it can disturb routes on more than one layer and therefore require more tidy up. Generally speaking, it's best left on since most via pushes are small nudges.

Bear in mind that via pushing can slow things down a lot, particularly if you are nudging a group of closely positioned vias on a multi-layer board. The best thing you can do to mitigate this is left click to place an anchor as soon as you have moved the vias to a suitable position. Placing an anchor will commit the route so far (you can still unwind by moving the mouse back over the route) and all of those push calculations no longer need to be made on every mouse move as you continue with the rest of the route placement.

If you're trying to push a via and it's not moving it could be blocked by an immovable object on another layer.

No Entry Sign vs Push Limit Cursor

If a push fails (either in placement or in editing) it's almost always because one of the objects being pushed has hit an obstacle. In this case you'll get a no-entry sign. Bear in mind that the object getting stuck can be on another layer if you are pushing vias or can be outside of the current viewing area if pushing large tracks.

No Entry Cursor indicates no legal path to continue.

There is also a maximum limit of objects that can be pushed. It's quite rare to see this but it basically means that you need to either:

  • Left click to anchor the push so far. This will commit all of the tracks and vias being pushed and reset the count.
  • Move the mouse backwards and try a different route.
  • Launch the Route Command centre and toggle off via pushing. Often it is vias that result in a situation of a pushes b pushes c and so on in different layers of the board.

Push Limit Cursor and Status Bar Change.

Route Placement Options

These options are specific to route placement and apply regardless of whether Push mode is enabled or not.

Enable Click To Complete (SHIFT+S)

Click to Complete is a calculated solution to the destination shown as a 'shadow track' in front of the route being placed. You can complete the route at any time by pressing the ENTER key.

Click to Complete showing Shadow track to destination.

Notes:

  • When you are pushing tracks Click to Complete will not attempt to find a solution.
  • You may want to turn this option off if you have a very large and complex board and it is causing a performance overhead.

Use Curved Corners (SHIFT+C)

This switches the corner type of the route being placed from mitred to curved.

Current Route Style

These options affect only the route being placed and so are only enabled when Route Command Centre is launched during route input.

Trace/Neck Style

Set the trace and/or neck style for the route being placed. This allows in-route overrides of the default track widths set up in the Net Classes tab of Design Rule Manager.

The values set here will apply to both the internal and the external trace width / neck widths.

You should always set trace widths in the net classes tab. These options are intended to provide 'when needed' local overrides, not introduce a completely different way of working.

Use Neck Style (SHIFT+N)

Choose to switch to the specified necking route style. This can intended to be toggled on and off interactively using the keyboard shortcut at points where the full route width does not allow the route to pass.

This is not the same as auto-track necking. It is an absolute switch to the neck tracking style, irrespective of whether it is actually needed at this point in the route.

Applied from

Choose whether the route width changes you've selected apply from the start of the route or from the current position of the route.

Enable Auto-Necking

Choose whether or not auto track necking should be attempted (when full route width is blocked) in the route currently being placed.

Route Editing Options

The main decision for route editing is DRC awareness (gated on the SHIFT+A shortcut).

When DRC awareness is active:

  • The editing of placed tracks will obey all design rules.
  • You can push other objects during route editing (if Push mode is enabled)

This makes it much easier to tidy up the PCB following push routing or generally to hug/group tracks together and maximise the space available on the board.

When DRC awareness is turned off:

  • The route being edited will see no obstables and move straight through anything else on the board.
  • Visual DRC will indicate (via yellow border) when you are in a illegal position but nothing will prevent you getting into an illegal position.

DRC aware route editing is almost always going to be helpful and is enabled by default. However, DRC aware routing off is also needed in some situations, where things are very messy (e.g after a component block move) and you need freedom to manually untangle the situation without hindrance.

Another case might be where no legal edit is possible for the track you want to move. For example, the pad-trace design rule means that the route is in violation at the pins of the IC and your edit can't change that. In this situation you should look at the DRC rules and possibly use a DRC room around the IC if need be. However, if you want to make the edit regardless of the violation you can toggle DRC awareness on and off with the SHIFT+A shortcut key.

When you turn off DRC aware editing the Visual DRC shroud acts as a design rule guide. The outer ring will change colour if there is a violation anywhere on the route and trace segments in violation with the currently edited route will also be re-coloured. This helps move a route out of violation and alerts you if another violation takes place during the edit.

Use SHIFT+A to toggle DRC route edit awareness and remember that the status bar will show you which mode you are in.

See Also:

Visual DRC

Enable Snap when Editing

Editing operations are gridless and smooth with any location being a potentially valid one. This means for example when moving a via that any legal free space point is available for the via move. It also means that with DRC awareness on you can drag a track to the closest legal point to an adjacent track.

Turning snap with editing on is potentially helpful where all the pins of your IC's have the same pitch as you can then set the snap to that granularity and line things up easily. However, in the vast majority of cases this is not true and the option best left disabled.

Turning this option on will vastly reduce the effectiveness of DRC aware editing since legal positions are now dependent on both design rules and current snap grid. Having snap on will also result in poor performance with Push editing since the number of legal destinations for the push is drastically reduced.

Minimum Segment Length

Minimum segment length imposes a lower limit on the length of all segments when route editing. That is, editing a route in such a way that would result in a segment smaller than this limit will not be permitted and the last valid solution will be presented. This limit can be modified during route editing operations but, does not act post-process to change existing segments.

If you turn this on you may find that some editing operations that you would expect to succeed get stuck because the solution would create a segment which is smaller than the minimum segment length you've chosen. If this happens, you can either route a different way or change the value in route command centre. Setting it to '0' will disable it.

Setting this can result in very confusing situations if you are not careful. For example, if you set minimum segment size to 20th and then try to move a via you may well not be able to because moving the via along a track will change the sizes of the track segments and none can now be below 20th. This is not obvious.

Similarly, trying to drag a vertical track slightly sideways or a horizontal one slightly vertical will create short track segments. With a minimum segment size in force such operations may not be possible and it can be hard to understand why the edit has failed.

Visual DRC

Visual DRC in push mode showing clearances around immovable objects.

Visual DRC provides more information about the area around the mouse when routing a track. It expands the objects in this area by their design rule clearances, allowing you to see where obstacles are likely to be and how best to plot a route across the board.

In the example picture above we have set the checkbox to highlight only immovable obstacles. This is very helpful in push mode; you can see instantly that the tracks from U7 and T8 can be pushed whereas the tracks from T5,U6 and U8 cannot (because they are length matched in this case).

If we turned push mode off and were routing in FMR mode then all objects are immovable and the viewport would look more like this:

Visual DRC in FMR mode - all objects are immovable

You can turn visual DRC on and off via the SHIFT+D keyboard shortcut and can adjust the viewport size from inside route command centre. You can also choose to highlight all objects even in push mode in this dialogue.

When editing a track and DRC awareness is off Visual DRC gains additional features to help guide the route editing operation. First, the border of the viewport will colour yellow if the route being edited is in violation against any object anywhere along the route. This is especially helpful if you are moving a larger route at high zoom as you can easily cause a violation somewhere outside of the viewing area.

Viewport border colour indicates a violation somewhere on the route (via below).

Second, if the segment of the route being dragged overlaps the clearance of another object that will be highlighted to show that you have moved into violation. This allows for fine control over editing in the area around the mouse.

Here the route is being dragged right and collided with adjacent route clearance.

Viewport size

This slider allows you to change the size of the circle that displays the Design Rules.


Tag Connections

Tag Track Connections

Overview

Tag Connections is used to select all connections between two components, regardless of whether they transition layers or are tapped / forked at via points. It's a really helpful tool on busy boards, especially when you want to:

  • Length Match / Net tune busses where the lines are via'd up and down.
  • Length Match with daisy chain / fly-by.

An Example where you might want U1->U2 to be equal length and U2->U39 to be equal length

Options

Components

Select the two components for which connecting lines should be selected.

Additive

The Additive field allows you to select multiple different component options consecutively. Existing selections will remain tagged and connections matching the new criteria will be added.

Ignore Power Rails

Removes power net connections from the selection. This option should be selected when the purpose of selection is subsequent length matching for example.


Auto Name Generator

Overview

This tool provides a semi-automatic way of annotating the layout. You can provide a name stem and an increment quantity and then consecutively left click on the footprints you wish to annotate. Note that you need to re-enter the tool and hit the cancel button to exit assignment mode.

It is very important to understand that the automatic annotation provided on placement is consistent with ISIS on a netlisted design and renaming footprints with this tool on a netlisted layout is not recommended.

Options

String

Enter the name stem for the parts you want to name. For example to name 3 components fred1,fred2 and fred3 enter fred in this field as the common stem.

Count

Enter the initial count value for the parts you want to name. Each named part increments the count from this value.


Auto Placer

Overview

This tool allows for automatic placement of the netlisted components onto the layout. You must have a continuous board edge before running this command otherwise ARES does not know into which area to place the components.

Options

Component Pane

This pane show a list of all the components still to be placed. When the dialogue form is first displayed the components are listed in alphabetical order with all the components selected for placement.

Design Rules

These options allow you to configure the design rules for placement of the components on the board. Context sensitive help for each is available in the usual way with the mouse over the appropriate option.

  • Placement Grid - This defines the step size used by the auto-placer when trying to find a position for each component. This should always be set to a multiple of the grid size you are going to use for auto-routing. Values other than 100th, 50th or 25th would be highly unusual.
  • Edge Boundary - This defines the minimum distance to be allowed between any component and the edge of the board as drawn on the edge layer.

Preferred DIL Rotation

As it is seen to be desirable that DIL packages all have the same orientation they are treated as somewhat of a special case. This option is therefore available to specify the preferred rotation for these packages. It is set to horizontal by default but the shape of your board may dictate that vertically placed DIL packages may better use of the available space. Two further controls in the cost weightings group on the dialogue form define how heavily penalised a component will be if the package is placed with either 90 or 180 degree rotation from the default. If you are not concerned about the orientation of your DIL packages then set these costs to zero.

Options

There are two important options here:

  • Push and Shove - The auto-placer recognises two types of component, those initially placed by the user which are deemed to be fixed and immovable and those placed by the auto-placer which may or may not have been moved by the user. The latter will be pushed and shoved around the board where possible in an attempt to best place the remaining components. This shuffling can become restrictive and counter-productive on boards where the pre-placed components are in the centre of the board. In such cases Push & Shove should be disabled.
  • Bottom Copper - When selected placement will take place on bottom side of the PCB rather than the default top side. If you want placement on both sides you should set up placement rooms and then group components accordingly.

See Also:

Component Groups and Placement Rooms.

Trial Placement Cost Weightings

Auto-placement is achieved by trying the next component at various positions on the board in an attempt to minimise a number of key factors. The relative importance of these factors is determined by the value in each of the seven categories. Help on each topic is available in the usual way with the mouse over that topic. These weightings define the importance of grouping components together. This can be particularly important for things like decoupling capacitors.


Auto Router

Overview

All autorouting operations – regardless of the mode of operation - start by invoking the Autorouter command on the Tools Menu in ARES. This topic discusses the various configurations on the dialogue form.

Note that the despite it’s seeming complexity, the basic operation of the router is extremely simple. Many configuration options are provided for additional flexibility and the default values are sufficient for all but the most complex of boards.

Options

Execution Modes

The main section of the dialogue form allows you to choose one of four execution modes; Automated Routing, Scripted Routing (run a script file), interactive routing (type routing commands) or, if you have a copy of ELECTRA, to launch the ELECTRA Autorouter and route the board externally. Some of these radio buttons may be disabled based on the following rules:

  • If you have a PCB Design Starter Kit, a PCB Design Level 1 or a PCB Design Level 1+ then the Scripted Routing mode and the Interactive Routing Mode will be disabled.
  • If you do not have a license for the ELECTRA autorouter or ELECTRA is not installed on your computer then the ELECTRA Mode will be disabled.
  • The Language Reference Manual and practical examples of working in scripted and interactive mode can be found in the main help documentation (Help Menu-ARES Help).

Several additional options are available in the fully automated mode. Whilst in most cases the default settings will suffice these options provide extra flexibility for more complex or densely packed PCB’s.

Fanout Passes

These passes will autoroute small escape wires with a via from SMD pads, thereby allowing easier connection to the pads during the main routing passes.

Routing Passes

The number of principle routing passes. There is only marginal benefit in increasing this beyond 50; for complicated or densely packed boards we recommend increasing the repeat phases rather than the number of routing passes.

Cleaning Passes

Cleaning passes will basically rip-up and reroute each net with high via cost and the highest cost for making clearance and crossing violation. The default value is adequate for almost all boards.

Repeat Phases

This allows you to specify the number of times the routing passes and cleaning passes will repeat. The ARES Autorouter is an adaptive shape based router so repeating the route/clean passes will typically help achieve higher completion. The default value is adequate for most boards but increasing the repeat value will have benefit in more complex or densely packed layouts.

Filter Passes

The filter pass will be performed after the router has repeated the route/clean passes the specified number of times. This will simply rip any tracks that have conflicts at the time of invocation. The default value for this is fine for almost all layouts.

Recorner Pass

This pass is performed last and changes 90 degree wire corners to 135 degrees to reduce track length.

Routing Rules

These options provide additional guidelines to the router and indicate the default behaviour for the routing algorithms. As with the scheduling options detailed above, the default values will suffice for the vast majority of boards.

Wire Grid

Specify the default wire routing grid. This advises the router as to the preferred grid for placing tracks but does not actually constrain it to routing on that grid.

Via Grid

Specify the default via routing grid. This tells the router the preferred grid for placing vias but does not constrain it to routing on that grid.

Allow Off Grid Routing?

This option, defaulted to on, determines whether the router is constrained to routing on grid (grid based routing) or is able to route off grid when necessary. We strongly advise leaving this option enabled as disabling this option will adversely affect router performance in most cases.

Conflict Handling

The ARES router works on a costing basis so it first places all tracks according to their ‘ideal’ position and then increases the costing of illegal tracks until there are no conflicts remaining. This means that in the unlikely event that the router does not achieve completion there will be illegal tracks placed on the boards and these options allow you to configure how you would like ARES to handle such tracks.

Treat Conflicts as Missing

In this case when the router is aborted or stops any tracks that cross other tracks or are deemed illegal are ripped from the layout and the connection will revert to a ratsnest line in ARES.

Treat Conflicts as Illegal Tracks

When selected, all conflicts will be left as illegal tracks (showing design rule violations and flashing in yellow). Note however, that is possible (particularly if the user aborts the router) that you can have a very large numbers of conflicts early on during the routing process and trying to sort out such a tangle in ARES is more or less impossible.

Command Buttons

The Begin Routing button is the button that invokes the router and commences the auto-routing of the board. Two additional buttons for exporting a design file and importing a session file are provided for users with the SPECCTRA™ Autorouter, whilst the Reset to Defaults button will reset all the configurable options to their initial values at installation. Finally, the Cancel button can be used to return to the ARES Editor without invoking the autorouter.


AUTOMATIC ANNOTATOR

Overview

This command is used to renumber the components to give a geometrically sensible placement order. If you prefer your annotation to be in logical order then you should set annotation offsets in sheets on the schematic and then use the global annotator from the tools menu in ISIS.

Options

All placed

This is the default selection and will apply the annotation to all placed components on the board.

Tagged only

When this option is chosen, annotation will apply only to the selected area of the board. This can be useful where you are duplicating circuitry (e.g. channels on an amp) and you want to re-annotate one channel.

Duplicating circuitry should never be done as a simple copy and paste. Either Project Clips or the Replicate Command should be used. See Multi-Sheet Designs Examples in the Schematic reference manual for some worked examples.

Use Sheet Offsets

When checked any initial annotation offsets that are set in the sheet properties on the schematic will be applied/honoured during the annotation pass.

Board Side Order

Select whether you wish to annotate either component or solder side first or both simultaneously.

First Side

Specify the start point and the direction for the annotation on the first side.

Second Side

Specify the start point and the direction for the annotation on the second side. This will be disabled if you choose to annotate both sides simultaneously in the board side order combo.

Configuration View

This is a visual preview of the currently configured annotation on both component and solder side.

Notes:

§. If live netlisting is enabled the annotation changes will seamlessly reflect back to the schematic without any further action on your part. If live netlisting is turned off however, the act of re-annotating in ARES will apply the changes to the schematic and then lock the layout as it involves a netlist change which - in this mode - you must manually confirm.

§. Obviously, the position of parts on a layout is completely arbitrary and any attempt to sensibly re-annotate the board relies on heuristics. While generally a global re-annotate will perform sensibly it does very much depend on the individual board topology and you may need to make some manual adjustments.


Design Rules

The dialogue form allows you to edit the design rules of the board and examine which rules apply in different regions of the PCB. There will always be at least one design rule called default which applies to all layers and signals on the board in the absence of any others.

The Region Tree

The left hand side of the dialogue is a tree view of the regions currently on the board. By default the tree will be two levels deep corresponding to the board (top level) and then the individual layers. If you add a design rule room it will appear as a third level on the layer(s) that the room applies to

Creating a Design Rule Room on Top Copper and it's appearance in the Region Tree.

When you select a region on the tree the right hand side will update to show you the rules that are in force across the entire selected region. You won't see the rules for a room in a layer because the room doesn't cover the entire region and you won't see the rules for a layer when you select board for the same reason. It's very possible however that you will see the rule for the board when you select a layer - indeed, this is the default situation for a new design. This is because smaller regions will inherit rules from larger regions unless a specific rule is set for the smaller region. You'll see that if you click on the top copper layer the default rule still applies - it is shown in a light grey to indicate that it is inherited from a larger region (the board rule in this case).

The Default Rule applies to Top Copper because we haven't created a Top Copper Rule.

The Rule List

As we've seen the right hand side shows you the list of applicable rules in the currently selected region. Rules which are created with a scope of the current region are drawn solid and rules which are inherited from a larger region are drawn in a light grey. Double clicking on an entry will pop up the edit rule dialogue and allow you to make changes to the design rule.

Normally, it's pretty easy to work out and check that things are correct but there are some subtleties where multiple rules apply. Consider the example below:

Specific Electrical Rules mean multiple rules can apply in a region.

Inside the room there is a rule for signal traces (in black). However, other objects in the room are not affected by this rule and so inherit rules from larger regions. The Top Copper Power rule applies and so objects on the power net class in the room will use these clearances. The HPWR rule applies to the whole board for high power tracks and, since that hasn't been overridden in the room, those clearances will also apply to relevant objects in the room. Finally, the default rule for the whole board will apply to anything not relevant to any of the other rules.

For the current selection in the region tree the applicable rules will be presented in order of descending priority. This is helpful in understanding which rules apply first (e.g. a specific net class rule will be applied before an all net class rule) in a given layer or region.

Note that we could remove all of these dependencies by creating a rule that applied to everything in the room.

A Rule with no Electrical Filter in a Region will apply to everything in the region except where another rule with an electrical filter exists.

Now the picture is much clearer. The SIGRM rule will apply to the signal net class inside the room and the ROOMALL rule will apply to everything else inside the room. No rules are inherited from larger regions because everything inside the room is covered by at least one rule scoped to the room.

Design Rule Hierarchy

We've seen that adding rules can override other rules and this can generally be quite intuitive. For example, you would expect creating a rule for top copper to override the rule for the whole board on top copper. This is an example of the design rule hierarchy in action. The full design rule hierarchy is summarised below along with a link to the full topic in the reference manual. We strongly recommend reading through this topic to make sure you have a firm grasp of rule priorities.

Design Rule Priorities. Higher priority rules will override lower priority rules within their scope.

See Also:

Reference Manual: Design Rule Hierarchy

Editing Options

Enable Design Rule Checking?

Uncheck this option to disable live design rule checking.

This is not recommended. If you turn design rule checking off the software will not warn you of copper violations.

New / Clone / Edit Buttons

These buttons launch the edit rule button where you can specify a scope for a design rule and set clearances.

- Using the new button will result in the creation of a new design rule.

- Using the clone button will result in the creation of a new design rule with all the clearances defaulting to those in the currently selected design rule. This button is disabled unless a design rule is selected.

- Using the Edit button will result in the currently selected design rule being changed. This button is disabled unless a design rule is currently selected in the rules list.

You can also edit a rule simply by double clicking on it in the rules list.

Delete Button

This button allows you to delete the currently selected rule. Note that the default rule cannot be deleted in order that some copper cleareances apply in the event of no other rules being present.

All / Applicable Radio Buttons

The applicable option means that the rules list will show you the rules that apply to the region you have selected in the region tree. When you select all the full list of rules will be shown but you will have no indication of where any given rule applies (the region tree is disabled). We strongly recommend that you only use the All Rules view for auditing purposes and use the Applicable Rules view for normal operation and inspection of the board constraints.


Net Classes

Overview

This dialogue forms allows you to set the trace and via styles to be used for connections, and also the layer sets for the autorouter.

Options

Net Class

Select the net class to be configured. Selecting a different net class saves the changes made to the current one.

You can add new net classes so that when you 'save as template' the technology data stored in the template will include the net class configuration. This is useful when you want to re-use constraints across multiple designs and safe as an unused net class in a layout will have no effect on the board.

Routing Styles

These options are used to determine the trace width, neck width and via style used for the currently selected net class. They will be used when manual routing provided that auto-trace style selection is enabled (Tools Menu) and also when auto-routing.

  • Trace Style - Specify the name of the trace style to be used for connections assigned to the edited net class.
  • Neck Style - If not blank, this field enables Auto Track Necking for the autorouter, and defines the style which it will neck to.
  • Via Style - Specify the name of the via style to be used for connections assigned to the edited net class.

Given differences in airflow it can be helpful to thicken tracks slightly on inner layers versus outer layers. You can opt to have different trace widths on inner layers by enabling the checkbox and then entering the appropriate styles. These options are enabled only for non-default net classes.

Set different trace widths on inner layers.

Via Type for Autorouting

Select the via type to be used with the net class to be edited.

Normal: Tells the auto-router to place a standard thru-hole via with this net class.

Smart: Tells the auto-router to examine the specified drill spans for the board (set in the layer stack) and choose the smallest drill range that gets from source layer to destination layer.

Ratsnest Display

The ratsnest display allows you to change the colours of the ratsnest display or to just show certain parts of the ratsnest. For example you can set your power lines a different colour from your signal lines, or you could hide the signal lines temporarily while you sort out the power lines and vice versa making the ratsnest easier to use and visualise where connections need to be made.

Layer Assignment For Autorouting

Each net class can involve up to 8 layers on which connections assigned to it will be routed by the autorouter. The (H) layer is for predominantly horizontal routes and the (V) layer for predominantly vertical routes. Single sided routing can be achieved by specifying the same layer for both H and V routes.

Priority

This is used by the autorouter - connections assigned to the highest priority (smallest number) net class will be routed first. Net Classes with the same priority will be routed simultaneously. This will probably result in the router spending much more time 'mapping', but may lead to higher completion rates than routing them in turn, especially on single sided boards.

Testpoint Rules

Set minimum testpoint requirements for all nets in the currently selected net class. By default, this follows the global setting found on the defaults tab of this dialogue form but you can override and set specific requirements as needed. It follows that there are essentially three ways of setting requirements:

§. Set the default minimum to 0 and leave everything following global = no testpoint requirements.

§. Set the default minimum to 0 and uncheck follow global where needed.

§. Set the default minimum to a value (e.g. 2) and edit per net class to adjust or set to zero.


Power Plane Generator

Overview

This tool is used to place a power plane on a specified layer of the board. Note that you must have a contiguous board edge before invoking this command as ARES needs to know which area to flood fill.

Users with the Advanced Feature Set who wish to place a partial power plane, a split plane or a keepout inside a plane should use the power plane icon to enter placement mode.

Options

Net

Choose a net for the power plane. If no net is specified, the power plane will connect to any pads which are marked for Thermal or Solid connection. Note that only named nets can be selected here. You can name a net using a wire label on any wire of that net on the schematic.

Layer

Choose a layer for the power plane. The number of available layers depends on the number of copper layers specified in the layer stackup.

Boundary

Choose a boundary style for the power plane. This is the thickness of the pen used to render the boundary of the zone. For almost all purposes the default is fine.

Edge Clearance

The power plane will step away from the edge of the board by the amount specified in the design rule manager for edge clearance. Since this value is rule specific and you can create single layer design rules it follows that you can define different edge clearances for power planes on different layers.

Clearance from Pads and Traces

Any border of the zone is considered to be a trace for design rule purposes. It follows that the clearance from a pad to the zone is the pad->trace clearance of the design rule currently in force. Similarly, the clearance between a trace running through the power plane and the border of the power plane will be the trace->trace clearance of the currently enforced design rule.

See Also:

Setting Design Clearances.


Search and Tag

Overview

The search and tag tool provides a quick and easy way to highlight parts within ARES and is a very powerful design aid. The OR and AND search and tag dialogues can be used in conjunction with the original search and tag. Once you have performed your first search and tag if you want to expand it you can use the OR search and tag function to highlight extra components of a different string. If you wish to decrease the amount of highlighted components you can use the AND search and tag to be more specific. It works in the same way OR and AND functions work in mathematics. For example if you were to search and tag "R" you would highlight all of the resistors, then if you were to OR search and tag "C" it would highlight all of the resistors and capacitors. If you were to then AND search and tag "100" it would only highlight the resistors and capacitors with a value of 100.

Options

Field

Select the property which you wish to use as the seed of your search from the drop down list.

String

Enter the condition which you want to associate with the selected property in order to define the search criteria.

Mode

Select one of the options below to define how the specified string is tested against the selected property.

Range

Specify the range over which the search is to be carried out.


ZONE INSPECTOR

Overview

The Zone Inspector dialogue provides summary information on all of the power and ground planes used in the layout. It has three main functions:

  1. Design Review. You can easily analyse zone configuration settings and also check the impact of part placement and tracking on the zone integrity.
  2. Zone Locator. You can quickly tag a zone in the grid and, if needed, then zoom the editing window around the zone.
  3. Zone Editing. You can launch the Edit Zone dialogue for any plane directly from the Zone Inspector.

Layer Selector

List of Layers used in the Board

This area of the dialogue form is a listing of all of the layers currently defined in the Layer Stackup. Layers which have no power planes will be listed for completeness but will be disabled. The number of planes on a given layer is indicated on the right hand side of the layer name as well as the percentage coverage of the layer by planes

The default view of the data grid shows all of the power and ground planes on the entire board. The primary purpose of the layer selector is to refine the contents of the data grid to a particular layer by selecting that layer from the list.

Data Grid

The data grid contains information about all planes in the currently selected scope. The scope is either the full board or a single layer as specified by the layer selector on the left hand side of the dialogue.

The data can be re-ordered by any column by clicking on the column title at the top. This is useful if you are planning to review all zones with a certain property (e.g. Net = +12V) or to give you an overview of best to worst (e.g. Pieces column).

Layer

The colour blob is a layer indicator and matches the colour used on the layout and as shown in the Layer Selector on the left. This is the default ordering column ensuring that planes are grouped by layer when in full board view.

Net

Lists the net that a given plane is assigned to.

Net Class

Lists the net class that a given plane is assigned to.

Type

Specifies the type of the plane. Options are Solid, Empty, Hatched, Diagonal Hatch or Compatible.

Compatible Zones are entirely blind to connectivity and design rules. They are dumb blocks of copper. As such, we do not advise or recommend their use. If you really need to use be very careful as the software cannot warn you of connectivity or clearance problems.

Full Board?

Indicates whether the plane has been set to cover the full board. This can either be done at the point of layer stackup by defining a plane layer or via the lock to board edge option on the Edit Zone dialogue after placement.

Lock to Board Edge ensures maximum coverage on the layer.

Pieces

Specifies the number of pieces that the zone has been splintered into following placement. For example, a track running through the plane will split it into two pieces and the routing to an IC may leave sliver pieces in between the pins. You can think of this column as an indication of how badly the zone integrity has been affected by the rest of the layout.

Islands

Specifies the number of islands on the plane. An island is a piece (as discussed above) that has no connectivity. Often they are therefore considered redundant and can be suppressed via the option on the zone dialogue form.

Use this checkbox to remove unconnected pieces of plane from the layout.

Stitching Vias

When a plane has been stitched automatically (via the zone stitching or zone shielding commands) this column will display the number of vias used the stitching or shielding.

Coverage

This column provides a percentage coverage for the copper area of the plane against the total area of the layer. It will be approximate and will not account for things like relief connection spokes.

Buttons

Bring to Front

Bring the currently selected zone to the front of the drawing order on the layer. The effect of this is that the zone will be drawn first and will punch out holes in other zones (other zones will redraw around this one).

Move to Back

Send the currently selected zone to the back of the drawing order on the layer. This has the effect that the plane will draw around all existing objects, including zones.

Edit Zone

Launch the Edit Zone dialogue form for the currently selected zone. Disabled if no plane is selected in the data grid.

Zoom In

Zoom the editing window around the currently selected zone. This action can be repeated multiple times to view at increased magnification. Disabled if no plane is selected in the data grid.

Zoom to Board

Reset the zoom level of the Editing Window to full board view.


Displayed Layers

Overview

This dialogue form allows you to choose the layers that are displayed and provides a live update on screen of the currently selected layer set. It also allows you to switch between saved colour profiles and to create your own colour profile(s).

A colour profile is simply a saved set of colours corresponding to the selection of the options on this dialogue form. Two profiles are provided as standard - one for screen usage and a second for printing. For the majority of users these will suffice without modification, although you are free to change or create your own as required.

Options

Colour Sets

Colour sets allow you to configure various different layer visibility options into named groups, including paper colours and solder resist/paste mask visibility. You should then assign a colourset to a keyboard shortcut for easy access. Typical examples might be:

  • ALL : All of the layers turned on.
  • TOP: Top copper, top silk, top resist, top paste, ratsnest, board edge.
  • BOT: Bottom copper, Bottom silk, Bottom resist, Bottom paste, ratsnest, board edge.
  • INNERX: selection of inner layers in use with the current project.
  • TOPASSEMBLY: Top Assembly layer, Edge Layer and Draw Component Assembly Checkbox. Maybe a mech layer if additional info is there.

Colour sets are also useful for printing, with both a MONOCHROME and a white paper option.

Displayed Layers set up for Top Assembly view. Note the keyboard shortcut - really useful for toggling between full board view and assembly plot or other view.

Layer Check boxes

When checked the selected layer will be visible on the layout.

Layer Colour Boxes

The colour of any given layer can be changed by clicking on the colour checkbox and adjusting as required. Some care is required if the paper colour is being changed to ensure that a sensible result is achieved where colours overlap (traces on different layers). As a general rule of thumb, if you choose a light paper colour (e.g. in the WHITE_PAPER profile) then choose secondary colours for the specific layers whereas with a dark paper colour (e.g. in the BLACK_PAPER profile) you should choose primary/strong colours for the layers.

Display Options

  • Draw Component Assembly - When enabled, the automatic component assembly plot information will be drawn as will any manual component assembly information (stored in a package). Useful only really in Assembly plot view or maybe if silkscreen idents are suppressed. Component assembly graphics are not selectable or movable directly, you must select and move the component.
  • Draw Full Solder Resist - When enabled, a full solder resist (including pad expansions) is displayed on screen. You can adjust the brightness of this layer via the Thru-View Settings if you are working in hardware accelerated mode.
  • Draw Full Paste Mask - When enabled, a full paste mask (including pad coverage) is displayed on screen. You can adjust the brightness of this layer via the Thru-View Settings if you are working in hardware accelerated mode.

See Also:

Assembly Drawings


Goto Component

Overview

This command provides a fast and simple way to locate a footprint on the layout. Simply type the reference for the footprint (e.g. U3, C34, etc.) and the display will zoom and center around the footprint.


Goto Pin

Overview

Enter the name of the component pin that you want the viewer to pan to.

Options

Component ID-Pin

Enter the name of the component pin to center the screen on and highlight. Separate the component name and the pin number using a hyphen. For example, entering U1-6 would focus on U1 pin 6.


Goto XY Coordinate

Goto POSITION

Overview

This dialogue form allows you to move to specific coordinates within the ARES viewer relative to different origins. This command is typically used to accurately position the mouse for placement.

The behaviour of the dialogue will depend on whether you have polar or cartesian co-ordinates specified (View Menu)

Options

X Coordinate (Cartesian)

Enter the x-co-ordinate of the absolute position that you want to go to.

Y Coordinate (Cartesian)

Enter the y-co-ordinate of the absolute position that you want to go to.

Radius (Polar)

Enter the radius from the specified origin that you want to go to.

Angle (Polar)

Enter the angle offset that you want to extend to.

Relative to

Choose the origin you wish the coordinates to be relative to. The database origin is internal to the software, whilst the current origin is either the default or the false origin if you have specified one.

See Also:

Replicate Command

Making a Circular Footprint (Tutorial)

Positioning commands will snap the mouse to the current grid after execution. For accurate placement you therefore want to select as fine a grid as possible before executing this command (particularly in polar mode).


Thru-View Settings

Overview

This dialogue form allows customization of the thru-view display engine.

Options

Graphics Mode

Check the different box depending on which graphics mode you wish your computer to use, some graphics cards will support Open GL in hardware.

OpenGL mode typically uses less memory in the PCB layout module and especially in the 3D viewer. This can be important for large projects that are near their memory limit

Opacity

Here you can select the opacity of various layers on the board, adjusting these values will effect the prominence of their display.

Auto-Pan Animation

This provides control over the smooth panning of the board.

  • Panning Distance - Setting the distance moved.
  • Number of Steps - The smoothness of the scroll (the more steps the smoother the scroll).
  • Pan Time - The speed according to personal preference.

Highlight Animation

The highlight animation options control what happens when the mouse is placed over an object

  • Attack Rate - The speed at which items highlight when the mouse is placed over the object.
  • Release Rate - The speed at which an object highlight will disappear.

Multi-Sampling

Allows to change the anti-aliasing of text on the display providing your graphics card supports the options.